* Patch by Travis Sawyer, 01 Mar 2004:

  Ocotea:
  - Add IBM PPC440GX Ref Platform support (Ocotea)
    Original code by Paul Reynolds <PaulReynolds@lhsolutions.com>
    Adapted to U-Boot and 440GX port
  440gx_enet.c:
  - Add gracious handling of all Ethernet Pin Selections for 440GX
  - Add RGMII selection for Cicada CIS8201 Gigabit PHY
  ppc440.h:
  - Add needed bit definitions
  - Fix formatting

* Patch by Carl Riechers, 1 Mar 2004:
  Add PPC440GX prbdv0 divider to fix memory clock calculation.

* Patch by Stephan Linz, 27 Feb 2004
  - avoid problems for targets without NFS download support

17 files changed, 2472 insertions, 106 deletions

diff --git a/CHANGELOG b/CHANGELOG
index a282c85..9e3f9be 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,24 @@
 Changes for U-Boot 1.0.2:
 ======================================================================
 
+* Patch by Travis Sawye, 01 Mar 2004:
+  Ocotea:
+  - Add IBM PPC440GX Ref Platform support (Ocotea)
+    Original code by Paul Reynolds <PaulReynolds@lhsolutions.com>
+    Adapted to U-Boot and 440GX port
+  440gx_enet.c:
+  - Add gracious handling of all Ethernet Pin Selections for 440GX
+  - Add RGMII selection for Cicada CIS8201 Gigabit PHY
+  ppc440.h:
+  - Add needed bit definitions
+  - Fix formatting
+
+* Patch by Carl Riechers, 1 Mar 2004:
+  Add PPC440GX prbdv0 divider to fix memory clock calculation.
+
+* Patch by Stephan Linz, 27 Feb 2004
+  - avoid problems for targets without NFS download support
+
 * Patch by Rune Torgersen, 27 Feb 2004:
   - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
   - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
diff --git a/MAKEALL b/MAKEALL
index dec6f53..ddc863c 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -61,10 +61,10 @@ LIST_4xx="	\
 	CPCI440		CPCIISER4	CRAYL1		csb272		\
 	DASA_SIM	DP405		DU405		EBONY		\
 	ERIC		EXBITGEN	HUB405		MIP405		\
-	MIP405T		ML2		ml300		OCRTC		\
-	ORSG		PCI405		PIP405		PLU405		\
-	PMC405		PPChameleonEVB	VOH405		W7OLMC		\
-	W7OLMG		WALNUT405	XPEDITE1K			\
+	MIP405T		ML2		ml300		OCOTEA		\
+	OCRTC		ORSG		PCI405		PIP405		\
+	PLU405		PMC405		PPChameleonEVB	VOH405		\
+	W7OLMC		W7OLMG		WALNUT405	XPEDITE1K	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 2e862bf..4be1aff 100644
--- a/Makefile
+++ b/Makefile
@@ -597,6 +597,9 @@ ML2_config:unconfig
 ml300_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
 
+OCOTEA_config:unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx ocotea
+
 OCRTC_config		\
 ORSG_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd
diff --git a/board/ocotea/Makefile b/board/ocotea/Makefile
new file mode 100644
index 0000000..af223d2
--- /dev/null
+++ b/board/ocotea/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/ocotea/config.mk b/board/ocotea/config.mk
new file mode 100644
index 0000000..a71dbac
--- /dev/null
+++ b/board/ocotea/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IBM 440GX Reference Platform (Ocotea) board
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/ocotea/flash.c b/board/ocotea/flash.c
new file mode 100644
index 0000000..15e688f
--- /dev/null
+++ b/board/ocotea/flash.c
@@ -0,0 +1,595 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+#define     BOOT_SMALL_FLASH        32	/* 00100000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
+
+#define     BOOT_SMALL_FLASH_VAL    4
+#define     FLASH_ONBD_N_VAL        2
+#define     FLASH_SRAM_SEL_VAL      1
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+	{0xFF800000, 0xFF900000, 0xFFC00000},	/* 0:000: configuraton 4 */
+	{0xFF900000, 0xFF800000, 0xFFC00000},	/* 1:001: configuraton 3 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 2:010: configuraton 8 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 3:011: configuraton 7 */
+	{0xFFE00000, 0xFFF00000, 0xFF800000},	/* 4:100: configuraton 2 */
+	{0xFFF00000, 0xFFF80000, 0xFF800000},	/* 5:101: configuraton 1 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 6:110: configuraton 6 */
+	{0x00000000, 0x00000000, 0x00000000}	/* 7:111: configuraton 5 */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+
+#ifdef CONFIG_OCOTEA
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned short index = 0;
+	int i;
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	/* check the bitmap of switch status */
+	if (switch_status & BOOT_SMALL_FLASH) {
+		index += BOOT_SMALL_FLASH_VAL;
+	}
+	if (switch_status & FLASH_ONBD_N) {
+		index += FLASH_ONBD_N_VAL;
+	}
+	if (switch_status & FLASH_SRAM_SEL) {
+		index += FLASH_SRAM_SEL_VAL;
+	}
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AMDLV033C:
+		printf("AM29LV033C (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+	       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *) info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned) addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	udelay(10000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	udelay(1000);
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+	udelay(1000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);		/* no or unknown flash  */
+	}
+
+	value = addr2[1];		/* device ID            */
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;			/* => 4 MB              */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);		/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040) ||
+	    (info->flash_id == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr =
+		(FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+			printf("Erasing sector %p\n", addr2);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);		/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+	    for (i = 0, cp = wp; i < l; ++i, ++cp) {
+		    data = (data << 8) | (*(uchar *) cp);
+	    }
+	    for (; i < 4 && cnt > 0; ++i) {
+		    data = (data << 8) | *src++;
+		    --cnt;
+		    ++cp;
+	    }
+	    for (; cnt == 0 && i < 4; ++i, ++cp) {
+		    data = (data << 8) | (*(uchar *) cp);
+	    }
+
+	    if ((rc = write_word(info, wp, data)) != 0) {
+		    return (rc);
+	    }
+	    wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/board/ocotea/init.S b/board/ocotea/init.S
new file mode 100644
index 0000000..385afb5
--- /dev/null
+++ b/board/ocotea/init.S
@@ -0,0 +1,96 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)	( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+    tlbtab_end
diff --git a/board/ocotea/ocotea.c b/board/ocotea/ocotea.c
new file mode 100644
index 0000000..4324e57
--- /dev/null
+++ b/board/ocotea/ocotea.c
@@ -0,0 +1,459 @@
+/*
+ *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include "ocotea.h"
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <440gx_enet.h>
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+long int fixed_sdram (void);
+void fpga_init (void);
+
+int board_early_init_f (void)
+{
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------------*/
+	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
+	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+	/*-------------------------------------------------------------------------+
+	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
+	      EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | 4 MB FLASH. Initialize bank 2 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
+	      EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	fpga_init();
+
+	return 0;
+}
+
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+	printf ("Board: IBM 440GX Evaluation Board\n");
+	printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram (0);
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    128 MB, non-ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0         */
+	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0                 */
+	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (mem_tr0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3                       */
+	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
+	mtsdram (mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_cfg0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
+	for (;;) {
+		mfsdram (mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB                           */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 *	The ocotea board is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *--------------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+    /* The ocotea board is always configured as host. */
+    return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+
+void fpga_init(void)
+{
+	unsigned long group;
+	unsigned long sdr0_pfc0;
+	unsigned long sdr0_pfc1;
+	unsigned long sdr0_cust0;
+	unsigned long pvr;
+
+	mfsdr (sdr_pfc0, sdr0_pfc0);
+	mfsdr (sdr_pfc1, sdr0_pfc1);
+	group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
+	pvr = get_pvr ();
+
+	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
+	if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
+		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+		out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+		     FPGA_REG2_EXT_INTFACE_ENABLE);
+		mtsdr (sdr_pfc0, sdr0_pfc0);
+		mtsdr (sdr_pfc1, sdr0_pfc1);
+	} else {
+		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
+		switch (group)
+		{
+		case 0:
+		case 1:
+		case 2:
+			/* CPU trace A */
+			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+			     FPGA_REG2_EXT_INTFACE_ENABLE);
+			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+			mtsdr (sdr_pfc0, sdr0_pfc0);
+			mtsdr (sdr_pfc1, sdr0_pfc1);
+			break;
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+			/* CPU trace B - Over EBMI */
+			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
+			mtsdr (sdr_pfc0, sdr0_pfc0);
+			mtsdr (sdr_pfc1, sdr0_pfc1);
+			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+			     FPGA_REG2_EXT_INTFACE_DISABLE);
+			break;
+		}
+	}
+
+	/* Initialize the ethernet specific functions in the fpga */
+	mfsdr(sdr_pfc1, sdr0_pfc1);
+	mfsdr(sdr_cust0, sdr0_cust0);
+	if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
+	    ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
+	     (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+			     FPGA_REG3_ENET_GROUP7);
+		}
+		else
+		{
+			if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
+			{
+				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+				     FPGA_REG3_ENET_GROUP7);
+			}
+			else
+			{
+				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+				     FPGA_REG3_ENET_GROUP8);
+			}
+		}
+	}
+	else
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+			     FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+		}
+		else
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+			     FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+		}
+	}
+	out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
+	     FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
+	     FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
+
+	/* reset the gigabyte phy if necessary */
+	if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
+			udelay(10000);
+			out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
+		}
+		else
+		{
+			out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
+			udelay(10000);
+			out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
+		}
+	}
+
+	/* Turn off the LED's */
+	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
+	     FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
+	     FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
+
+	return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+#endif
+
diff --git a/board/ocotea/ocotea.h b/board/ocotea/ocotea.h
new file mode 100644
index 0000000..41bd450
--- /dev/null
+++ b/board/ocotea/ocotea.h
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Board specific FPGA stuff ... */
+#define FPGA_REG0                       (CFG_FPGA_BASE + 0x00)
+#define   FPGA_REG0_SSCG_MASK             0x80
+#define   FPGA_REG0_SSCG_DISABLE          0x00
+#define   FPGA_REG0_SSCG_ENABLE           0x80
+#define   FPGA_REG0_BOOT_MASK             0x40
+#define   FPGA_REG0_BOOT_LARGE_FLASH      0x00
+#define   FPGA_REG0_BOOT_SMALL_FLASH      0x40
+#define   FPGA_REG0_ECLS_MASK             0x38  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_0                0x20  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_1                0x10  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_2                0x08  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER1             0x00  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER3             0x08  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER4             0x10  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER5             0x18  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER2             0x20  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER6             0x28  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER7             0x30  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER8             0x38  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ARBITER_MASK          0x04
+#define   FPGA_REG0_ARBITER_EXT           0x00
+#define   FPGA_REG0_ARBITER_INT           0x04
+#define   FPGA_REG0_ONBOARD_FLASH_MASK    0x02
+#define   FPGA_REG0_ONBOARD_FLASH_ENABLE  0x00
+#define   FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
+#define   FPGA_REG0_FLASH                 0x01
+#define FPGA_REG1                       (CFG_FPGA_BASE + 0x01)
+#define   FPGA_REG1_9772_FSELFBX_MASK     0x80
+#define   FPGA_REG1_9772_FSELFBX_6        0x00
+#define   FPGA_REG1_9772_FSELFBX_10       0x80
+#define   FPGA_REG1_9531_SX_MASK          0x60
+#define   FPGA_REG1_9531_SX_33MHZ         0x00
+#define   FPGA_REG1_9531_SX_100MHZ        0x20
+#define   FPGA_REG1_9531_SX_66MHZ         0x40
+#define   FPGA_REG1_9531_SX_133MHZ        0x60
+#define   FPGA_REG1_9772_FSELBX_MASK      0x18
+#define   FPGA_REG1_9772_FSELBX_4         0x00
+#define   FPGA_REG1_9772_FSELBX_6         0x08
+#define   FPGA_REG1_9772_FSELBX_8         0x10
+#define   FPGA_REG1_9772_FSELBX_10        0x18
+#define   FPGA_REG1_SOURCE_MASK           0x07
+#define   FPGA_REG1_SOURCE_TC             0x00
+#define   FPGA_REG1_SOURCE_66MHZ          0x01
+#define   FPGA_REG1_SOURCE_50MHZ          0x02
+#define   FPGA_REG1_SOURCE_33MHZ          0x03
+#define   FPGA_REG1_SOURCE_25MHZ          0x04
+#define   FPGA_REG1_SOURCE_SSDIV1         0x05
+#define   FPGA_REG1_SOURCE_SSDIV2         0x06
+#define   FPGA_REG1_SOURCE_SSDIV4         0x07
+#define FPGA_REG2                       (CFG_FPGA_BASE + 0x02)
+#define   FPGA_REG2_TC0                   0x80
+#define   FPGA_REG2_TC1                   0x40
+#define   FPGA_REG2_TC2                   0x20
+#define   FPGA_REG2_TC3                   0x10
+#define   FPGA_REG2_GIGABIT_RESET_DISABLE 0x08   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG2_EXT_INTFACE_MASK      0x04
+#define   FPGA_REG2_EXT_INTFACE_ENABLE    0x00
+#define   FPGA_REG2_EXT_INTFACE_DISABLE   0x04
+#define   FPGA_REG2_DEFAULT_UART1_N       0x01
+#define FPGA_REG3                       (CFG_FPGA_BASE + 0x03)
+#define   FPGA_REG3_GIGABIT_RESET_DISABLE 0x80   /*Use on Ocotea pass 1 boards*/
+#define   FPGA_REG3_ENET_MASK1            0x70   /*Use on Ocotea pass 1 boards*/
+#define   FPGA_REG3_ENET_MASK2            0xF0   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG3_ENET_GROUP0           0x00
+#define   FPGA_REG3_ENET_GROUP1           0x10
+#define   FPGA_REG3_ENET_GROUP2           0x20
+#define   FPGA_REG3_ENET_GROUP3           0x30
+#define   FPGA_REG3_ENET_GROUP4           0x40
+#define   FPGA_REG3_ENET_GROUP5           0x50
+#define   FPGA_REG3_ENET_GROUP6           0x60
+#define   FPGA_REG3_ENET_GROUP7           0x70
+#define   FPGA_REG3_ENET_GROUP8           0x80   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/
+#define   FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/
+#define   FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/
+#define   FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/
+#define   FPGA_REG3_STAT_MASK             0x0F
+#define   FPGA_REG3_STAT_LED8_ENAB        0x08
+#define   FPGA_REG3_STAT_LED4_ENAB        0x04
+#define   FPGA_REG3_STAT_LED2_ENAB        0x02
+#define   FPGA_REG3_STAT_LED1_ENAB        0x01
+#define   FPGA_REG3_STAT_LED8_DISAB       0x00
+#define   FPGA_REG3_STAT_LED4_DISAB       0x00
+#define   FPGA_REG3_STAT_LED2_DISAB       0x00
+#define   FPGA_REG3_STAT_LED1_DISAB       0x00
+#define FPGA_REG4                       (CFG_FPGA_BASE + 0x04)
+#define   FPGA_REG4_GPHY_MODE10           0x80
+#define   FPGA_REG4_GPHY_MODE100          0x40
+#define   FPGA_REG4_GPHY_MODE1000         0x20
+#define   FPGA_REG4_GPHY_FRC_DPLX         0x10
+#define   FPGA_REG4_GPHY_ANEG_DIS         0x08
+#define   FPGA_REG4_CONNECT_PHYS          0x04
+
+
+#define   SDR0_CUST0_ENET3_MASK         0x00000080
+#define   SDR0_CUST0_ENET3_COPPER       0x00000000
+#define   SDR0_CUST0_ENET3_FIBER        0x00000080
+#define   SDR0_CUST0_RGMII3_MASK        0x00000070
+#define   SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
+#define   SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
+#define   SDR0_CUST0_RGMII3_DISAB       0x00000000
+#define   SDR0_CUST0_RGMII3_RTBI        0x00000040
+#define   SDR0_CUST0_RGMII3_RGMII       0x00000050
+#define   SDR0_CUST0_RGMII3_TBI         0x00000060
+#define   SDR0_CUST0_RGMII3_GMII        0x00000070
+#define   SDR0_CUST0_ENET2_MASK         0x00000008
+#define   SDR0_CUST0_ENET2_COPPER       0x00000000
+#define   SDR0_CUST0_ENET2_FIBER        0x00000008
+#define   SDR0_CUST0_RGMII2_MASK        0x00000007
+#define   SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+#define   SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
+#define   SDR0_CUST0_RGMII2_DISAB       0x00000000
+#define   SDR0_CUST0_RGMII2_RTBI        0x00000004
+#define   SDR0_CUST0_RGMII2_RGMII       0x00000005
+#define   SDR0_CUST0_RGMII2_TBI         0x00000006
+#define   SDR0_CUST0_RGMII2_GMII        0x00000007
diff --git a/board/ocotea/u-boot.lds b/board/ocotea/u-boot.lds
new file mode 100644
index 0000000..8a54617
--- /dev/null
+++ b/board/ocotea/u-boot.lds
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/ocotea/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/440gx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ocotea/u-boot.lds.debug b/board/ocotea/u-boot.lds.debug
new file mode 100644
index 0000000..41534de
--- /dev/null
+++ b/board/ocotea/u-boot.lds.debug
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/ocotea/init.o (.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/440gx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c
index c8259b1..ba7418a 100644
--- a/cpu/ppc4xx/440gx_enet.c
+++ b/cpu/ppc4xx/440gx_enet.c
@@ -187,6 +187,11 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	unsigned short devnum;
 	unsigned short reg_short;
 	sys_info_t sysinfo;
+#if defined (CONFIG_440_GX)
+	unsigned long pfc1;
+	unsigned long zmiifer;
+	unsigned long rmiifer;
+#endif
 
 	EMAC_440GX_HW_PST hw_p = dev->priv;
 
@@ -262,17 +267,84 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	reg = 0;
 	out32 (ZMII_FER, 0);
 	udelay (100);
-	out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
-	out32 (ZMII_SSR, 0x11110000);
-	/* reset emac so we have access to the phy */
-	__asm__ volatile ("eieio");
 
-	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-	__asm__ volatile ("eieio");
+#if defined(CONFIG_440_GX)
+	mfsdr(sdr_pfc1, pfc1);
+	pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
 
-	if ((devnum == 2) || (devnum == 3))
+	switch (pfc1) {
+	case 1:
+		zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
+		rmiifer = 0x0;
+		break;
+	case 2:
+		zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V(devnum);
+		rmiifer = 0x0;
+		break;
+	case 3:
+		if (devnum == 0) {
+			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
+			rmiifer = 0x0;
+		} else if (devnum == 2) {
+			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
+			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
+		} else { /* invalid case */
+			zmiifer = 0x0;
+			rmiifer = 0x0;
+		}
+		break;
+	case 4:
+		if ((devnum == 0) || (devnum == 1)) {
+			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
+			rmiifer = 0x0;
+		} else { /* ((devnum == 2) || (devnum == 3)) */
+			zmiifer = (ZMII_FER_MDI/* | ZMII_FER_RMII */) << ZMII_FER_V (devnum);
+			rmiifer = RGMII_FER_RGMII << RGMII_FER_V (devnum);
+		}
+		break;
+	case 5:
+		if ((devnum == 0) || (devnum == 1) || (devnum == 2)) {
+			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
+			rmiifer = 0x0;
+		} else {
+			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
+			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
+		}
+		break;
+	case 6:
+		if ((devnum == 0) || (devnum == 1)) {
+			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
+			rmiifer = 0x0;
+		} else {
+			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
+			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
+		}
+		break;
+	case 0:
+	default:
+		zmiifer = (ZMII_FER_MDI | ZMII_FER_MII) << ZMII_FER_V(devnum);
+		rmiifer = 0x0;
+		break;
+	}
+
+	out32 (ZMII_FER, zmiifer);
+	out32 (RGMII_FER, rmiifer);
+#else
+	if ((devnum == 0) || (devnum == 1)) {
+		out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+	}
+	else { /* ((devnum == 2) || (devnum == 3)) */
+		out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
 		out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
 				   (RGMII_FER_RGMII << RGMII_FER_V (3))));
+	}
+#endif
+	out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
+	__asm__ volatile ("eieio");
+
+	/* reset emac so we have access to the phy */
+
+	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
 	__asm__ volatile ("eieio");
 
 	failsafe = 1000;
@@ -325,6 +397,16 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	/* Reset the phy */
 	miiphy_reset (reg);
 
+#if defined(CONFIG_CIS8201_PHY)
+	/*
+	 * Cicada 8201 PHY needs to have an extended register whacked
+	 * for RGMII mode.
+	 */
+	if ( ((devnum == 2) || (devnum ==3)) && (4 == pfc1) ) {
+		miiphy_write (reg, 23, 0x1200);
+	}
+#endif
+
 	/* Start/Restart autonegotiation */
 	phy_setup_aneg (reg);
 	udelay (1000);
@@ -332,7 +414,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	miiphy_read (reg, PHY_BMSR, &reg_short);
 
 	/*
-	 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
+	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
 	 */
 	if ((reg_short & PHY_BMSR_AUTN_ABLE)
 	    && !(reg_short & PHY_BMSR_AUTN_COMP)) {
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index e776050..7172fe3 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -247,7 +247,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	unsigned long temp1;
 	unsigned long lfdiv;
 	unsigned long m;
-
+	unsigned long prbdv0;    
 
 	/* Extract configured divisors */
 	mfsdr( sdr_sdstp0,strp0 );
@@ -263,6 +263,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	sysInfo->pllOpbDiv = temp ? temp : 4;
 	temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
 	sysInfo->pllExtBusDiv = temp ? temp : 4;
+	prbdv0 = (strp0 >> 2) & 0x7;
 
 	/* Calculate 'M' based on feedback source */
 	temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
@@ -284,7 +285,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	/* Now calculate the individual clocks */
 	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
-	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
+	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
 	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 
diff --git a/include/configs/OCOTEA.h b/include/configs/OCOTEA.h
new file mode 100644
index 0000000..0b1873e
--- /dev/null
+++ b/include/configs/OCOTEA.h
@@ -0,0 +1,248 @@
+/*
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * 1 March 2004  Travis B. Sawyer <tsawyer@sandburst.com>
+ * Adapted to current Das U-Boot source
+ ***********************************************************************/
+
+
+/************************************************************************
+ * OCOTEA.h - configuration for IBM 440GX Ref (Ocotea)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_OCOTEA		1	    /* Board is ebony		*/
+#define CONFIG_440_GX           1           /* Specifc GX support       */
+#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
+#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CFG_MONITOR_BASE    0xfff80000	    /* start of monitor		*/
+#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+
+#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM  1
+#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	64		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM       1        /* Use SPD EEPROM for setup     */
+#define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES    {0x69}  /* Don't probe these addrs */
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_NVRAM	1	    /* Environment uses NVRAM	*/
+#undef	CFG_ENV_IS_IN_FLASH		    /* ... not in flash		*/
+#undef	CFG_ENV_IS_IN_EEPROM		    /* ... not in EEPROM	*/
+#define CONFIG_ENV_OVERWRITE    1
+
+#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+
+#define CONFIG_BOOTARGS		"root=/dev/hda1 "
+#define CONFIG_BOOTCOMMAND	"bootm ffc00000"    /* autoboot command */
+#define CONFIG_BOOTDELAY	-1		    /* disable autoboot */
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR        2
+#define CONFIG_PHY2_ADDR        0x10
+#define CONFIG_PHY3_ADDR        0x18
+#define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR           10.1.2.3
+#define CONFIG_ETHADDR          00:04:AC:E3:28:8A
+#define CONFIG_ETHADDR1         00:04:AC:E3:28:8B
+#define CONFIG_ETHADDR2         00:04:AC:E3:28:8C
+#define CONFIG_ETHADDR3         00:04:AC:E3:28:8D
+#define CFG_RX_ETH_BUFFER       32        /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SERVERIP         10.1.2.2
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_KGDB	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_BEDBUG	| \
+                                CFG_CMD_PING    | \
+				CFG_CMD_DIAG    | \
+                                CFG_CMD_MII     | \
+                                CFG_CMD_NET     | \
+				CFG_CMD_ELF	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		100		/* decrementer freq: 1 ms ticks */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			            /* include pci support	        */
+#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/ppc440.h b/include/ppc440.h
index 6eb33f1..69766de 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -571,6 +571,329 @@
 #endif /* CONFIG_440_GX */
 
 /*-----------------------------------------------------------------------------+
+|  External Bus Controller Bit Settings
++-----------------------------------------------------------------------------*/
+#define EBC_CFGADDR_MASK                0x0000003F
+
+#define EBC_BXCR_BAS_ENCODE(n) 	((((unsigned long)(n))&0xFFF00000)<<0)
+#define EBC_BXCR_BS_MASK  		0x000E0000
+#define EBC_BXCR_BS_1MB   		0x00000000
+#define EBC_BXCR_BS_2MB   		0x00020000
+#define EBC_BXCR_BS_4MB   		0x00040000
+#define EBC_BXCR_BS_8MB   		0x00060000
+#define EBC_BXCR_BS_16MB  		0x00080000
+#define EBC_BXCR_BS_32MB  		0x000A0000
+#define EBC_BXCR_BS_64MB  		0x000C0000
+#define EBC_BXCR_BS_128MB 		0x000E0000
+#define EBC_BXCR_BU_MASK  		0x00018000
+#define EBC_BXCR_BU_R     		0x00008000
+#define EBC_BXCR_BU_W     		0x00010000
+#define EBC_BXCR_BU_RW    		0x00018000
+#define EBC_BXCR_BW_MASK  		0x00006000
+#define EBC_BXCR_BW_8BIT  		0x00000000
+#define EBC_BXCR_BW_16BIT 		0x00002000
+
+#define EBC_BXAP_BME_ENABLED   	0x80000000
+#define EBC_BXAP_BME_DISABLED  	0x00000000
+#define EBC_BXAP_TWT_ENCODE(n)  	((((unsigned long)(n))&0xFF)<<23)
+#define EBC_BXAP_BCE_DISABLE           0x00000000
+#define EBC_BXAP_BCE_ENABLE            0x00400000
+#define EBC_BXAP_CSN_ENCODE(n)  	((((unsigned long)(n))&0x3)<<18)
+#define EBC_BXAP_OEN_ENCODE(n)  	((((unsigned long)(n))&0x3)<<16)
+#define EBC_BXAP_WBN_ENCODE(n)  	((((unsigned long)(n))&0x3)<<14)
+#define EBC_BXAP_WBF_ENCODE(n)  	((((unsigned long)(n))&0x3)<<12)
+#define EBC_BXAP_TH_ENCODE(n)   	((((unsigned long)(n))&0x7)<<9)
+#define EBC_BXAP_RE_ENABLED    	0x00000100
+#define EBC_BXAP_RE_DISABLED   	0x00000000
+#define EBC_BXAP_SOR_DELAYED   	0x00000000
+#define EBC_BXAP_SOR_NONDELAYED  	0x00000080
+#define EBC_BXAP_BEM_WRITEONLY 	0x00000000
+#define EBC_BXAP_BEM_RW                0x00000040
+#define EBC_BXAP_PEN_DISABLED  	0x00000000
+
+#define EBC_CFG_LE_MASK      		0x80000000
+#define EBC_CFG_LE_UNLOCK    		0x00000000
+#define EBC_CFG_LE_LOCK    		0x80000000
+#define EBC_CFG_PTD_MASK       	0x40000000
+#define EBC_CFG_PTD_ENABLE     	0x00000000
+#define EBC_CFG_PTD_DISABLE    	0x40000000
+#define EBC_CFG_RTC_MASK               0x38000000
+#define EBC_CFG_RTC_16PERCLK   	0x00000000
+#define EBC_CFG_RTC_32PERCLK           0x08000000
+#define EBC_CFG_RTC_64PERCLK           0x10000000
+#define EBC_CFG_RTC_128PERCLK          0x18000000
+#define EBC_CFG_RTC_256PERCLK          0x20000000
+#define EBC_CFG_RTC_512PERCLK          0x28000000
+#define EBC_CFG_RTC_1024PERCLK         0x30000000
+#define EBC_CFG_RTC_2048PERCLK         0x38000000
+#define EBC_CFG_ATC_MASK               0x04000000
+#define EBC_CFG_ATC_HI                 0x00000000
+#define EBC_CFG_ATC_PREVIOUS           0x04000000
+#define EBC_CFG_DTC_MASK               0x02000000
+#define EBC_CFG_DTC_HI                 0x00000000
+#define EBC_CFG_DTC_PREVIOUS           0x02000000
+#define EBC_CFG_CTC_MASK               0x01000000
+#define EBC_CFG_CTC_HI                 0x00000000
+#define EBC_CFG_CTC_PREVIOUS           0x01000000
+#define EBC_CFG_OEO_MASK               0x00800000
+#define EBC_CFG_OEO_HI                 0x00000000
+#define EBC_CFG_OEO_PREVIOUS           0x00800000
+#define EBC_CFG_EMC_MASK       	0x00400000
+#define EBC_CFG_EMC_NONDEFAULT 	0x00000000
+#define EBC_CFG_EMC_DEFAULT    	0x00400000
+#define EBC_CFG_PME_MASK       	0x00200000
+#define EBC_CFG_PME_DISABLE    	0x00000000
+#define EBC_CFG_PME_ENABLE     	0x00200000
+#define EBC_CFG_PMT_MASK               0x001F0000
+#define EBC_CFG_PMT_ENCODE(n)  	((((unsigned long)(n))&0x1F)<<12)
+#define EBC_CFG_PR_MASK                0x0000C000
+#define EBC_CFG_PR_16                  0x00000000
+#define EBC_CFG_PR_32                  0x00004000
+#define EBC_CFG_PR_64                  0x00008000
+#define EBC_CFG_PR_128                 0x0000C000
+
+/*-----------------------------------------------------------------------------+
+|  SDR 0 Bit Settings
++-----------------------------------------------------------------------------*/
+#define SDR0_SDSTP0_ENG_MASK         0x80000000
+#define SDR0_SDSTP0_ENG_PLLDIS       0x00000000
+#define SDR0_SDSTP0_ENG_PLLENAB      0x80000000
+#define SDR0_SDSTP0_ENG_ENCODE(n)    ((((unsigned long)(n))&0x01)<<31)
+#define SDR0_SDSTP0_ENG_DECODE(n)    ((((unsigned long)(n))>>31)&0x01)
+#define SDR0_SDSTP0_SRC_MASK         0x40000000
+#define SDR0_SDSTP0_SRC_PLLOUTA      0x00000000
+#define SDR0_SDSTP0_SRC_PLLOUTB      0x40000000
+#define SDR0_SDSTP0_SRC_ENCODE(n)    ((((unsigned long)(n))&0x01)<<30)
+#define SDR0_SDSTP0_SRC_DECODE(n)    ((((unsigned long)(n))>>30)&0x01)
+#define SDR0_SDSTP0_SEL_MASK         0x38000000
+#define SDR0_SDSTP0_SEL_PLLOUT       0x00000000
+#define SDR0_SDSTP0_SEL_CPU          0x08000000
+#define SDR0_SDSTP0_SEL_EBC          0x28000000
+#define SDR0_SDSTP0_SEL_ENCODE(n)    ((((unsigned long)(n))&0x07)<<27)
+#define SDR0_SDSTP0_SEL_DECODE(n)    ((((unsigned long)(n))>>27)&0x07)
+#define SDR0_SDSTP0_TUNE_MASK        0x07FE0000
+#define SDR0_SDSTP0_TUNE_ENCODE(n)   ((((unsigned long)(n))&0x3FF)<<17)
+#define SDR0_SDSTP0_TUNE_DECODE(n)   ((((unsigned long)(n))>>17)&0x3FF)
+#define SDR0_SDSTP0_FBDV_MASK        0x0001F000
+#define SDR0_SDSTP0_FBDV_ENCODE(n)   ((((unsigned long)(n))&0x1F)<<12)
+#define SDR0_SDSTP0_FBDV_DECODE(n)   ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
+#define SDR0_SDSTP0_FWDVA_MASK       0x00000F00
+#define SDR0_SDSTP0_FWDVA_ENCODE(n)  ((((unsigned long)(n))&0x0F)<<8)
+#define SDR0_SDSTP0_FWDVA_DECODE(n)  ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
+#define SDR0_SDSTP0_FWDVB_MASK       0x000000E0
+#define SDR0_SDSTP0_FWDVB_ENCODE(n)  ((((unsigned long)(n))&0x07)<<5)
+#define SDR0_SDSTP0_FWDVB_DECODE(n)  ((((((unsigned long)(n))>>5)-1)&0x07)+1)
+#define SDR0_SDSTP0_PRBDV0_MASK      0x0000001C
+#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
+#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
+#define SDR0_SDSTP0_OPBDV0_MASK      0x00000003
+#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
+#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
+
+#define SDR0_SDSTP1_LFBDV_MASK       0xFC000000
+#define SDR0_SDSTP1_LFBDV_ENCODE(n)  ((((unsigned long)(n))&0x3F)<<26)
+#define SDR0_SDSTP1_LFBDV_DECODE(n)  ((((unsigned long)(n))>>26)&0x3F)
+#define SDR0_SDSTP1_EBCDV0_MASK      0x03000000
+#define SDR0_SDSTP1_EBCDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define SDR0_SDSTP1_EBCDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
+#define SDR0_SDSTP1_MALDV0_MASK      0x00C00000
+#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
+#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+#define SDR0_SDSTP1_RW_MASK          0x00300000
+#define SDR0_SDSTP1_RW_8BIT          0x00000000
+#define SDR0_SDSTP1_RW_16BIT         0x00100000
+#define SDR0_SDSTP1_RW_32BIT         0x00200000
+#define SDR0_SDSTP1_RW_ENCODE(n)     ((((unsigned long)(n))&0x03)<<20)
+#define SDR0_SDSTP1_RW_DECODE(n)     ((((unsigned long)(n))>>20)&0x03)
+#define SDR0_SDSTP1_EARV_MASK        0x00080000
+#define SDR0_SDSTP1_EARV_EBC         0x00000000
+#define SDR0_SDSTP1_EARV_PCI         0x00080000
+#define SDR0_SDSTP1_PAE_MASK         0x00040000
+#define SDR0_SDSTP1_PAE_DISABLE      0x00000000
+#define SDR0_SDSTP1_PAE_ENABLE       0x00040000
+#define SDR0_SDSTP1_PAE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<18)
+#define SDR0_SDSTP1_PAE_DECODE(n)    ((((unsigned long)(n))>>18)&0x01)
+#define SDR0_SDSTP1_PHCE_MASK        0x00020000
+#define SDR0_SDSTP1_PHCE_DISABLE     0x00000000
+#define SDR0_SDSTP1_PHCE_ENABLE      0x00020000
+#define SDR0_SDSTP1_PHCE_ENCODE(n)   ((((unsigned long)(n))&0x01)<<17)
+#define SDR0_SDSTP1_PHCE_DECODE(n)   ((((unsigned long)(n))>>17)&0x01)
+#define SDR0_SDSTP1_PISE_MASK        0x00010000
+#define SDR0_SDSTP1_PISE_DISABLE     0x00000000
+#define SDR0_SDSTP1_PISE_ENABLE      0x00010000
+#define SDR0_SDSTP1_PISE_ENCODE(n)   ((((unsigned long)(n))&0x01)<<16)
+#define SDR0_SDSTP1_PISE_DECODE(n)   ((((unsigned long)(n))>>16)&0x01)
+#define SDR0_SDSTP1_PCWE_MASK        0x00008000
+#define SDR0_SDSTP1_PCWE_DISABLE     0x00000000
+#define SDR0_SDSTP1_PCWE_ENABLE      0x00008000
+#define SDR0_SDSTP1_PCWE_ENCODE(n)   ((((unsigned long)(n))&0x01)<<15)
+#define SDR0_SDSTP1_PCWE_DECODE(n)   ((((unsigned long)(n))>>15)&0x01)
+#define SDR0_SDSTP1_PPIM_MASK        0x00008000
+#define SDR0_SDSTP1_PPIM_ENCODE(n)   ((((unsigned long)(n))&0x0F)<<11)
+#define SDR0_SDSTP1_PPIM_DECODE(n)   ((((unsigned long)(n))>>11)&0x0F)
+#define SDR0_SDSTP1_PR64E_MASK       0x00000400
+#define SDR0_SDSTP1_PR64E_DISABLE    0x00000000
+#define SDR0_SDSTP1_PR64E_ENABLE     0x00000400
+#define SDR0_SDSTP1_PR64E_ENCODE(n)  ((((unsigned long)(n))&0x01)<<10)
+#define SDR0_SDSTP1_PR64E_DECODE(n)  ((((unsigned long)(n))>>10)&0x01)
+#define SDR0_SDSTP1_PXFS_MASK        0x00000300
+#define SDR0_SDSTP1_PXFS_HIGH        0x00000000
+#define SDR0_SDSTP1_PXFS_MED         0x00000100
+#define SDR0_SDSTP1_PXFS_LOW         0x00000200
+#define SDR0_SDSTP1_PXFS_ENCODE(n)   ((((unsigned long)(n))&0x03)<<8)
+#define SDR0_SDSTP1_PXFS_DECODE(n)   ((((unsigned long)(n))>>8)&0x03)
+#define SDR0_SDSTP1_PDM_MASK         0x00000040
+#define SDR0_SDSTP1_PDM_MULTIPOINT   0x00000000
+#define SDR0_SDSTP1_PDM_P2P          0x00000040
+#define SDR0_SDSTP1_PDM_ENCODE(n)    ((((unsigned long)(n))&0x01)<<6)
+#define SDR0_SDSTP1_PDM_DECODE(n)    ((((unsigned long)(n))>>6)&0x01)
+#define SDR0_SDSTP1_EPS_MASK         0x00000038
+#define SDR0_SDSTP1_EPS_GROUP0       0x00000000
+#define SDR0_SDSTP1_EPS_GROUP1       0x00000008
+#define SDR0_SDSTP1_EPS_GROUP2       0x00000010
+#define SDR0_SDSTP1_EPS_GROUP3       0x00000018
+#define SDR0_SDSTP1_EPS_GROUP4       0x00000020
+#define SDR0_SDSTP1_EPS_GROUP5       0x00000028
+#define SDR0_SDSTP1_EPS_GROUP6       0x00000030
+#define SDR0_SDSTP1_EPS_GROUP7       0x00000038
+#define SDR0_SDSTP1_EPS_ENCODE(n)    ((((unsigned long)(n))&0x07)<<3)
+#define SDR0_SDSTP1_EPS_DECODE(n)    ((((unsigned long)(n))>>3)&0x07)
+#define SDR0_SDSTP1_RMII_MASK        0x00000004
+#define SDR0_SDSTP1_RMII_100MBIT     0x00000000
+#define SDR0_SDSTP1_RMII_10MBIT      0x00000004
+#define SDR0_SDSTP1_RMII_ENCODE(n)   ((((unsigned long)(n))&0x01)<<2)
+#define SDR0_SDSTP1_RMII_DECODE(n)   ((((unsigned long)(n))>>2)&0x01)
+#define SDR0_SDSTP1_TRE_MASK         0x00000002
+#define SDR0_SDSTP1_TRE_DISABLE      0x00000000
+#define SDR0_SDSTP1_TRE_ENABLE       0x00000002
+#define SDR0_SDSTP1_TRE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<1)
+#define SDR0_SDSTP1_TRE_DECODE(n)    ((((unsigned long)(n))>>1)&0x01)
+#define SDR0_SDSTP1_NTO1_MASK        0x00000001
+#define SDR0_SDSTP1_NTO1_DISABLE     0x00000000
+#define SDR0_SDSTP1_NTO1_ENABLE      0x00000001
+#define SDR0_SDSTP1_NTO1_ENCODE(n)   ((((unsigned long)(n))&0x01)<<0)
+#define SDR0_SDSTP1_NTO1_DECODE(n)   ((((unsigned long)(n))>>0)&0x01)
+
+#define SDR0_EBC_RW_MASK             0x30000000
+#define SDR0_EBC_RW_8BIT             0x00000000
+#define SDR0_EBC_RW_16BIT            0x10000000
+#define SDR0_EBC_RW_32BIT            0x20000000
+#define SDR0_EBC_RW_ENCODE(n)        ((((unsigned long)(n))&0x03)<<28)
+#define SDR0_EBC_RW_DECODE(n)        ((((unsigned long)(n))>>28)&0x03)
+
+#define SDR0_UARTX_UXICS_MASK        0xF0000000
+#define SDR0_UARTX_UXICS_PLB         0x20000000
+#define SDR0_UARTX_UXEC_MASK         0x00800000
+#define SDR0_UARTX_UXEC_INT          0x00000000
+#define SDR0_UARTX_UXEC_EXT          0x00800000
+#define SDR0_UARTX_UXDTE_MASK        0x00400000
+#define SDR0_UARTX_UXDTE_DISABLE     0x00000000
+#define SDR0_UARTX_UXDTE_ENABLE      0x00400000
+#define SDR0_UARTX_UXDRE_MASK        0x00200000
+#define SDR0_UARTX_UXDRE_DISABLE     0x00000000
+#define SDR0_UARTX_UXDRE_ENABLE      0x00200000
+#define SDR0_UARTX_UXDC_MASK         0x00100000
+#define SDR0_UARTX_UXDC_NOTCLEARED   0x00000000
+#define SDR0_UARTX_UXDC_CLEARED      0x00100000
+#define SDR0_UARTX_UXDIV_MASK        0x000000FF
+#define SDR0_UARTX_UXDIV_ENCODE(n)   ((((unsigned long)(n))&0xFF)<<0)
+#define SDR0_UARTX_UXDIV_DECODE(n)   ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
+
+#define SDR0_CPU440_EARV_MASK        0x30000000
+#define SDR0_CPU440_EARV_EBC         0x10000000
+#define SDR0_CPU440_EARV_PCI         0x20000000
+#define SDR0_CPU440_EARV_ENCODE(n)   ((((unsigned long)(n))&0x03)<<28)
+#define SDR0_CPU440_EARV_DECODE(n)   ((((unsigned long)(n))>>28)&0x03)
+#define SDR0_CPU440_NTO1_MASK        0x00000002
+#define SDR0_CPU440_NTO1_NTOP        0x00000000
+#define SDR0_CPU440_NTO1_NTO1        0x00000002
+#define SDR0_CPU440_NTO1_ENCODE(n)   ((((unsigned long)(n))&0x01)<<1)
+#define SDR0_CPU440_NTO1_DECODE(n)   ((((unsigned long)(n))>>1)&0x01)
+
+#define SDR0_XCR_PAE_MASK            0x80000000
+#define SDR0_XCR_PAE_DISABLE         0x00000000
+#define SDR0_XCR_PAE_ENABLE          0x80000000
+#define SDR0_XCR_PAE_ENCODE(n)       ((((unsigned long)(n))&0x01)<<31)
+#define SDR0_XCR_PAE_DECODE(n)       ((((unsigned long)(n))>>31)&0x01)
+#define SDR0_XCR_PHCE_MASK           0x40000000
+#define SDR0_XCR_PHCE_DISABLE        0x00000000
+#define SDR0_XCR_PHCE_ENABLE         0x40000000
+#define SDR0_XCR_PHCE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<30)
+#define SDR0_XCR_PHCE_DECODE(n)      ((((unsigned long)(n))>>30)&0x01)
+#define SDR0_XCR_PISE_MASK           0x20000000
+#define SDR0_XCR_PISE_DISABLE        0x00000000
+#define SDR0_XCR_PISE_ENABLE         0x20000000
+#define SDR0_XCR_PISE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<29)
+#define SDR0_XCR_PISE_DECODE(n)      ((((unsigned long)(n))>>29)&0x01)
+#define SDR0_XCR_PCWE_MASK           0x10000000
+#define SDR0_XCR_PCWE_DISABLE        0x00000000
+#define SDR0_XCR_PCWE_ENABLE         0x10000000
+#define SDR0_XCR_PCWE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<28)
+#define SDR0_XCR_PCWE_DECODE(n)      ((((unsigned long)(n))>>28)&0x01)
+#define SDR0_XCR_PPIM_MASK           0x0F000000
+#define SDR0_XCR_PPIM_ENCODE(n)      ((((unsigned long)(n))&0x0F)<<24)
+#define SDR0_XCR_PPIM_DECODE(n)      ((((unsigned long)(n))>>24)&0x0F)
+#define SDR0_XCR_PR64E_MASK          0x00800000
+#define SDR0_XCR_PR64E_DISABLE       0x00000000
+#define SDR0_XCR_PR64E_ENABLE        0x00800000
+#define SDR0_XCR_PR64E_ENCODE(n)     ((((unsigned long)(n))&0x01)<<23)
+#define SDR0_XCR_PR64E_DECODE(n)     ((((unsigned long)(n))>>23)&0x01)
+#define SDR0_XCR_PXFS_MASK           0x00600000
+#define SDR0_XCR_PXFS_HIGH           0x00000000
+#define SDR0_XCR_PXFS_MED            0x00200000
+#define SDR0_XCR_PXFS_LOW            0x00400000
+#define SDR0_XCR_PXFS_ENCODE(n)      ((((unsigned long)(n))&0x03)<<21)
+#define SDR0_XCR_PXFS_DECODE(n)      ((((unsigned long)(n))>>21)&0x03)
+#define SDR0_XCR_PDM_MASK            0x00000040
+#define SDR0_XCR_PDM_MULTIPOINT      0x00000000
+#define SDR0_XCR_PDM_P2P             0x00000040
+#define SDR0_XCR_PDM_ENCODE(n)       ((((unsigned long)(n))&0x01)<<19)
+#define SDR0_XCR_PDM_DECODE(n)       ((((unsigned long)(n))>>19)&0x01)
+
+#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
+#define SDR0_PFC0_GEIE_MASK          0x00003E00
+#define SDR0_PFC0_GEIE_TRE           0x00003E00
+#define SDR0_PFC0_GEIE_NOTRE         0x00000000
+#define SDR0_PFC0_TRE_MASK           0x00000100
+#define SDR0_PFC0_TRE_DISABLE        0x00000000
+#define SDR0_PFC0_TRE_ENABLE         0x00000100
+#define SDR0_PFC0_TRE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<8)
+#define SDR0_PFC0_TRE_DECODE(n)      ((((unsigned long)(n))>>8)&0x01)
+
+#define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
+#define SDR0_PFC1_EPS_MASK           0x01C00000
+#define SDR0_PFC1_EPS_GROUP0         0x00000000
+#define SDR0_PFC1_EPS_GROUP1         0x00400000
+#define SDR0_PFC1_EPS_GROUP2         0x00800000
+#define SDR0_PFC1_EPS_GROUP3         0x00C00000
+#define SDR0_PFC1_EPS_GROUP4         0x01000000
+#define SDR0_PFC1_EPS_GROUP5         0x01400000
+#define SDR0_PFC1_EPS_GROUP6         0x01800000
+#define SDR0_PFC1_EPS_GROUP7         0x01C00000
+#define SDR0_PFC1_EPS_ENCODE(n)      ((((unsigned long)(n))&0x07)<<22)
+#define SDR0_PFC1_EPS_DECODE(n)      ((((unsigned long)(n))>>22)&0x07)
+#define SDR0_PFC1_RMII_MASK          0x00200000
+#define SDR0_PFC1_RMII_100MBIT       0x00000000
+#define SDR0_PFC1_RMII_10MBIT        0x00200000
+#define SDR0_PFC1_RMII_ENCODE(n)     ((((unsigned long)(n))&0x01)<<21)
+#define SDR0_PFC1_RMII_DECODE(n)     ((((unsigned long)(n))>>21)&0x01)
+#define SDR0_PFC1_CTEMS_MASK         0x00100000
+#define SDR0_PFC1_CTEMS_EMS          0x00000000
+#define SDR0_PFC1_CTEMS_CPUTRACE     0x00100000
+
+#define SDR0_MFR_TAH0_MASK           0x80000000
+#define SDR0_MFR_TAH0_ENABLE         0x00000000
+#define SDR0_MFR_TAH0_DISABLE        0x80000000
+#define SDR0_MFR_TAH1_MASK           0x40000000
+#define SDR0_MFR_TAH1_ENABLE         0x00000000
+#define SDR0_MFR_TAH1_DISABLE        0x40000000
+#define SDR0_MFR_PCM_MASK            0x20000000
+#define SDR0_MFR_PCM_PPC440GX        0x00000000
+#define SDR0_MFR_PCM_PPC440GP        0x20000000
+#define SDR0_MFR_ECS_MASK            0x10000000
+#define SDR0_MFR_ECS_INTERNAL        0x10000000
+
+/*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
 #if !defined (CONFIG_440_GX)
@@ -631,99 +954,99 @@
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
 '----------------------------------------------------------------------------*/
-#define	   IICMDBUF	    0x00
-#define	   IICSDBUF	    0x02
-#define	   IICLMADR	    0x04
-#define	   IICHMADR	    0x05
-#define	   IICCNTL	    0x06
-#define	   IICMDCNTL	    0x07
-#define	   IICSTS	    0x08
-#define	   IICEXTSTS	    0x09
-#define	   IICLSADR	    0x0A
-#define	   IICHSADR	    0x0B
-#define	   IICCLKDIV	    0x0C
-#define	   IICINTRMSK	    0x0D
-#define	   IICXFRCNT	    0x0E
-#define	   IICXTCNTLSS	    0x0F
-#define	   IICDIRECTCNTL    0x10
+#define IICMDBUF	    0x00
+#define IICSDBUF	    0x02
+#define IICLMADR	    0x04
+#define IICHMADR	    0x05
+#define IICCNTL	    0x06
+#define IICMDCNTL	    0x07
+#define IICSTS	            0x08
+#define IICEXTSTS	    0x09
+#define IICLSADR	    0x0A
+#define IICHSADR	    0x0B
+#define IICCLKDIV	    0x0C
+#define IICINTRMSK	    0x0D
+#define IICXFRCNT	    0x0E
+#define IICXTCNTLSS	    0x0F
+#define IICDIRECTCNTL      0x10
 
 /*-----------------------------------------------------------------------------
 | UART Register Offsets
 '----------------------------------------------------------------------------*/
-#define		DATA_REG	0x00
-#define		DL_LSB		0x00
-#define		DL_MSB		0x01
-#define		INT_ENABLE	0x01
-#define		FIFO_CONTROL	0x02
-#define		LINE_CONTROL	0x03
-#define		MODEM_CONTROL	0x04
-#define		LINE_STATUS	0x05
-#define		MODEM_STATUS	0x06
-#define		SCRATCH		0x07
+#define DATA_REG	0x00
+#define DL_LSB		0x00
+#define DL_MSB		0x01
+#define INT_ENABLE	0x01
+#define FIFO_CONTROL	0x02
+#define LINE_CONTROL	0x03
+#define MODEM_CONTROL	0x04
+#define LINE_STATUS	0x05
+#define MODEM_STATUS	0x06
+#define SCRATCH	0x07
 
 /*-----------------------------------------------------------------------------
 | PCI Internal Registers et. al. (accessed via plb)
 +----------------------------------------------------------------------------*/
-#define		PCIX0_CFGADR		(CFG_PCI_BASE + 0x0ec00000)
-#define		PCIX0_CFGDATA		(CFG_PCI_BASE + 0x0ec00004)
-#define		PCIX0_CFGBASE		(CFG_PCI_BASE + 0x0ec80000)
-#define		PCIX0_IOBASE		(CFG_PCI_BASE + 0x08000000)
-
-#define		PCIX0_VENDID		(PCIX0_CFGBASE + PCI_VENDOR_ID )
-#define		PCIX0_DEVID			(PCIX0_CFGBASE + PCI_DEVICE_ID )
-#define		PCIX0_CMD			(PCIX0_CFGBASE + PCI_COMMAND )
-#define		PCIX0_STATUS		(PCIX0_CFGBASE + PCI_STATUS )
-#define		PCIX0_REVID			(PCIX0_CFGBASE + PCI_REVISION_ID )
-#define		PCIX0_CLS			(PCIX0_CFGBASE + PCI_CLASS_CODE)
-#define		PCIX0_CACHELS		(PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
-#define		PCIX0_LATTIM		(PCIX0_CFGBASE + PCI_LATENCY_TIMER )
-#define		PCIX0_HDTYPE		(PCIX0_CFGBASE + PCI_HEADER_TYPE )
-#define		PCIX0_BIST			(PCIX0_CFGBASE + PCI_BIST )
-#define		PCIX0_BAR0			(PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
-#define		PCIX0_BAR1			(PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
-#define		PCIX0_BAR2			(PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
-#define		PCIX0_BAR3			(PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
-#define		PCIX0_BAR4			(PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
-#define		PCIX0_BAR5			(PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
-#define		PCIX0_CISPTR		(PCIX0_CFGBASE + PCI_CARDBUS_CIS )
-#define		PCIX0_SBSYSVID		(PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
-#define		PCIX0_SBSYSID		(PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
-#define		PCIX0_EROMBA		(PCIX0_CFGBASE + PCI_ROM_ADDRESS )
-#define		PCIX0_CAP			(PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
-#define		PCIX0_RES0			(PCIX0_CFGBASE + 0x0035 )
-#define		PCIX0_RES1			(PCIX0_CFGBASE + 0x0036 )
-#define		PCIX0_RES2			(PCIX0_CFGBASE + 0x0038 )
-#define		PCIX0_INTLN			(PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
-#define		PCIX0_INTPN			(PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
-#define		PCIX0_MINGNT		(PCIX0_CFGBASE + PCI_MIN_GNT )
-#define		PCIX0_MAXLTNCY		(PCIX0_CFGBASE + PCI_MAX_LAT )
-
-#define	    PCIX0_BRDGOPT1	(PCIX0_CFGBASE + 0x0040)
-#define	    PCIX0_BRDGOPT2	(PCIX0_CFGBASE + 0x0044)
-
-#define		PCIX0_POM0LAL		(PCIX0_CFGBASE + 0x0068)
-#define		PCIX0_POM0LAH		(PCIX0_CFGBASE + 0x006c)
-#define		PCIX0_POM0SA		(PCIX0_CFGBASE + 0x0070)
-#define		PCIX0_POM0PCIAL		(PCIX0_CFGBASE + 0x0074)
-#define		PCIX0_POM0PCIAH		(PCIX0_CFGBASE + 0x0078)
-#define		PCIX0_POM1LAL		(PCIX0_CFGBASE + 0x007c)
-#define		PCIX0_POM1LAH		(PCIX0_CFGBASE + 0x0080)
-#define		PCIX0_POM1SA		(PCIX0_CFGBASE + 0x0084)
-#define		PCIX0_POM1PCIAL		(PCIX0_CFGBASE + 0x0088)
-#define		PCIX0_POM1PCIAH		(PCIX0_CFGBASE + 0x008c)
-#define		PCIX0_POM2SA		(PCIX0_CFGBASE + 0x0090)
-
-#define		PCIX0_PIM0SA		(PCIX0_CFGBASE + 0x0098)
-#define		PCIX0_PIM0LAL		(PCIX0_CFGBASE + 0x009c)
-#define		PCIX0_PIM0LAH		(PCIX0_CFGBASE + 0x00a0)
-#define		PCIX0_PIM1SA		(PCIX0_CFGBASE + 0x00a4)
-#define		PCIX0_PIM1LAL		(PCIX0_CFGBASE + 0x00a8)
-#define		PCIX0_PIM1LAH		(PCIX0_CFGBASE + 0x00ac)
-#define		PCIX0_PIM2SA		(PCIX0_CFGBASE + 0x00b0)
-#define		PCIX0_PIM2LAL		(PCIX0_CFGBASE + 0x00b4)
-#define		PCIX0_PIM2LAH		(PCIX0_CFGBASE + 0x00b8)
-
-#define	    PCIX0_STS		(PCIX0_CFGBASE + 0x00e0)
+#define PCIX0_CFGADR		(CFG_PCI_BASE + 0x0ec00000)
+#define PCIX0_CFGDATA		(CFG_PCI_BASE + 0x0ec00004)
+#define PCIX0_CFGBASE		(CFG_PCI_BASE + 0x0ec80000)
+#define PCIX0_IOBASE		(CFG_PCI_BASE + 0x08000000)
+
+#define PCIX0_VENDID		(PCIX0_CFGBASE + PCI_VENDOR_ID )
+#define PCIX0_DEVID		(PCIX0_CFGBASE + PCI_DEVICE_ID )
+#define PCIX0_CMD		(PCIX0_CFGBASE + PCI_COMMAND )
+#define PCIX0_STATUS		(PCIX0_CFGBASE + PCI_STATUS )
+#define PCIX0_REVID		(PCIX0_CFGBASE + PCI_REVISION_ID )
+#define PCIX0_CLS		(PCIX0_CFGBASE + PCI_CLASS_CODE)
+#define PCIX0_CACHELS		(PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
+#define PCIX0_LATTIM		(PCIX0_CFGBASE + PCI_LATENCY_TIMER )
+#define PCIX0_HDTYPE		(PCIX0_CFGBASE + PCI_HEADER_TYPE )
+#define PCIX0_BIST		(PCIX0_CFGBASE + PCI_BIST )
+#define PCIX0_BAR0		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
+#define PCIX0_BAR1		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
+#define PCIX0_BAR2		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
+#define PCIX0_BAR3		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
+#define PCIX0_BAR4		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
+#define PCIX0_BAR5		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
+#define PCIX0_CISPTR		(PCIX0_CFGBASE + PCI_CARDBUS_CIS )
+#define PCIX0_SBSYSVID		(PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
+#define PCIX0_SBSYSID		(PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
+#define PCIX0_EROMBA		(PCIX0_CFGBASE + PCI_ROM_ADDRESS )
+#define PCIX0_CAP		(PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
+#define PCIX0_RES0		(PCIX0_CFGBASE + 0x0035 )
+#define PCIX0_RES1		(PCIX0_CFGBASE + 0x0036 )
+#define PCIX0_RES2		(PCIX0_CFGBASE + 0x0038 )
+#define PCIX0_INTLN		(PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
+#define PCIX0_INTPN		(PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
+#define PCIX0_MINGNT		(PCIX0_CFGBASE + PCI_MIN_GNT )
+#define PCIX0_MAXLTNCY		(PCIX0_CFGBASE + PCI_MAX_LAT )
+
+#define PCIX0_BRDGOPT1	        (PCIX0_CFGBASE + 0x0040)
+#define PCIX0_BRDGOPT2	        (PCIX0_CFGBASE + 0x0044)
+
+#define PCIX0_POM0LAL		(PCIX0_CFGBASE + 0x0068)
+#define PCIX0_POM0LAH		(PCIX0_CFGBASE + 0x006c)
+#define PCIX0_POM0SA		(PCIX0_CFGBASE + 0x0070)
+#define PCIX0_POM0PCIAL	(PCIX0_CFGBASE + 0x0074)
+#define PCIX0_POM0PCIAH	(PCIX0_CFGBASE + 0x0078)
+#define PCIX0_POM1LAL		(PCIX0_CFGBASE + 0x007c)
+#define PCIX0_POM1LAH		(PCIX0_CFGBASE + 0x0080)
+#define PCIX0_POM1SA		(PCIX0_CFGBASE + 0x0084)
+#define PCIX0_POM1PCIAL	(PCIX0_CFGBASE + 0x0088)
+#define PCIX0_POM1PCIAH	(PCIX0_CFGBASE + 0x008c)
+#define PCIX0_POM2SA		(PCIX0_CFGBASE + 0x0090)
+
+#define PCIX0_PIM0SA		(PCIX0_CFGBASE + 0x0098)
+#define PCIX0_PIM0LAL		(PCIX0_CFGBASE + 0x009c)
+#define PCIX0_PIM0LAH		(PCIX0_CFGBASE + 0x00a0)
+#define PCIX0_PIM1SA		(PCIX0_CFGBASE + 0x00a4)
+#define PCIX0_PIM1LAL		(PCIX0_CFGBASE + 0x00a8)
+#define PCIX0_PIM1LAH		(PCIX0_CFGBASE + 0x00ac)
+#define PCIX0_PIM2SA		(PCIX0_CFGBASE + 0x00b0)
+#define PCIX0_PIM2LAL		(PCIX0_CFGBASE + 0x00b4)
+#define PCIX0_PIM2LAH		(PCIX0_CFGBASE + 0x00b8)
+
+#define PCIX0_STS		(PCIX0_CFGBASE + 0x00e0)
 
 /*
  * Macros for accessing the indirect EBC registers
diff --git a/net/bootp.c b/net/bootp.c
index f5adce4..b760b88 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -339,12 +339,14 @@ BootpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
 			 */
 			NetState = NETLOOP_SUCCESS;
 			return;
+#if (CONFIG_COMMANDS & CFG_CMD_NFS)
 		} else if (strcmp(s, "NFS") == 0) {
 			/*
 			 * Use NFS to load the bootfile.
 			 */
 			NfsStart();
 			return;
+#endif
 		}
 	}
 
@@ -893,12 +895,14 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
 					 */
 					NetState = NETLOOP_SUCCESS;
 					return;
+#if (CONFIG_COMMANDS & CFG_CMD_NFS)
 				} else if (strcmp(s, "NFS") == 0) {
 					/*
 					 * Use NFS to load the bootfile.
 					 */
 					NfsStart();
 					return;
+#endif
 				}
 			}
 			TftpStart();
diff --git a/net/rarp.c b/net/rarp.c
index b8cc542..5f18d84 100644
--- a/net/rarp.c
+++ b/net/rarp.c
@@ -51,13 +51,20 @@ RarpHandler(uchar * dummi0, unsigned dummi1, unsigned dummi2, unsigned dummi3)
 #ifdef	DEBUG
 	printf("Got good RARP\n");
 #endif
-	if (((s = getenv("autoload")) != NULL) && (*s == 'n')) {
-		NetState = NETLOOP_SUCCESS;
-		return;
-	}
-	else if ((s != NULL) && !strcmp(s, "NFS")) {
-		NfsStart();
-		return;
+	if ((s = getenv("autoload")) != NULL) {
+		if (*s == 'n') {
+			/*
+			 * Just use RARP to configure system;
+			 * Do not use TFTP/NFS to to load the bootfile.
+			 */
+			NetState = NETLOOP_SUCCESS;
+			return;
+#if (CONFIG_COMMANDS & CFG_CMD_NFS)
+		} else if ((s != NULL) && !strcmp(s, "NFS")) {
+			NfsStart();
+			return;
+#endif
+		}
 	}
 	TftpStart ();
 }