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authorStefan Roese <sr@denx.de>2009-07-27 09:13:38 +0200
committerStefan Roese <sr@denx.de>2009-07-28 07:26:07 +0200
commit042d01c72e0ea95731708dd24bb8b6cf42e75c80 (patch)
tree651dee9bd7f35917c2b2f4f1bab5ade676e30a21
parent11a1604f8d0a8d936b42f6435d004b4aa33a5d87 (diff)
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ppc4xx: Fix problem with NOR range assignment in Canyonlands ft_board_setup
This patch fixes the problem, that the current fdt board fixup code only set's one range, the one for NOR. By this it's overwriting the already correctly configured values done in __ft_board_setup(). Just remove this now unneeded NOR fixup and all the ranges are correctly defined. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Felix Radensky <felix@embedded-sol.com>
-rw-r--r--board/amcc/canyonlands/canyonlands.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index c0c1352..5071c8d 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -585,23 +585,8 @@ extern void __ft_board_setup(void *blob, bd_t *bd);
void ft_board_setup(void *blob, bd_t *bd)
{
- u32 val[4];
- int rc;
-
__ft_board_setup(blob, bd);
- /* Fixup NOR mapping */
- val[0] = CONFIG_SYS_NOR_CS; /* chip select number */
- val[1] = 0; /* always 0 */
- val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */
- val[3] = gd->bd->bi_flashsize;
- rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
- val, sizeof(val), 1);
- if (rc) {
- printf("Unable to update property NOR mapping, err=%s\n",
- fdt_strerror(rc));
- }
-
if (gd->board_type == BOARD_CANYONLANDS_SATA) {
/*
* When SATA is selected we need to disable the first PCIe