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| author | Michal Simek <monstr@monstr.eu> | 2007-09-11 00:29:27 +0200 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2007-09-11 00:29:27 +0200 |
| commit | 9c73f4b81172bc9f1b8f132450e69bcfb5b960ca (patch) | |
| tree | b20402ff5f80a91423b9d444ba5b947d36cd06ff | |
| parent | 78cff50edba6b1508eb15c2f53ce966ac891eb9e (diff) | |
| parent | e251e00d0db4b36d1d2b7e38fec43a7296b529a2 (diff) | |
| download | u-boot-imx-9c73f4b81172bc9f1b8f132450e69bcfb5b960ca.zip u-boot-imx-9c73f4b81172bc9f1b8f132450e69bcfb5b960ca.tar.gz u-boot-imx-9c73f4b81172bc9f1b8f132450e69bcfb5b960ca.tar.bz2 | |
Merge git://www.denx.de/git/u-boot
347 files changed, 28323 insertions, 5458 deletions
@@ -1,3 +1,1162 @@ +commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3 +Author: stefano babic <sbabic@denx.de> +Date: Thu Aug 30 23:01:49 2007 +0200 + + PXA270: Added support for TrizepsIV board. + + This patch add support for the Trizeps IV module (520Mhz). + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 80172c6181c912fbb34ea3ba0c22b232b419b47f +Author: stefano babic <sbabic@denx.de> +Date: Thu Aug 30 22:57:04 2007 +0200 + + PXA270: Add support for multiple serial ports. + + This patch adds support for multiple serial ports to the PXA target. + FFUART, BTUART and STUART are supported. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 28bb3f72c687ac6b2eb076b01dd21a5fd657d45e +Author: stefano babic <sbabic@denx.de> +Date: Thu Aug 30 22:48:47 2007 +0200 + + PXA270: fix compile issue (invalid lvalue) + + Code is broken for PXA270 due to "invalid lvalue in assignment". + + This patch fix it in pxa-regs.h + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 1d2ca446e1a731df420206d04fe278c27ea6b8e8 +Author: Jason Jin <Jason.jin@freescale.com> +Date: Thu Aug 30 18:19:05 2007 +0800 + + Add BUILD_DIR support for bios emulator. + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + +commit b4d8a55145442f136982634862341a3e02002bda +Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com> +Date: Fri Aug 31 14:41:51 2007 +0900 + + [MIPS] Remove inline asm string functions + + Stop using inline string functions on MIPS as other ARCHs do so, + since the optimized inline asm versions are not small. + + This change is triggered by a following MIPS build error: + common/libcommon.a(exports.o)(.text+0xdc): In function `jumptable_init': + common/exports.c:32: undefined reference to `strcmp' + make: *** [u-boot] Error 1 + + Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> + +commit 8ea2c4e54833deaebc24c3ca6b7f21353c25b0f5 +Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com> +Date: Fri Aug 31 14:41:45 2007 +0900 + + [MIPS] Update asm string header + + This patches contains several bugfixes and cleanups in the latest upstream: + + - Don't include linux/config.h + - Remove buggy inline version of memscan. + - Merge with Linux 2.6.11-rc3. + - Fix undefined reference to strcpy in binfmt_misc caused by gcc 3.4. + - Goodbye mips64. 31704 lines of code bite the dust. + - Replace extern inline with static inline. + - Fix return value of strncpy. + - Remove a bunch more "$1" clobbers. + + Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> + +commit 5b729fb3bd98f49855d6bfc657c3fbae95f2adc2 +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Tue Sep 4 17:31:22 2007 +0200 + + Fix do_bootm_linux() so that multi-file images with FDT blob boot. + + Fix incorrect blob address calculation in do_bootm_linux() that prevents + booting the kernel from a multi-file image (kernel + initrd + blob). + + Also, make minor updates to the U-Boot's output and to the coding style. + + Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> + +commit 041a2554ad619e80dce520c1a33210affcb6a3f2 +Author: Gary Jennejohn <gary.jennejohn@freenet.de> +Date: Fri Aug 31 14:29:04 2007 +0200 + + Add support for Sil680 IDE controller. + + o add drivers/sil680.c to support the Sil680 IDE-controller. + o drivers/Makefile: add sil680.o. + + Signed-off-by: Gary Jennejohn <garyj@denx.de> + +commit e79021223bc339df655e360645a52c457a74b067 +Author: Grant Likely <grant.likely@secretlab.ca> +Date: Thu Sep 6 09:47:40 2007 -0600 + + bootm/fdt: Only process the fdt if an fdt address was provided + + Boards with CONFIG_OF_LIBFDT enabled are not able to boot old-style + kernels using the board info structure (instead of passing a device tree) + This change allows the old style booting to be used if the fdt argument + was not passed to 'bootm'. + + Signed-off-by: Grant Likely <grant.likely@secretlab.ca> + Acked-by: Kim Phillips <kim.phillips@freescale.com> + +commit cf2817a84c2e9bea2c5dfc084bce2f2d2563ac43 +Author: Grant Likely <grant.likely@secretlab.ca> +Date: Thu Sep 6 09:46:23 2007 -0600 + + Migrate 5xxx boards from CONFIG_OF_FLAT_TREE to CONFIG_OF_LIBFDT + + Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200 + + Tested on: lite5200b + + Note: the fixup functions have not been moved to a common place. This + patch is targeted for immediate merging as in solves a build issue, but + the final name/location of the fixups is still subject to debate. I + propose to merge this now, and move the fixups in the next merge window + to be usable by all targets. + + Signed-off-by: Grant Likely <grant.likely@secretlab.ca> + +commit 41bb76e941929f54a73206fb132f7a4c275543a3 +Author: Grant Likely <grant.likely@secretlab.ca> +Date: Thu Sep 6 09:46:17 2007 -0600 + + libfdt: add convenience function fdt_find_and_setprop() + + Given the path to a node, fdt_find_and_setprop() allows a property value + to be set directly. + + Signed-off-by: Grant Likely <grant.likely@secretlab.ca> + +commit 56a9270521baaa00e12639a978302a67f61ef060 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Aug 30 16:18:18 2007 -0500 + + Fix ULI RTC support on MPC8544 DS + + The RTC on the M1575 ULI chipset requires a dummy read before + we are able to talk to the RTC. We accomplish this by adding a + second memory region to the PHB the ULI is on and read from it. + + The second region is added to maintain compatiabilty with Linux's + view of the PCI memory map. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit f75e89e9b5714db2b0e80074071dfbdd6f59488a +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Thu Aug 30 01:58:48 2007 -0500 + + ft_board_setup update 85xx/86xx of pci/pcie bus-range property. + + pcie is now differentiated from pci. Add 8641 bus-range updates. + + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + +commit 81b73dec16fd1227369a191e725e10044a9d56b8 +Author: Gary Jennejohn <garyj@denx.de> +Date: Fri Aug 31 15:21:46 2007 +0200 + + ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia + + The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is + set to non-zero, because it doesn't support MRM (memory-read- + multiple) correctly. We now added the possibility to configure + this register in the board config file, so that the default value + of 8 can be overridden. + + Here the details of this patch: + + o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow + board-specific settings. As an example the sequoia board requires 0. + Idea from Stefan Roese <sr@denx.de>. + o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the + PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. + o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set + CFG_PCI_CACHE_LINE_SIZE to 0. + + Signed-off-by: Gary Jennejohn <garyj@denx.de> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 60174746c668b309378a91488dded898e9553eae +Author: Wolfgang Denk <wd@denx.de> +Date: Fri Aug 31 10:01:51 2007 +0200 + + Fix TFTP OACK code for short packets. + + The old code had a loop limit overflow bug which caused a semi- + infinite loop for small packets, because in "i<len-8", "i" was signed, + but "len" was unsigned, and "len-8" became a huge number for small + values of "len". + + This is a workaround which replaces broken commit 8f1bc284. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit ff13ac8c7bbebb238e339592de765c546dba1073 +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Aug 30 14:42:15 2007 +0200 + + Backout commit 8f1bc284 as it causes TFTP to fail. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 1900fbf255acba8b94fb442a16408ea85a1d46a6 +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Thu Aug 30 02:26:17 2007 -0500 + + Revert "Fix MPC8544DS PCIe3 scsi." + + This reverts commit 9468e680. + Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient. + + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + +commit 8f1bc28408ded213418d9bc0780c7d8fb8a03774 +Author: Grant Likely <grant.likely@secretlab.ca> +Date: Wed Aug 29 18:26:24 2007 -0600 + + tftp: don't implicity trust the format of recevied packets + + The TFTP OACK code trusts that the incoming packet is formated as + ASCII text and can be processed by string functions. It also has a + loop limit overflow bug where if the packet length is less than 8, it + ends up looping over *all* of memory to find the 'blksize' string. + + This patch solves the problem by forcing the packet to be null + terminated and using strstr() to search for the sub string. + + Signed-off-by: Grant Likely <grant.likely@secretlab.ca> + +commit 2602a5c40ae37ab965a4e240854fdaffb51328a4 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Aug 29 09:06:05 2007 -0500 + + sbc8641: remove unused OF_FLAT_TREE_MAX_SIZE + + this had slipped through the cracks, since the sbc board was added + after I wrote the original patch to remove all these symbols, and + before it was merged. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit c5bded3c88e48ae648a75d357dc81a8255fa81f1 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Aug 29 14:05:30 2007 +0200 + + Add mii_init() prototype + + to get rid of a *lot* of compiler warnings. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 2d1f23aa1e74e4a8f8ffa67f246eb98c522dfd7f +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Aug 29 13:35:03 2007 +0200 + + Disable network support on cmi_mpc5xx board + + ..because it caused compiler errors and there seems to be no + board maintainer to take care of this. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 9468e6804b7e25b0f6f52e53f47bce3175400a16 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Aug 20 09:44:00 2007 -0500 + + Fix MPC8544DS PCIe3 scsi. + + <ed.swarthout@freescale.com> + + The problem is pciauto_setup_device() getting called from fsl_pci_init.c + is allocating memory space it doesn't need. + + Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com> + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 4bf4abb8a4e9955556b120a1aafa30c03e74032a +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Tue Aug 21 09:38:59 2007 -0500 + + 8548cds fixes + + Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the + correct consoledev needed for linux boot. + Standardize on fdt{file,addr} var to hold dtb file name. + + Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}. + + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + +commit 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933 +Author: Haiying Wang <Haiying.Wang@freescale.com> +Date: Thu Aug 23 15:20:54 2007 -0400 + + Enable L2 cache for MPC8568MDS board + + The L2 cache size is 512KB for 8568, print out the correct informaiton. + + Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> + +commit 94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b +Author: Jason Jin <Jason.jin@freescale.com> +Date: Wed Aug 22 17:54:49 2007 +0800 + + Remove the bios emulator binary files from MAI board + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + +commit 7608d75f9c87c9eb5b3a43219d0506d3e979a13f +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Aug 21 17:00:17 2007 -0500 + + support board vendor-common makefiles + + if a board/$(VENDOR)/common/Makefile exists, build it. + + also add the first such case, board/freescale/common/Makefile, to + handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as + dictated by board configuration. + + thusly get rid of alternate build dir errors such as: + + FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory + + by putting the common/ mkdir command in its proper place (the common + Makefile). Common bits from existing individual board Makefiles have + been removed. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit ef8f20752712dc1cdbd86f47e3bd6e35f81c83fd +Author: stefano babic <sbabic@denx.de> +Date: Tue Aug 21 15:52:33 2007 +0200 + + Fix: TFTP is not working on little endian systems + + TFTP does not work anymore after multicast tftp + patch was applied on little endian systems. + This patch fix it. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 5f470948570526e9186f053a3003da7719604e90 +Author: stefano babic <sbabic@denx.de> +Date: Tue Aug 21 15:50:33 2007 +0200 + + Fix MAC address setting in DM9000 driver. + + The logic to check if there is a correct MAC address in the DM9000 + EEPROM, added in the last patch, is wrong. Now the MAC address is + always taken from the environment, even if a suitable MAC is present + in the EEPROM. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 4a8527ef086ec7c89f40674ef024ae6f988a614a +Author: Martin Krause <martin.krause@tqs.de> +Date: Tue Aug 21 12:40:34 2007 +0200 + + MPC5xxx: fix some compiler warnings in USB code + + Fix the following warnings: + - usb.c:xx: warning: function declaration isn't a prototype + - usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer + from pointer wihtout a cast + + Signed-off-by: Martin Krause <martin.krase@tqs.de> + +commit 16e23c3f5dab6937f5109365416808c7f15c122b +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Mon Aug 20 23:55:33 2007 -0500 + + fsl_pci_init - Remove self PCSRBAR allocation + + CPU physical address space was being wasted by allocating a + PCSRBAR PCI inbound region to it's memory space. + + As a rule, PCSRBAR should be left alone since it does not affect + transactions from self and other masters may have changed it. + + Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com> + +commit 0e700ce03a23bb1921149bc77008ace7103d5289 +Author: Martin Krause <martin.krause@tqs.de> +Date: Mon Aug 20 13:56:47 2007 +0200 + + Fix compiler warning in include/s3c2410.h + + This patch fixes the "type qualifiers ignored on fuction return tpye" + warning for include/s3c2410.h + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + +commit 9bb8b209ed2058a5756ecbeb544c067e44a42aea +Author: Dirk Behme <dirk.behme@googlemail.com> +Date: Mon Aug 20 07:09:05 2007 +0200 + + Fix compilation error for omap2420h4_config. + + omap2420h4 switched to cfi, so remove old (already disabled) flash.c + and flash_probe() calls in env_flash.c. + + Signed-off-by: Dirk Behme <dirk.behme@gmail.com> + +commit 3bb342fc85d79dbb6b8c2039e7cdcddc82b8d90f +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Fri Aug 10 14:34:14 2007 -0500 + + fdt: remove unused OF_FLAT_TREE_MAX_SIZE references + + and make some minor corrections to the FDT part of the README. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 6af2eeb1e99c2dcc584d4c5ab7fcae30a325f4de +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Aug 29 01:32:05 2007 +0200 + + Minor coding style cleanup. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit a861558c65f65f1cf1302f3a35e9db7686b9e1a3 +Author: Heiko Schocher <hs@pollux.denx.de> +Date: Tue Aug 28 17:40:33 2007 +0200 + + [UC101] Fix: if no CF in the board, U-Boot resets sometimes. + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit f98984cb194bb34dbe1db9429d3b51133af30d07 +Author: Heiko Schocher <hs@pollux.denx.de> +Date: Tue Aug 28 17:39:14 2007 +0200 + + IDE: - make ide_inb () and ide_outb () "weak", so boards can + define there own I/O functions. + (Needed for the pcs440ep board). + - The default I/O Functions are again 8 Bit accesses. + - Added CONFIG_CMD_IDE for the pcs440ep Board. + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit 9c02defc29b57945b600714cf61ddfd02b02fb14 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Sat Aug 25 05:07:16 2007 +0200 + + POST: limit memory test area to not touch global data anymore + + As experienced on lwmon5, on some boards the POST memory test can + corrupt the global data buffer (bd). This patch fixes this issue + by checking and limiting this area. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 75e1a84d483e36be10e206e539b028c4889e1158 +Author: Stefan Roese <sr@denx.de> +Date: Fri Aug 24 15:41:42 2007 +0200 + + ppc4xx: Add RTC POST test to lwmon5 board configuration + + Since this RTC POST test is taking quite a while to complete + it's only initiated upon special keypress same as the complete + memory POST. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit d7bfa620037a6d2210159387571bdf93aa32c162 +Author: Stefan Roese <sr@denx.de> +Date: Fri Aug 24 15:19:10 2007 +0200 + + ppc4xx: Change GPIO signal for watchdog triggering on lwmon5 + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c25dd8fc25e9ca3695db996a257d9ba4dab414db +Author: Stefan Roese <sr@denx.de> +Date: Thu Aug 23 11:02:37 2007 +0200 + + ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board + + This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5 + board. Now the "eeprom" command can be used to read/write from/to this + device. Additionally a new command was added "eepromwp" to en-/disable + the write-protect of this 2nd EEPROM. + + The 1st EEPROM is not affected by this write-protect command. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c64fb30e4c5976007d56fc1789c7a0666082b536 +Author: Stefan Roese <sr@denx.de> +Date: Wed Aug 22 08:56:09 2007 +0200 + + ppc4xx: Remove unused option CFG_INIT_RAM_OCM + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 3ad63878737a5a2b1e60825bf0a7d601d7a695e7 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 21 16:27:57 2007 +0200 + + ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based) + + This patch adds support for the matrix keyboard on the lwmon5 board. + Since the implementation in the dsPCI is kind of compatible with the + "old" lwmon board, most of the code is copied from the lwmon + board directory. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 3e66c078003607a7d1d214c15a5f262bc1b4032f +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Aug 19 10:27:34 2007 +0200 + + Fix some build errors. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 05675735ef77dc23b5e0eb782bad1ff477b55e86 +Author: Wolfgang Denk <wd@denx.de> +Date: Sat Aug 18 22:00:38 2007 +0200 + + Update CHANGELOG. + +commit 79f240f7ecc0506b43ac50d1ea405ff6540d4d57 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Aug 16 22:52:39 2007 -0500 + + lib_ppc: make board_add_ram_info weak + + platforms wishing to display RAM diagnostics in addition to size, + can do so, on one line, in their own board_add_ram_info() + implementation. + + this consequently eliminates CONFIG_ADD_RAM_INFO. + + Thanks to Stefan for the hint. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 815b5bd5b18569917c3e04b9757511e6ed23b9f6 +Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com> +Date: Fri Aug 17 12:43:44 2007 +0900 + + PCI_READ_VIA_DWORD_OP: Fix *val uninitialized bug + + This patch has been sent on: + - 6 Jun 2007 + + Many users of PCI config read routines tend to ignore the function + ret value, and are only concerned about the contents of *val. Based + on this, pci_hose_read_config_{byte,word}_via_dword should initialize + the *val on dword read error. + + Without this fix, for example, we'll go on scanning bus with vendor or + header_type uninitialized. This brings many unnecessary config trials. + + Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> + +commit 26667b7fa05a8bf2fc65fb9f3230b02b1a10c367 +Author: Stefan Roese <sr@denx.de> +Date: Sat Aug 18 14:37:52 2007 +0200 + + ColdFire: Fix some remaining problems with CFG_CMD_ + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 8280f6a1c43247616b68224675188e5ccd124650 +Author: Stefan Roese <sr@denx.de> +Date: Sat Aug 18 14:33:02 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 4a442d3186b31893b4f77c6e82f63c4517a5224b +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Aug 16 19:23:50 2007 -0500 + + ColdFire: Add M5235EVB Platform for MCF523x + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 4cc1cd5941827a04cf5c51a07fcc42e8945894aa +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Fri Aug 17 09:30:00 2007 -0500 + + mpc83xx: fix typo in DDR2 programming + + introduced in the implement board_add_ram_info patch as I was cleaning out the + magic numbers. sorry. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit e58fe95784d2514fc9c21028dc59f2b319a35d80 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Aug 16 22:53:09 2007 -0500 + + mpc83xx: move freescale boards to boards/freescale + + includes build fixes. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 5aa4ad8d8e7e9468219990c7875d5fdc9e962f47 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Aug 16 22:52:59 2007 -0500 + + mpc83xx: suppress unused variable 'val8' warning + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit bbea46f76f767b919070b4829bf34c86bd223248 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Aug 16 22:52:48 2007 -0500 + + mpc83xx: implement board_add_ram_info + + add board_add_ram_info, to make memory diagnostic output more + consistent. u-boot banner output now looks like: + + DRAM: 256 MB (DDR1, 64-bit, ECC on) + + and for boards with SDRAM on the local bus, a line such as this is + added: + + SDRAM: 64 MB (local bus) + + also replaced some magic numbers with their equivalent define names. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 14778585d1389d86d5846efec29e5fce892680ce +Author: Tony Li <tony.li@freescale.com> +Date: Fri Aug 17 10:35:59 2007 +0800 + + mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support + + The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c + And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board. + + Signed-off-by Tony Li <tony.li@freescale.com> + +commit 8ae158cd87a4a25722b27835261b6ff0fa2aa6a7 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Aug 16 15:05:11 2007 -0500 + + ColdFire: Add M54455EVB for MCF5445x + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit a1436a842654a8d3927d082a8ae9ee0a10da62d7 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Aug 16 13:20:50 2007 -0500 + + ColdFire: Add M5253EVBE platform for MCF52x2 + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit a605aacd8324094199402816cc6d9124aba57b8d +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Aug 16 05:04:31 2007 -0500 + + ColdFire: Add M5249EVB platform for MCF52x2 + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit f28e1bd9daa6de5eb33ae4822bda6b008ccb4e9e +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 20:32:06 2007 -0500 + + ColdFire: Update Freescale MCF52x2 platforms + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 870470dbf6f4bb9864e0d97aeedbc17c167c6d1c +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 19:55:10 2007 -0500 + + ColdFire: Update EB+MCF-EV123 platform + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit aa93d859d9b1fcd8eea52d51b06e86c38f72111b +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 19:46:38 2007 -0500 + + ColdFire: update TASREG platform for MCF52x2 + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit a9505510bf56a9b5558248dd8b73ec9d9a1556a2 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 19:45:51 2007 -0500 + + ColdFire: update r5200 platform for MCF52x2 + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 6cfd3c7bc813fb317ab7c0781f0d1874b1c0877c +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 19:43:20 2007 -0500 + + ColdFire: idmr platform MCF52x2 update + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 6706424d0bb851fb52af00cd1c3301e91ee7f2b0 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 19:41:06 2007 -0500 + + ColdFire: cobra5272 platform for MCF52x2 update + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 56115665b4a64c10c01440c57749b265e0908fa4 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 19:38:15 2007 -0500 + + ColdFire: MCF52x2 Header files update + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 83ec20bc4380eebddfde45da6e3a69a92d4db21d +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 19:21:21 2007 -0500 + + ColdFire: MCF52x2 update + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit f52e78304dcc0ac459c0ea1fa5be275c7d1642cf +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 18:46:11 2007 -0500 + + ColdFire: MCF5329 update cache + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 7171977fb8fd77cfb6676953fa9a05789c450513 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 15:40:20 2007 -0500 + + ColdFire: MCF5329 header file clean up + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit ab77bc547ba561c25ea34457ed17aa0b2f7c2723 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Wed Aug 15 15:39:17 2007 -0500 + + ColdFire: MCF5329 Update and cleanup + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 10327dc5541f947c0cf7e31fef86c4706169607a +Author: Andy Fleming <afleming@freescale.com> +Date: Thu Aug 16 16:35:02 2007 -0500 + + Add CONFIG_HAS_ETH0 to all boards with TSEC + + The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether + to update TSEC1's device-tree node, so we need to add it + to all the boards with TSECs. Do this for 83xx and 86xx, too, + since they will eventually do something similar. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit d64ee908a1b525e5bb2b4cbeb5c449ad6a469666 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Aug 16 15:05:04 2007 -0500 + + Update MPC8544 DS PCI memory map + + The PCIe bus that the ULI M1575 is connected to has no possible way of + needing more than the fixed amount of IO & Memory space needed by the ULI. + + So make it use far less IO & memory space and have it use the shared LAW. This + free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed + by each bus. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit ea5877e31ed63ade948fd1293895ec23fe01472e +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Aug 16 11:01:21 2007 -0500 + + Fix up some fdt issues on 8544DS + + It looks like we had a merge issue that duplicated a bit of code + in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get + the MAC address properly set in the device tree on boot for TSEC1 + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 07bc20560cb9d3d186cca268c05c82762e8c55ad +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Thu Aug 16 15:16:03 2007 +0200 + + PPC4xx:HCU4/5 cleanup + + Minor cleanups to confirm to the u-boot coding style. + Some german expressions -> english. + HCU5 enforces a unique IP adress for a given slot in the rack. + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 1e6b07c64967c1eb2cd84faa4c32bf2a769bc8eb +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Thu Aug 16 15:16:02 2007 +0200 + + PPC4xx:HCU4/5 cleanup ecc/sdram init + + Make ecc initialisation robust, as DDR2-ECC errors may be generated + while zeroing the RAM. + + Return 16 bytes (a cacheline) less than the available memory, as the + board and/or PPC440EPx might have problems accessing the last bytes. + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit d35b508a55508535b6e8445b718585d27df733d3 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Aug 15 22:29:56 2007 -0500 + + fdt: suppress unused variable 'bd' warning + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 82bd9ee77490588d4da785d75829ca63d0176baf +Author: Andy Fleming <afleming@freescale.com> +Date: Wed Aug 15 20:06:50 2007 -0500 + + Fix warnings from of_data copy fix + + Forgot to cast of_flat_tree to ulong. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 7613afda77d5eec0f47d303025b0c661b70e4c73 +Author: Andy Fleming <afleming@freescale.com> +Date: Wed Aug 15 20:03:44 2007 -0500 + + Don't wait for disconnected TSECs + + The TSEC driver's PHY code waits a long time for autonegotiation to + complete, even if the link is down. The PHY knows the link is + down or up before autonegotiation completes, so we can short-circuit + the process if the link is down. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit b96c83d4ae475a70ef2635cd0e748174c44c8601 +Author: Andy Fleming <afleming@freescale.com> +Date: Wed Aug 15 20:03:34 2007 -0500 + + Fix numerous bugs in the 8568 UEC support + + Actually, fixed a large bug in the UEC for *all* platforms. + How did this ever work? + + uec_init() did not follow the spec for eth_init(), and returned + 0 on success. Switch it to return the link like tsec_init() + (and 0 on error) + + The immap for the 8568 was defined based on MPC8568, rather than + CONFIG_MPC8568 + + CONFIG_QE was off + + CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0" + + Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is + enabled + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 3a79013e2adda53332dfd0b511066a805e929a9d +Author: Andy Fleming <afleming@freescale.com> +Date: Wed Aug 15 20:03:25 2007 -0500 + + Define tsec flag values in config files + + The tsec_info structure and array has a "flags" field for each + ethernet controller. This field is the only reason there are + settings. Switch to defining TSECn_FLAGS for each controller + in the config header, and we can greatly simplify the array, and + also simplify the addition of future boards. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit ec7238229507e7f47533a611ea8c53319d234cf3 +Author: Andy Fleming <afleming@freescale.com> +Date: Wed Aug 15 20:03:13 2007 -0500 + + Add support for building all boards with a TSEC + + Changes to the TSEC driver affect almost all 83xx, 85xx, and 86xx boards. + Now we can do a MAKEALL test on all of them! + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 10aaf716cb0dc6614df54ef78bed5144afd23ef8 +Author: Andy Fleming <afleming@freescale.com> +Date: Wed Aug 15 17:30:56 2007 -0500 + + Fix of_data copying for CONFIG_OF_FLAT_TREE-using boards + + The fix, "Fix where the #ifdef CFG_BOOTMAPSZ is placed" + neglected to *also* put the code inside the similar #ifdef + for CONFIG_OF_FLAT_TREE. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 78f9fef7f406078c8bf7191e665a73f795157746 +Author: Scott Wood <scottwood@freescale.com> +Date: Wed Aug 15 15:46:46 2007 -0500 + + mpc885ads: Don't define CONFIG_BZIP2. + + bzip2 requires a significant chunk of malloc space, and there isn't + enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area + and a downloaded image at 0x400000. + + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 002275a3ed8b114885f6702d6d544d0780dfe689 +Author: Michal Simek <Monstr@seznam.cz> +Date: Thu Aug 16 08:54:10 2007 +0200 + + Bios emulator - fix microblaze toolchain problem + + microblaze CPU have problem with bios_emulator code. + Microblaze toolchain doesn't support PRAGMA PACK. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit a5a38f4fd7e5366d706ff6a985f9b6715ddbc98b +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Aug 16 11:51:04 2007 +0200 + + Minor Coding Style fix; Update CHANGELOG file. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 8fb6e80c06849e3013ac5c9350d8ed9e52967991 +Author: Stefan Roese <sr@denx.de> +Date: Thu Aug 16 11:21:49 2007 +0200 + + ppc4xx: Remove #warning in esd auto_update.c + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 2d78074d2e806edc380c1464eb9e5df335ece65e +Author: Stefan Roese <sr@denx.de> +Date: Fri Jun 22 17:32:28 2007 +0200 + + ppc7xx: Update CPCI750 board + + This small CPCI750 update extends the board specific command + "show_config" to display the Marvell strapping registers and + extends the PCI IDE controller. + + Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 9de469bd960cc1870bb40d6672ed42726b8b50d7 +Author: Stefan Roese <sr@denx.de> +Date: Thu Aug 16 10:18:33 2007 +0200 + + ppc4xx: Only enable POST FPU test on Sequoia and not Rainier + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 6da0c5bd4a53e40eb4f7eb72a4c051ecabad783c +Author: Stefan Roese <sr@denx.de> +Date: Thu Aug 16 09:54:51 2007 +0200 + + Add missing rainier (PPC440GRx) target to MAKEALL and MAINTAINERs files + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 02ba7022f62bb75908296c58c63866e1d294b69a +Author: Stefan Roese <sr@denx.de> +Date: Thu Aug 16 09:52:29 2007 +0200 + + ppc4xx: Update Sequoia/Rainier bootstrap command + + As suggested by David Mitchell, here an update for the Sequoia/Rainier + bootstrap command. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 35cc4e4823668e8745854899cfaedd4489beb0ef +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Aug 15 22:30:39 2007 -0500 + + mpc83xx: enable libfdt by default on freescale boards + + this enables libfdt code by default for the + freescale mpc8313erdb, mpc832xemds, mpc8349emds, + mpc8349itx and gp boards. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 3fde9e8b22cfbd7af489214758f9839a206576cb +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Aug 15 22:30:33 2007 -0500 + + mpc83xx: migrate remaining freescale boards to libfdt + + this adds libfdt support code for the freescale + mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx, + and gp boards. + + Boards remain compatible with OF_FLAT_TREE. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 6a16e0dfcc4119b46adb1dce2d6c8fb3c5d108e1 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Aug 15 22:30:26 2007 -0500 + + mpc83xx: move common /memory node update mechanism to cpu.c + + also adds common prototypes to include/common.h. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 8f9e0e9f339aee4ce31a338d5f27356eb5457f85 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Aug 15 22:30:19 2007 -0500 + + mpc83xx: remaining 8360 libfdt fixes + + PCI clocks and QE frequencies weren't being updated, and the core clock + was being updated incorrectly. This patch also adds a /memory node if + it doesn't already exist prior to update. + + plus some cosmetic trimming to single line comments. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit f4b2ac5ed9aaff9920d487bff8a59696c083a524 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Aug 15 22:30:12 2007 -0500 + + mpc83xx: fix UEC2->1 typo in libfdt setup code + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 19fa1c35368484d4ed10ddce8a7793c21862e3a3 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Aug 15 22:30:05 2007 -0500 + + mpc83xx: add MAINTAINER and MAKEALL entries for the mpc8323erdb + + and reorder the existing 83xx maintainers alpha. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Aug 15 11:55:35 2007 -0500 + + 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h + + Remove a leftover in net/tftp.c while we're at it. + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 4ce917742b1e48faa9bf9a9757545e56fb4cfe44 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Aug 15 12:20:40 2007 -0500 + + Move the MPC8641HPCN board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 8662577fe36fdb6a44b55b998d9daac6392a736a +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Aug 15 11:46:22 2007 -0500 + + 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h + + Remove a leftover in net/tftp.c while we're at it. + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 210f463c71917b7a4495c2103c228b9c179ae64d +Author: Jerry Van Baren <gvb.uboot@gmail.com> +Date: Wed Aug 15 11:13:15 2007 -0400 + + Fix where the #ifdef CFG_BOOTMAPSZ is placed. + + Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb + interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT) + when it should have gone inside of the conditional. As a result, it + broke non-LIBFDT board builds. + + Also added a missing "not." to the comment. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 0e19209767194a97cec6d93dba9e64d1da8d548e +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Wed Aug 15 12:14:23 2007 +0200 + + PPC4xx:HCU4/5-Board fix compile warning + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Tue Aug 14 14:06:45 2007 -0500 + + Fix malloc size error in ahci_init_one. + + Typically this causes scsi init to corrupt the + devlist and break the coninfo command. + Fix a compiler size warning. + + Signed-off-by: Jason Jin <jason.jin@freescale.com> + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit b361acd64fd2525c081b9b288b0804efe209c0e9 +Author: ksi@koi8.net <ksi@koi8.net> +Date: Tue Aug 14 10:02:16 2007 -0700 + + TI DaVinci - fix unsupported %hhx format + + Signed-off-by: Sergey Kubushyn <ksi@koi8.net> + +commit f01dbb5424a81453c81190dd30e945891466f621 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Aug 14 18:42:36 2007 +0200 + + Coding style cleanup. Update CHANGELOG. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 Author: Andy Fleming <afleming@freescale.com> Date: Tue Aug 14 10:32:59 2007 -0500 @@ -20,6 +1179,50 @@ Date: Tue Aug 14 15:40:00 2007 +0100 Supply spi interface in at45.c +commit 4ce846ec59f36b85d6644a769690ad3feb667575 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 15:12:01 2007 +0200 + + POST: Fix merge problem + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 429d9571f60631ae8a2fe12b11be4c75b0c2b37c +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 15:03:17 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 779e975117a75e91fcebe226a63104dbfb924ab1 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 14:44:41 2007 +0200 + + ppc4xx: Add initial Zeus (PPC405EP) board support + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c5a172a5fd636c12467429e3f7910e53773979c6 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 14:41:55 2007 +0200 + + POST: Add option for external ethernet loopback test + + When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST + is not done using an internal loopback connection, but by assuming + that an external loopback connector is plugged into the board. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit eb2b4010ae426245172988804ee8d9193fb41038 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 14:39:44 2007 +0200 + + POST: Add ppc405 support to cache and UART POST + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 0c42f36f15074bd9808a7dbd7ef611fad9bf537c Author: Peter Pearse <peter.pearse@arm.com> Date: Tue Aug 14 10:46:32 2007 +0100 @@ -391,6 +1594,17 @@ Date: Wed Jun 27 13:34:26 2007 +0200 Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Acked-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com> +commit 273db7e1bdd1937e32f1d4507321bb721ebd3118 +Author: Stefan Roese <sr@denx.de> +Date: Mon Aug 13 09:05:33 2007 +0200 + + ppc4xx: Fix problem in PLL clock calculation + + This patch was originall provided by David Mitchell <dmitchell@amcc.com> + and fixes a bug in the PLL clock calculation. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 9986bc3e40e899bea372a99a2bca4071bdf2e24b Author: Wolfgang Denk <wd@denx.de> Date: Sun Aug 12 21:34:50 2007 +0200 @@ -849,6 +2063,14 @@ Date: Thu Aug 2 14:42:20 2007 -0500 Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> +commit 35d22f957a85a22bb3cd1ad084fa5404620d1c42 +Author: Stefan Roese <sr@denx.de> +Date: Fri Aug 10 10:42:25 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f Author: Dirk Behme <dirk.behme@googlemail.com> Date: Thu Aug 2 17:42:08 2007 +0200 @@ -873,6 +2095,105 @@ Date: Thu Aug 2 17:41:14 2007 +0200 Signed-off-by: Dirk Behme <dirk.behme@gmail.com> +commit 157cda4d0c3d592ccbb19bbfc07d9251894f0894 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:31:22 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU5 files + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 6e5de26c6e7580faf16e87745cd488b92b492d0c +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:30:33 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU4 files + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit e8397fc78c9394d71de233a4d810fbc9047e4c76 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:38:26 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: common files + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit ac982ea5a4f2f993efcf52dca122f5a59df047d8 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:28:44 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: make related + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 137fdd9f474ecb853efdace5200576308c67f18d +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:28:03 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU5 config + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 714bc55b35b6f6a65cc8740a3842a543e88cdef2 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:27:15 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU4 config + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 1894dd381124bdbfbdae7cf3a6ca52a8eb1f4421 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:25:31 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: READMEs + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 641cca9569ce351ddb287fd3343d8b1dcb591db4 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:37:40 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: Infrastructure + + This series of patches adds support for 2 boards from Netstal Maschinen. + + The HCU4 has a PPC405Gpr and + the HCU5 has a PPC440EPX. + + The HCU4 has a somehow complicated flash setup, as the booteprom is + only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more + elegant solution. + + The HCU5 has only a booteprom as the whole code will be downloaded from a + different board which has HD, CD-ROM, etc and where all code is stored. + + This is my third try. I incorporated all suggestions made by Wolfgang and Stefan. + Thanks them a lot. + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 3e4c90c6233618fc1806e63fde68df5f3d6a0171 +Author: Stefan Roese <sr@denx.de> +Date: Fri Aug 10 08:42:55 2007 +0200 + + ppc4xx: Update lwmon5 POST configuration + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 29cb25da56afe18cf5e7072a92a9d98ea8af1fd4 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Fri Aug 10 08:25:22 2007 +0200 + + POST: Add ppc4xx UART POST support without external uart clock (lwmon5) + + The patch adds support for UART POST on ppc44x-based boards with no + external serial clocks installed. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + Acked-by: Stefan Roese <sr@denx.de> + commit 99c2fdab91bc633e46fb41dbaa629f87ccf6e00f Author: Kim Phillips <kim.phillips@freescale.com> Date: Mon Aug 6 18:18:34 2007 -0500 @@ -1144,6 +2465,78 @@ Date: Thu Aug 9 09:08:18 2007 -0500 Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com> +commit 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6 +Author: Stefan Roese <sr@denx.de> +Date: Wed Aug 8 09:54:26 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit a41de1f0d373e09c782dea558385a06247111ba5 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Sun Aug 5 05:15:18 2007 -0500 + + Port enabled for I2C signals and chipselects port configuration. + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 1a33ce65a4c51a69190dd8c408f9e1c62a66e94f +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Sun Aug 5 04:31:18 2007 -0500 + + Added NAND support + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit eaf9e447beb3e498818ef8ad0b8c1597cd506149 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Sun Aug 5 04:11:20 2007 -0500 + + Added I2C support + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 99c03c175d2689093176facf17c58ce2cb320001 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Sun Aug 5 03:58:52 2007 -0500 + + Changed CFG_CLK to gd->bus_clk for CFG_TIMER_PRESCALER. Added DECLARE_GLOBAL_DATA_PTR for time.c + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 8d1d66af54d305de29d0bbf4aa8c9e6375f7f731 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Sun Aug 5 03:55:21 2007 -0500 + + Added uart_gpio_conf() in serial_init(), seperated uart port configuration from cpu_init() to uart_gpio_conf() + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 6fde84a44b7e575ea80fe0e2d5be3b6f73d1e630 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Sun Aug 5 03:43:30 2007 -0500 + + Moved sync() from board file to include/asm-m68k/io.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 9e737d8476e7d6a596d16caaf6a3853a9a1190a2 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Sun Aug 5 03:30:44 2007 -0500 + + Declared attributes of void __mii_init(void) as an alias for int mii_init(void) + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 9998bd37ead85e93953559720710d3b0685c81e6 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Sun Aug 5 03:19:10 2007 -0500 + + Renamed CONFIG_MCFSERIAL to CONFIG_MCFUART + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + commit 7c4c3722a38d40b0cf537ddae72b04f4088b190c Author: Jason Jin <Jason.jin@freescale.com> Date: Tue Aug 7 16:17:06 2007 +0800 @@ -1169,6 +2562,17 @@ Date: Mon Aug 6 23:21:05 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit 537223afa61f64480df31ce440a9cb386df4a814 +Author: Stefan Roese <sr@denx.de> +Date: Mon Aug 6 21:10:17 2007 +0200 + + ppc4xx: Update AMCC Bamboo README doc/README.bamboo + + As suggested by Eugene O'Brien <Eugene.O'Brien@advantechamt.com>, + here an updated Bamboo README. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 9c7e4b06214db61bb21f1bcbe57c97519669baae Author: Wolfgang Denk <wd@denx.de> Date: Mon Aug 6 02:17:36 2007 +0200 @@ -1316,6 +2720,42 @@ Date: Thu Aug 2 10:11:18 2007 +0200 Minor cleanup of <board>_nand build rules. +commit 9ca8d79de096c65b9b9c867259b3ff4685f775ef +Author: Stefan Roese <sr@denx.de> +Date: Thu Aug 2 08:33:56 2007 +0200 + + ppc4xx: Code cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c92409812206ac67a7fa7aae298539a9c3804a46 +Author: Grzegorz Bernacki <gjb@semihalf.com> +Date: Tue Jul 31 18:51:48 2007 +0200 + + [ppc440SPe] Graceful recovery from machine check during PCIe configuration + + During config transactions on the PCIe bus an attempt to scan for a + non-existent device can lead to a machine check exception with certain + peripheral devices. In order to avoid crashing in such scenarios the + instrumented versions of the config cycle read routines are introduced, so + the exceptions fixups framework can gracefully recover. + + Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> + Acked-by: Rafal Jaworowski <raj@semihalf.com> + +commit dec99558b9ea75a37940d07f41a3565a50b54ad1 +Author: Rafal Jaworowski <raj@semihalf.com> +Date: Tue Jul 31 18:19:54 2007 +0200 + + [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A + + This brings back separate settings for PCIe bus numbers depending on chip + revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa + commit. 440SPe rev. A does NOT work properly with the same settings as for + the rev. B (no devices are seen on the bus during enumeration). + + Signed-off-by: Rafal Jaworowski <raj@semihalf.com> + commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 Author: Wolfgang Denk <wd@denx.de> Date: Thu Aug 2 00:48:45 2007 +0200 @@ -1324,6 +2764,55 @@ Date: Thu Aug 2 00:48:45 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit d2f68006627eda6cb6c7f364bddf621dbfd2fc68 +Author: Eugene OBrien <eugene.obrien@advantechamt.com> +Date: Tue Jul 31 10:24:56 2007 +0200 + + ppc4xx: Update AMCC Bamboo 440EP support + + Changed storage type of cfg_simulate_spd_eeprom to const + Changed storage type of gpio_tab to stack storage + (Cannot access global data declarations in .bss until afer code relocation) + + Improved SDRAM tests to catch problems where data is not uniquely addressable + (e.g. incorrectly programmed SDRAM row or columns) + + Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules + Fixed AM29LV320DT (OpCode Flash) sector map + + Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit ea9f6bce383cc9fbcdee28b5836109b1a6dba574 +Author: Stefan Roese <sr@denx.de> +Date: Tue Jul 31 08:37:01 2007 +0200 + + ppc4xx: Update 440EPx lwmon5 board support + + - Clear ECC status regs after ECC POST test + - Set dcbz for ECC generation with caches enabled as default + - Code cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 27a528fb41433c4c1e2b5d6bd3fd8d78606fc724 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 30 11:04:57 2007 +0200 + + ppc4xx: Only print ECC related info when the error bis are set + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit e36220a4baf1f188ba60f17e9d0f043069b1362a +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Fri Jul 27 16:44:31 2007 +0200 + + new FPGA image for PLU405 board + + new FPGA image for PLU405 board with improved CompactFlash timing + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 Author: Rafal Jaworowski <raj@semihalf.com> Date: Fri Jul 27 14:43:59 2007 +0200 @@ -1351,6 +2840,73 @@ Date: Fri Jul 27 14:22:04 2007 +0200 Signed-off-by: Rafal Jaworowski <raj@semihalf.com> +commit d4024bb72dd81695ec099b2199eda0d27c623e62 +Author: John Otken <john@softadvances.com> +Date: Thu Jul 26 17:49:11 2007 +0200 + + ppc4xx: Add support for AMCC 405EP Taihu board + + Signed-off-by: John Otken <john@softadvances.com> + +commit b66091de6c7390620312c2501db23d8391e7cabb +Author: Anatolij Gustschin <agust@denx.de> +Date: Thu Jul 26 15:08:01 2007 +0200 + + ppc4xx: lwmon5: Update Lime initialization + + Change Lime SDRAM initialization to now support 100MHz and + 133MHz (if enabled). Also the framebuffer is initialized to + display a blue rectangle with a white border. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 9f24a808f17fc0f37b7fb4805f734741335caecc +Author: Stefan Roese <sr@denx.de> +Date: Tue Jul 24 09:52:52 2007 +0200 + + ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added + + The used Intel NOR FLASH chips have internally two dies, and are now + treated as two seperate chips. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit aedf5bde179ecfbd0a96130d18996a96518b785f +Author: Stefan Roese <sr@denx.de> +Date: Tue Jul 24 07:20:09 2007 +0200 + + ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...) + + As suggested by Hakan Eryigit, here an updated setup for the lwmon5 + interrupt controller. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit a71d96eac8130b53a91f93cd10c70fca0db18d52 +Author: Stefan Roese <sr@denx.de> +Date: Fri Jul 20 15:03:44 2007 +0200 + + ppc4xx: Fix bug with default GPIO output value + + As spotted by Matthias Fuchs, the default output values for all GPIO1 + outputs were not setup correctly. This patch fixes this issue. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 531e3e8b831f357056448fa573137d5fb37000fd +Author: Pavel Kolesnikov <concord@emcraft.com> +Date: Fri Jul 20 15:03:03 2007 +0200 + + POST: Add ECC POST for the lwmon5 board + + This patch adds ECC Post test for the Lwmon5 board based + on PPC440EPx to U-Boot. + + Signed-off-by: Pavel Kolesnikov <concord@emcraft.com> + Acked-by: Yuri Tikhonov <yur@emcraft.com> + Acked-by: Stefan Roese <sr@denx.de> + commit cc3023b9f95d7ac959a764471a65001062aecf41 Author: Rafal Jaworowski <raj@semihalf.com> Date: Thu Jul 19 17:12:28 2007 +0200 @@ -1362,6 +2918,66 @@ Date: Thu Jul 19 17:12:28 2007 +0200 Signed-off-by: Rafal Jaworowski <raj@semihalf.com> +commit c883f6ea32dce91f07670b3aafecf6c99b1e5341 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 13:11:12 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 10:02:12 2007 +0200 + + ppc4xx: Code cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 2a49fc17d09020e7ebd9536694d99d20e419fcb8 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 10:01:38 2007 +0200 + + ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 10:00:43 2007 +0200 + + ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c + + The new boardspecific DDR2 controller configuration is used for the Yucca + board. Now the Yucca board with 440SPe Rev. A chips is also supported. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 6ed14addf97c8cd8f531e9ae7b2d3e222fffd53e +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 09:57:00 2007 +0200 + + ppc4xx: Add new weak functions to support boardspecific DDR2 configuration + + The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better + support non default, boardspecific DDR(2) controller configuration. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 5743a9207a370b90f09b20ebd61167c806b937f3 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 08:53:51 2007 +0200 + + ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup + + The new function remove_tlb() can be used to remove the TLB's used to + map a specific memory region. This is especially useful for the DDR(2) + setup routines which configure the SDRAM area temporarily as a cached + area (for speedup on auto-calibration and ECC generation) and later + need this area uncached for normal usage. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 3a6cab844cf74f76639d795e0be8717e02c86af7 Author: Wolfgang Denk <wd@denx.de> Date: Sat Jul 14 22:51:02 2007 +0200 @@ -1393,6 +3009,17 @@ Date: Fri Jul 13 08:26:05 2007 +0200 Signed-off-by: Heiko Schocher <hs@denx.de> +commit a2e1c7098cf9574386b0c96841dfc8ea5cc93578 +Author: Stefan Roese <sr@denx.de> +Date: Thu Jul 12 16:32:08 2007 +0200 + + ppc4xx: Change receive buffer handling in the 4xx emac driver + + This change fixes a bug in the receive buffer handling, that + could lead to problems upon high network traffic (broadcasts...). + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 239f05ee4dd4cfe0b50f251b533dcebe9e67c360 Author: Wolfgang Denk <wd@denx.de> Date: Thu Jul 12 01:45:34 2007 +0200 @@ -1581,6 +3208,252 @@ Date: Sun Jul 8 13:44:27 2007 +0200 Signed-off-by: Stefan Roese <sr@denx.de> +commit 0dca874db62718e41253659e60f3a1de7eb418ce +Author: TsiChung <tcliew@Goku.(none)> +Date: Tue Jul 10 15:45:43 2007 -0500 + + Cache update and added CFG_UNIFY_CACHE + + Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only. + + Signed-off-by: TsiChung <tcliew@Goku.(none)> + +commit 52b017604a8f4d4a795880ef6e7861d7f2f1b005 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:36:16 2007 -0500 + + Update header file. Include dtimer_intr_setup(). Changed timer divider to global define. + + Include immap.h and timer.h. Moved dtimer interrupt setup to dtimer_intr_setup() from cpu/mcf532x/interrupts.c. Changed (CFG_CLK /1000000) -1 << 8 to CFG_TIMER_PRESCALER + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 5cdc07c7ef8f08ea55d3c47ed9221d91aa6d5fac +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:31:25 2007 -0500 + + Update header files + + Include immap.h and renamed mcfrtc.h to rtc.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 2870e98ac8e5553e9187b12a47e5f46babb53990 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:29:21 2007 -0500 + + Add mcffec_initialize() + + Added mcffec_initialize() in eth_initialize() + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 45a25bfd0c52f8a3fa137216bc94d32f90bedc5d +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:27:40 2007 -0500 + + Update header file and clean up + + Include immap.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 0cee9c66318602c856a899ae5fa7579ccba6443a +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:23:15 2007 -0500 + + New uart structure and defines + + Seperated from mcfuart.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit a90e79de8d99e9c9d69d60bfff9f24c337165900 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:22:31 2007 -0500 + + New timer structure and defines + + Seperated from mcftimer.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit e04acb2eba4782489417240eff76e20e176aec10 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:21:09 2007 -0500 + + Rename mcfrtc to rtc + + Since it is already in m68k folder, un-necessary to pad mcf. Replaced immap_5329.h and m5329.h to immap.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 2bd806fe4fc23958b8f78778199e7a6e3f8f6ad5 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:17:36 2007 -0500 + + Rename mcfserial.c. Update include header + + Renamed mcfserial.c to mcfuart.c. Modified Makefile for mcfuart.o from mcfserial.o. Replace immap_5329.h and m5329.h to immap.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit f2208fbc2eb9de3f4285bfaa021c6ebae16c9b0e +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:13:58 2007 -0500 + + Header file update, clean up and cache handling + + Replaced immap_5329.h and m5329.h with immap.h. Included cache_invalid. + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 2e3f25ae9082daa9f5d181db45dfbc2e52ce0f97 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:10:40 2007 -0500 + + Create interrupts.c and modify Makefile + + interrupt_init() and dtimer_intr_setup() are placed in interrupts.c. Added interrupts.o to Makefile + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit ddd104f1ed655eda50c06ba636237a83ed943f34 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:06:55 2007 -0500 + + Enable Icache + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit b9bf3de377b2bae70c983c9b97feae914999e735 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:05:31 2007 -0500 + + Update header file and some clean up + + Replaced immap_5329.h and m5329.h with immap.h. Removed whitespaces. + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 84a015b52ec820a5ae173717d78516de731c89c2 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:03:28 2007 -0500 + + Update header file and enable icache + + Replaced immap_5329.h and m5329.h with immap.h. Enabled icache_enable() in cpu_init_r(). + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 7a17e759c7a8b58e910daf54df611e94fc8ca074 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 23:01:22 2007 -0500 + + Update header file and removed interrupt_init() + + Replace immap_5329.h and m5329.h with immap.h. Removed interrupt_init() and placed it in interrupts.c + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 3b635492c95bd0d6e08f93f699821cba1f602a64 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:57:46 2007 -0500 + + Update for flash.o and mii.o + + Removed flash.o and added mii.o + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit c5ded275d839e4ff79f41718d50a835d989f57bc +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:56:19 2007 -0500 + + MII functions calls. + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 427c814104560e29bda14955c67703245aaaa5b4 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:54:42 2007 -0500 + + Removed MII functions and replaced immap_5329.h and m5329.h with immap.h. + + The removed MII routines will be placed in mii.c. + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 01a793fda09c63df5a496f09dc1c7cb26e6751a2 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:51:05 2007 -0500 + + Duplicate code + + There is a Common Flash Interface Driver existed. To use the CFI driver, define CFG_FLASH_CFI in configuration file. + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 2744354a8437b8f78db178e30660215688bff570 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:46:38 2007 -0500 + + Seperate old structure defines and new structure defines + + Removed new uart structure and defines to uart.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 2bd58608dbcff8890ca9a0c59e861ac24f8bb230 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:45:01 2007 -0500 + + Seperate old structure defines and new structure defines + + New timer structure and defines will move to new timer.h + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 8cd5cd6de4ff92e03978338ed7aeb3ce7b7b9784 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:42:23 2007 -0500 + + Clean up + + Removed whitespace + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 514871f565dd8bd1121e4a3ac1665a790e20b8f2 +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:41:24 2007 -0500 + + Clean up + + Replaced whitespace with tabs + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit 48dbfeabc7afffe30609a4489f10c22cb67ef7dd +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:39:07 2007 -0500 + + Create new header file and move peripherals base address from configs file to new header file. + + Create new header file to include immap_5xxx.h and m5xxx.h and to share among drivers without update in driver file each processor is added. Moved peripherals base address and defines from configs file to immap.h. + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + +commit be296e31c4411f96d9cb3d2afc8fcb006867abfa +Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com> +Date: Thu Jul 5 22:24:58 2007 -0500 + + Revert file mode + + Changed MAKEALL file mode to executable, removed executable file mode from Makefile + + Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> + commit b3aff0cb9ecf236d7e8c93761dd1dadf6837a582 Author: Jon Loeliger <jdl@freescale.com> Date: Tue Jul 10 11:19:50 2007 -0500 @@ -1975,6 +3848,50 @@ Date: Tue Jul 10 00:01:28 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit c8603cfbd4573379a6076c9c208545ba2bbf019a +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 9 11:00:24 2007 +0200 + + Small coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 0f92c7e7c9a62755b1457d3c46f93c8c1f6c19fc +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Mon Jul 9 10:10:08 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + Remove unused CFG_NAND_LEGACY define + + These boards to not have NAND. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit bd84ee4c2020c3a6861f4bb2e7ea0fb49f82e803 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Mon Jul 9 10:10:06 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + Migrate esd 405EP boards to new NAND subsystem + + -cleanup + -use correct io accessors (in/out_be32()) + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit e09f7ab5749c345f924da272bea0521a73af5b11 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Mon Jul 9 10:10:04 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + This patch prepares the migration from the legacy NAND driver + to U-Boot's new NAND subsystem for esd boards. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + commit c3517f919d0f61650cf3027fd4faf0f631142f6c Author: Jon Loeliger <jdl@freescale.com> Date: Sun Jul 8 18:10:08 2007 -0500 @@ -2162,6 +4079,41 @@ Date: Thu Jul 5 19:13:52 2007 -0500 Signed-off-by: Jon Loeliger <jdl@freescale.com> +commit 10e038932f22ee80ebd53de312531e70e6590a2f +Author: Thomas Knobloch <knobloch@siemens.com> +Date: Fri Jul 6 14:58:39 2007 +0200 + + [NAND] Bad block skipping for command nboot + + The old implementation of command nboot does not support reading the image from + NAND flash with skipping of bad blocks. The patch implements a new version of + the nboot command: by calling nboot.jffs2 from the u-boot command line the + command will load the image from NAND flash with respect to bad blocks (by using + nand_read_opts()). This is similar to e.g. the NAND read command: "nand + read.jffs2 ...". + + Signed-off-by: Thomas Knobloch <knobloch@siemens.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 334043f601a90ac53e5ecc846fbb73a1ef38cb1f +Author: Stefan Roese <sr@denx.de> +Date: Fri Jul 6 12:26:51 2007 +0200 + + ppc4xx: Update lwmon5 default environment + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 5d187430a055d62f17ca84d75e7245439d1f7e75 +Author: Stefan Roese <sr@denx.de> +Date: Fri Jul 6 11:48:24 2007 +0200 + + ppc4xx: Update lwmon5 board + + Add unlock=yes environment variable to default variables to unlock + the CFI flash by default. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e Author: Stefan Roese <sr@denx.de> Date: Fri Jul 6 09:45:47 2007 +0200 @@ -3151,6 +5103,18 @@ Date: Fri Jun 22 14:58:04 2007 +0200 - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup +commit d677b32855f577ae2690dcd64a172cdd706e0ffc +Author: Mike Frysinger <vapier@gentoo.org> +Date: Fri Jun 22 10:34:12 2007 +0200 + + [patch] add nand_init() prototype to nand.h + + since nand_init() is expected to be called by other parts of u-boot, there + should be a prototype for it in nand.h + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + Signed-off-by: Stefan Roese <sr@denx.de> + commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b Author: Wolfgang Denk <wd@denx.de> Date: Wed Jun 20 18:14:24 2007 +0200 @@ -3192,6 +5156,26 @@ Date: Tue Jun 19 16:40:58 2007 +0200 Signed-off-by: Stefan Roese <sr@denx.de> +commit 8e585f02f82c17cc66cd229dbf0fd3066bbbf658 +Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com> +Date: Mon Jun 18 13:50:13 2007 -0500 + + Added M5329AFEE and M5329BFEE Platforms + + Added board/freescale/m5329evb, cpu/mcf532x, drivers/net, + drivers/serial, immap_5329.h, m5329.h, mcfrtc.h, + include/configs/M5329EVB.h, lib_m68k/interrupts.c, and + rtc/mcfrtc.c + + Modified CREDITS, MAKEFILE, Makefile, README, common/cmd_bdinfo.c, + common/cmd_mii.c, include/asm-m68k/byteorder.h, include/asm-m68k/fec.h, + include/asm-m68k/io.h, include/asm-m68k/mcftimer.h, + include/asm-m68k/mcfuart.h, include/asm-m68k/ptrace.h, + include/asm-m68k/u-boot.h, lib_m68k/Makefile, lib_m68k/board.c, + lib_m68k/time.c, net/eth.c and rtc/Makefile + + Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> + commit e73846b7cf1e29ae635bf9bb5570269663df2ee5 Author: Stefan Roese <sr@denx.de> Date: Fri Jun 15 11:33:41 2007 +0200 @@ -3767,6 +5751,16 @@ Date: Sun May 27 16:51:48 2007 +0200 Signed-off-by: Marian Balakowicz <m8@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com> +commit 7ebb4479b07ff294eb4d76e420753a0349f7c93b +Author: Ulf Samuelsson <ulf@atmel.com> +Date: Thu May 24 12:12:47 2007 +0200 + + [PATCH][NAND] Define the Vendor Id for Micron NAND Flash + + Signed-off-by: Ulf Samuelsson <ulf@atmel.com> + Signed-off-by: Ladislav Michl <ladis@linux-mips.org> + Signed-off-by: Stefan Roese <sr@denx.de> + commit d756894722c888d09a9fa1df8323753772d3dcce Author: Stefan Roese <sr@denx.de> Date: Thu May 24 09:49:00 2007 +0200 @@ -147,6 +147,11 @@ N: Daniel Engström E: daniel@omicron.se D: x86 port, Support for sc520_cdp board +N: Hayden Fraser +E: Hayden.Fraser@freescale.com +D: Support for ColdFire MCF5253 +W: www.freescale.com + N: Dr. Wolfgang Grandegger E: wg@denx.de D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards @@ -283,6 +288,11 @@ E: team@leox.org D: Support for LEOX boards, DS164x RTC W: http://www.leox.org +N: TsiChung Liew +E: Tsi-Chung.Liew@freescale.com +D: Support for ColdFire MCF523x, MCF532x, MCF5445x +W: www.freescale.com + N: Leif Lindholm E: leif.lindholm@i3micro.com D: Support for AMD dbau1550 board. @@ -297,6 +307,11 @@ N: Raymond Lo E: lo@routefree.com D: Support for DOS partitions +N: James MacAulay +E: james.macaulay@amirix.com +D: Suppport for Amirix AP1000 +W: www.amirix.com + N: Dan Malek E: dan@embeddedalley.com D: FADSROM, the grandfather of all of this @@ -372,8 +387,9 @@ D: Support for the Wind River sbc405, sbc8240 board W: http://www.windriver.com N: Stefan Roese -E: stefan.roese@esd-electronics.com -D: AMCC PPC401/403/405GP Support; Windows environment support +E: sr@denx.de +D: AMCC PPC4xx Support +W: http://www.denx.de N: Erwin Rol E: erwin@muffin.org @@ -407,6 +423,11 @@ N: Art Shipkowski E: art@videon-central.com D: Support for NetSilicon NS7520 +N: Michal Simek +E: monstr@monstr.eu +D: Support for Microblaze, ML401, XUPV2P board +W: www.monstr.eu + N: Yasushi Shoji E: yashi@atmark-techno.com D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board @@ -420,6 +441,11 @@ E: andrea.scian@dave-tech.it D: Port to B2 board W: www.dave-tech.it +N: Timur Tabi +E: timur@freescale.com +D: Support for MPC8349E-mITX +W: www.freescale.com + N: Rob Taylor E: robt@flyingpig.com D: Port to MBX860T and Sandpoint8240 @@ -473,18 +499,3 @@ N: Alex Zuepke E: azu@sysgo.de D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM W: www.elinos.com - -N: James MacAulay -E: james.macaulay@amirix.com -D: Suppport for Amirix AP1000 -W: www.amirix.com - -N: Timur Tabi -E: timur@freescale.com -D: Support for MPC8349E-mITX -W: www.freescale.com - -N: Michal Simek -E: monstr@monstr.eu -D: Support for Microblaze, ML401, XUPV2P board -W: www.monstr.eu diff --git a/MAINTAINERS b/MAINTAINERS index f812431..b8c1fdc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -42,6 +42,10 @@ Yuli Barcohen <yuli@arabellasw.com> Rattler MPC8248 ZPC1900 MPC8265 +Michael Barkowski <michael.barkowski@freescale.com> + + MPC8323ERDB MPC8323 + Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com> sacsng MPC8260 @@ -158,12 +162,12 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> VOH405 PPC405EP VOM405 PPC405EP WUH405 PPC405EP - CMS700 PPC405EP + CMS700 PPC405EP Niklaus Giger <niklaus.giger@netstal.com> - HCU4 PPC405GPr - HCU5 PPC440EPx + HCU4 PPC405GPr + HCU5 PPC440EPx Frank Gottschling <fgottschling@eltec.de> @@ -217,6 +221,10 @@ The LEOX team <team@leox.org> ELPT860 MPC860T +Dave Liu <daveliu@freescale.com> + + MPC8360EMDS MPC8360 + Nye Liu <nyet@zumanetworks.com> ZUMA MPC7xx_74xx @@ -273,6 +281,10 @@ Denis Peter <d.peter@mpl.ch> MIP405 PPC4xx PIP405 PPC4xx +Kim Phillips <kim.phillips@freescale.com> + + MPC8349EMDS MPC8349 + Daniel Poirot <dan.poirot@windriver.com> sbc8240 MPC8240 @@ -296,6 +308,7 @@ Stefan Roese <sr@denx.de> ocotea PPC440GX p3p440 PPC440GP pcs440ep PPC440EP + rainier PPC440GRx sequoia PPC440EPx sycamore PPC405GPr taishan PPC440GX @@ -320,6 +333,11 @@ Peter De Schrijver <p2@mind.be> ML2 PPC4xx +Timur Tabi <timur@freescale.com> + + MPC8349E-mITX MPC8349 + MPC8349E-mITX-GP MPC8349 + Erik Theisen <etheisen@mindspring.com> W7OLMC PPC4xx @@ -352,19 +370,6 @@ John Zhan <zhanz@sinovee.com> svm_sc8xx MPC8xx -Timur Tabi <timur@freescale.com> - - MPC8349E-mITX MPC8349 - MPC8349E-mITX-GP MPC8349 - -Kim Phillips <kim.phillips@freescale.com> - - MPC8349EMDS MPC8349 - -Dave Liu <daveliu@freescale.com> - - MPC8360EMDS MPC8360 - ------------------------------------------------------------------------- Unknown / orphaned boards: @@ -606,6 +611,16 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com> r5200 mcf52x2 +TsiChung Liew <Tsi-Chung.Liew@freescale.com> + + M5235EVB mcf52x2 + M5329EVB mcf532x + M54455EVB mcf5445x + +Hayden Fraser <Hayden.Fraser@freescale.com> + + M5253EVBE mcf52x2 + ######################################################################### # AVR32 Systems: # # # @@ -204,6 +204,7 @@ LIST_4xx=" \ PLU405 \ PMC405 \ PPChameleonEVB \ + rainier \ sbc405 \ sc3 \ sequoia \ @@ -298,6 +299,7 @@ LIST_8260=" \ LIST_83xx=" \ MPC8313ERDB_33 \ MPC8313ERDB_66 \ + MPC8323ERDB \ MPC832XEMDS \ MPC8349EMDS \ MPC8349ITX \ @@ -339,7 +341,7 @@ LIST_85xx=" \ LIST_86xx=" \ MPC8641HPCN \ - SBC8641D \ + sbc8641d \ " ######################################################################### @@ -358,6 +360,12 @@ LIST_74xx=" \ ZUMA \ " +LIST_TSEC=" \ + ${LIST_85xx} \ + ${LIST_86xx} \ + ${LIST_83xx} \ +" + LIST_7xx=" \ BAB7xx \ CPCI750 \ @@ -612,11 +620,16 @@ LIST_coldfire=" \ EB+MCF-EV123 \ EB+MCF-EV123_internal \ idmr \ + M5235EVB \ + M5249EVB \ + M5253EVB \ M5271EVB \ M5272C3 \ M5282EVB \ - TASREG \ + M5329EVB \ + M54455EVB \ r5200 \ + TASREG \ " ######################################################################### @@ -672,7 +685,7 @@ do mips|mips_el| \ nios|nios2| \ ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ - x86|I486) + x86|I486|TSEC) for target in `eval echo '$LIST_'${arg}` do build_target ${target} @@ -190,6 +190,8 @@ endif OBJS := $(addprefix $(obj),$(OBJS)) LIBS = lib_generic/libgeneric.a +LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \ + "board/$(VENDOR)/common/lib$(VENDOR).a"; fi) LIBS += board/$(BOARDDIR)/lib$(BOARD).a LIBS += cpu/$(CPU)/lib$(CPU).a ifdef SOC @@ -210,13 +212,14 @@ LIBS += drivers/libdrivers.a LIBS += drivers/bios_emulator/libatibiosemu.a LIBS += drivers/nand/libnand.a LIBS += drivers/nand_legacy/libnand_legacy.a -LIBS += drivers/net/libnetdrv.a +LIBS += drivers/net/libnet.a ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/qe.a endif ifeq ($(CPU),mpc85xx) LIBS += drivers/qe/qe.a endif +LIBS += drivers/serial/libserial.a LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/drivers/libpostdrivers.a LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \ @@ -1639,6 +1642,31 @@ ZPC1900_config: unconfig ## Coldfire ######################################################################### +M5235EVB_config \ +M5235EVB_Flash16_config \ +M5235EVB_Flash32_config: unconfig + @case "$@" in \ + M5235EVB_config) FLASH=16;; \ + M5235EVB_Flash16_config) FLASH=16;; \ + M5235EVB_Flash32_config) FLASH=32;; \ + esac; \ + >include/config.h ; \ + if [ "$${FLASH}" != "16" ] ; then \ + echo "#define NORFLASH_PS32BIT 1" >> include/config.h ; \ + echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \ + cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \ + else \ + echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \ + cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \ + fi + @$(MKCONFIG) -a M5235EVB m68k mcf523x m5235evb freescale + +M5249EVB_config : unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale + +M5253EVBE_config : unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale + cobra5272_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272 @@ -1674,6 +1702,46 @@ TASREG_config : unconfig r5200_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200 +M5329AFEE_config \ +M5329BFEE_config : unconfig + @case "$@" in \ + M5329AFEE_config) NAND=0;; \ + M5329BFEE_config) NAND=16;; \ + esac; \ + >include/config.h ; \ + if [ "$${NAND}" != "0" ] ; then \ + echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \ + fi + @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale + +M54455EVB_config \ +M54455EVB_atmel_config \ +M54455EVB_intel_config \ +M54455EVB_a33_config \ +M54455EVB_a66_config \ +M54455EVB_i33_config \ +M54455EVB_i66_config : unconfig + @case "$@" in \ + M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \ + M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \ + M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \ + M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \ + esac; \ + >include/config.h ; \ + if [ "$${FLASH}" == "INTEL" ] ; then \ + echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ + echo "... with INTEL boot..." ; \ + else \ + echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ + echo "... with ATMEL boot..." ; \ + fi; \ + echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ + echo "... with $${FREQ}Hz input clock" + @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale + ######################################################################### ## MPC83xx Systems ######################################################################### @@ -1690,7 +1758,7 @@ MPC8313ERDB_66_config: unconfig echo -n "...66M..." ; \ echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \ fi ; - @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb + @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale MPC8323ERDB_config: unconfig @$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale @@ -1718,10 +1786,10 @@ MPC832XEMDS_SLAVE_config: unconfig echo -n "...66M..." ; \ echo "#define PCI_66M" >>$(obj)include/config.h ; \ fi ; - @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds + @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale MPC8349EMDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale MPC8349ITX_config \ MPC8349ITX_LOWBOOT_config \ @@ -1735,7 +1803,7 @@ MPC8349ITXGP_config: unconfig @if [ "$(findstring LOWBOOT,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi - @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx + @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale MPC8360EMDS_config \ MPC8360EMDS_HOST_33_config \ @@ -1760,7 +1828,7 @@ MPC8360EMDS_SLAVE_config: unconfig echo -n "...66M..." ; \ echo "#define PCI_66M" >>$(obj)include/config.h ; \ fi ; - @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds + @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 @@ -1902,7 +1970,7 @@ TQM8560_config: unconfig ######################################################################### MPC8641HPCN_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn + @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale sbc8641d_config: unconfig @./mkconfig $(@:_config=) ppc mpc86xx sbc8641d @@ -2267,6 +2335,9 @@ scpu_config: unconfig pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +trizepsiv_config : unconfig + @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 @@ -136,6 +136,8 @@ Directory Hierarchy: - i386 Files specific to i386 CPUs - ixp Files specific to Intel XScale IXP CPUs - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs + - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs + - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs - mips Files specific to MIPS CPUs - mpc5xx Files specific to Freescale MPC5xx CPUs - mpc5xxx Files specific to Freescale MPC5xxx CPUs @@ -336,7 +338,7 @@ The following options need to be configured: CONFIG_OF_LIBFDT * New libfdt-based support * Adds the "fdt" command - * The bootm command does _not_ modify the fdt + * The bootm command automatically updates the fdt CONFIG_OF_FLAT_TREE * Deprecated, see CONFIG_OF_LIBFDT @@ -345,15 +347,13 @@ The following options need to be configured: * The environment variable "disable_of", when set, disables this functionality. - CONFIG_OF_FLAT_TREE_MAX_SIZE - - The maximum size of the constructed OF tree. - OF_CPU - The proper name of the cpus node. OF_SOC - The proper name of the soc node. OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device + boards with QUICC Engines require OF_QE to set UCC mac addresses + CONFIG_OF_HAS_BD_T * CONFIG_OF_LIBFDT - enables the "fdt bd_t" command @@ -363,7 +363,7 @@ The following options need to be configured: CONFIG_OF_HAS_UBOOT_ENV - * CONFIG_OF_LIBFDT - enables the "fdt bd_t" command + * CONFIG_OF_LIBFDT - enables the "fdt env" command * CONFIG_OF_FLAT_TREE - The resulting flat device tree will have a copy of u-boot's environment variables diff --git a/board/BuS/EB+MCF-EV123/Makefile b/board/BuS/EB+MCF-EV123/Makefile index ed3ac07..ceeffa7 100644 --- a/board/BuS/EB+MCF-EV123/Makefile +++ b/board/BuS/EB+MCF-EV123/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o +COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c new file mode 100644 index 0000000..ebd3ed9 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CFG_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake Binary files differdeleted file mode 100755 index 4d6ccb3..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp Binary files differdeleted file mode 100755 index d372949..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo Binary files differdeleted file mode 100755 index 6f65d41..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm Binary files differdeleted file mode 100755 index 7de5030..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep b/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep Binary files differdeleted file mode 100755 index 5451b22..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm Binary files differdeleted file mode 100755 index fbd3352..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm Binary files differdeleted file mode 100755 index dd14a7a..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans b/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans Binary files differdeleted file mode 100755 index a1aea4f..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake Binary files differdeleted file mode 100755 index f198f29..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm Binary files differdeleted file mode 100755 index e312a0b..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm Binary files differdeleted file mode 100755 index 9fe81a3..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans Binary files differdeleted file mode 100755 index e536c04..0000000 --- a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj b/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj Binary files differdeleted file mode 100644 index edd8809..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj +++ /dev/null diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj Binary files differdeleted file mode 100644 index 5533346..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj +++ /dev/null diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds index 038d849..34ceb0f 100644 --- a/board/ads5121/u-boot.lds +++ b/board/ads5121/u-boot.lds @@ -51,7 +51,6 @@ SECTIONS { cpu/mpc512x/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 5202ae6..e3f3da6 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -67,9 +67,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -109,9 +109,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index b804d55..afd60ec 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -392,16 +392,18 @@ int katmai_pcie_card_present(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for katmai card presence */ if (!katmai_pcie_card_present(i)) @@ -418,8 +420,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -439,10 +441,21 @@ void pcie_setup_hoses(void) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index 6fc60ea..f3803c0 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -26,76 +26,185 @@ #include <command.h> #include <i2c.h> -static u8 boot_533_nor[] = { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 -}; +/* + * There are 2 versions of production Sequoia & Rainier platforms. + * The primary difference is the reference clock. Those with + * 33333333 reference clocks will also have 667MHz rated + * processors. Not enough differences to have unique clock + * settings. + * + * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The + * values are independent of the rest of the clock settings. + * + * All Sequoias & Rainiers select from two possible EEPROMs in Boot + * Config F. One for 33MHz PCI, one for 66MHz PCI. The following + * values are for the 33MHz PCI configuration. Byte 5 (0 base) is + * the only value affected for a 66MHz PCI and simply needs a +0x10. + */ + +#define NAND_COMPATIBLE 0x01 +#define NOR_COMPATIBLE 0x02 + +/* check with Stefan on CFG_I2C_EEPROM_ADDR */ +#define I2C_EEPROM_ADDR 0x52 -static u8 boot_533_nand[] = { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 +static char *config_labels[] = { + "CPU: 333 PLB: 133 OPB: 66 EBC: 66", + "CPU: 333 PLB: 166 OPB: 83 EBC: 55", + "CPU: 400 PLB: 133 OPB: 66 EBC: 66", + "CPU: 400 PLB: 160 OPB: 80 EBC: 53", + "CPU: 416 PLB: 166 OPB: 83 EBC: 55", + "CPU: 500 PLB: 166 OPB: 83 EBC: 55", + "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + "CPU: 667 PLB: 166 OPB: 83 EBC: 55", + NULL }; -static u8 boot_667_nor[] = { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 +static u8 boot_configs[][17] = { + { + (NOR_COMPATIBLE), + 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + } }; -static u8 boot_667_nand[] = { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 +/* + * Bytes 6,8,9,11 change for NAND boot + */ +static u8 nand_boot[] = { + 0xd0, 0xa0, 0x68, 0x58 }; static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u8 chip; - u8 *buf; - int cpu_freq; + u8 *buf, bNAND; + int x, y, nbytes, selcfg; + extern char console_buffer[]; - if (argc < 3) { + if (argc < 2) { printf("Usage:\n%s\n", cmdtp->usage); return 1; } - cpu_freq = simple_strtol(argv[1], NULL, 10); - if (!((cpu_freq == 533) || (cpu_freq == 667))) { - printf("Unsupported cpu-frequency - only 533 and 667 supported\n"); + if ((strcmp(argv[1], "nor") != 0) && + (strcmp(argv[1], "nand") != 0)) { + printf("Unsupported boot-device - only nor|nand support\n"); return 1; } - /* use 0x52 as I2C EEPROM address for now */ - chip = 0x52; + /* set the nand flag based on provided input */ + if ((strcmp(argv[1], "nand") == 0)) + bNAND = 1; + else + bNAND = 0; - if ((strcmp(argv[2], "nor") != 0) && - (strcmp(argv[2], "nand") != 0)) { - printf("Unsupported boot-device - only nor|nand support\n"); - return 1; - } + printf("Available configurations: \n\n"); - if (strcmp(argv[2], "nand") == 0) { - switch (cpu_freq) { - default: - case 533: - buf = boot_533_nand; - break; - case 667: - buf = boot_667_nand; - break; + if (bNAND) { + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nand compatible */ + if (boot_configs[x][0] & NAND_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } } } else { - switch (cpu_freq) { - default: - case 533: - buf = boot_533_nor; - break; - case 667: - buf = boot_667_nor; - break; + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nor compatible */ + if (boot_configs[x][0] & NOR_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } } } - if (i2c_write(chip, 0, 1, buf, 16) != 0) - printf("Error writing to EEPROM at address 0x%x\n", chip); + do { + nbytes = readline(" Selection [1-x / quit]: "); + + if (nbytes) { + if (strcmp(console_buffer, "quit") == 0) + return 0; + selcfg = simple_strtol(console_buffer, NULL, 10); + if ((selcfg < 1) || (selcfg > y)) + nbytes = 0; + } + } while (nbytes == 0); + + + y = (selcfg - 1); + + for (x = 0; boot_configs[x][0] != 0; x++) { + if (bNAND) { + if (boot_configs[x][0] & NAND_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } else { + if (boot_configs[x][0] & NOR_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } + } + + buf = &boot_configs[x][1]; + + if (bNAND) { + buf[6] = nand_boot[0]; + buf[8] = nand_boot[1]; + buf[9] = nand_boot[2]; + buf[11] = nand_boot[3]; + } + + /* check CPLD register +5 for PCI 66MHz flag */ + if (in8(CFG_BCSR_BASE + 5) & 0x01) + buf[5] += 0x10; + + if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) + printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); printf("Done\n"); @@ -105,7 +214,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - bootstrap, 3, 0, do_bootstrap, + bootstrap, 2, 0, do_bootstrap, "bootstrap - program the I2C bootstrap EEPROM\n", - "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n" + "<nand|nor> - strap to boot from NAND or NOR flash\n" ); diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 45bcd4b..5fe3af9 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -126,6 +126,9 @@ tlbtab: /* TLB-entry for peripherals */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + /* TLB-entry PCI IO Space - from sr@denx.de */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index c92dcf7..67e8f8f 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -70,9 +70,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -112,9 +112,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index d08fcf3..397b018 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -846,16 +846,18 @@ void yucca_setup_pcie_fpga_endpoint(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for yucca card presence */ if (!yucca_pcie_card_present(i)) @@ -874,8 +876,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -895,10 +897,21 @@ void pcie_setup_hoses(void) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 48753d7..36d7e1e 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -362,20 +362,28 @@ pci_init_board(void) ); - /* outbound memory */ + /* inbound */ pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + + /* outbound memory */ + pci_set_region(hose->regions + 1, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 1, + pci_set_region(hose->regions + 2, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 2; + hose->region_count = 3; /* relocate config table pointers */ hose->config_table = \ @@ -534,7 +542,7 @@ ft_pci_setup(void *blob, bd_t *bd) #endif #ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile index cf07cf4..be704b7 100644 --- a/board/cobra5272/Makefile +++ b/board/cobra5272/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 26adb4a..86c7ee1 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -22,8 +22,7 @@ */ #include <common.h> -#include <asm/m5272.h> -#include <asm/immap_5272.h> +#include <asm/immap.h> int checkboard (void) @@ -35,7 +34,7 @@ int checkboard (void) long int initdram (int board_type) { - volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR); + volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM); sdp->sdram_sdtr = 0xf539; sdp->sdram_sdcr = 0x4211; diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c new file mode 100644 index 0000000..fadcbb3 --- /dev/null +++ b/board/cobra5272/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile index 4d75868..308f752 100644 --- a/board/esd/ash405/Makefile +++ b/board/esd/ash405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index f41eb7b..8a5b03b 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> @@ -33,6 +34,7 @@ #endif extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -164,18 +166,12 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -218,35 +214,17 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ -int testdram (void) +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} +#ifdef CONFIG_LXT971_NO_SLEEP + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); #endif +} diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile index df48766..0d4ab2d 100644 --- a/board/esd/cms700/Makefile +++ b/board/esd/cms700/Makefile @@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + $(CPLD) \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 635ba2f..2cdd7be 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2007 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> @@ -68,9 +69,9 @@ int board_early_init_f (void) /* * Reset CPLD via GPIO12 (CS3) pin */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET); udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET); udelay(1000); /* wait 1ms */ return 0; @@ -94,13 +95,7 @@ int misc_init_r (void) /* * Setup and enable EEPROM write protection */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); return (0); } @@ -153,11 +148,6 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } @@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state) switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP)); break; } } @@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 62f6c20..a76b00f 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -24,14 +24,12 @@ #include <common.h> -#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) -#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support! -#endif - #include <command.h> #include <image.h> #include <asm/byteorder.h> +#if defined(CFG_NAND_LEGACY) #include <linux/mtd/nand_legacy.h> +#endif #include <fat.h> #include <part.h> @@ -294,6 +292,8 @@ int au_do_update(int i, long sz) rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); +#else + rc = -1; #endif } if (rc != 0) { diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c new file mode 100644 index 0000000..7bf6847 --- /dev/null +++ b/board/esd/common/esd405ep_nand.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_CMD_NAND) +#include <asm/io.h> +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + switch(cmd) { + case NAND_CTL_SETCLE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); + break; + case NAND_CTL_CLRCLE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); + break; + case NAND_CTL_SETALE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); + break; + case NAND_CTL_CLRALE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); + break; + case NAND_CTL_SETNCE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); + break; + case NAND_CTL_CLRNCE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + break; + } +} + + +/* + * read device ready pin + */ +static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) +{ + if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY) + return 1; + return 0; +} + + +int board_nand_init(struct nand_chip *nand) +{ + /* + * Set NAND-FLASH GPIO signals to defaults + */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + + /* + * Initialize nand_chip structure + */ + nand->hwcontrol = esd405ep_nand_hwcontrol; + nand->dev_ready = esd405ep_nand_device_ready; + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_BIG_DELAY_US; + nand->options = NAND_SAMSUNG_LP_OPTIONS; + return 0; +} +#endif diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 17e3568..298aa6a 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -55,6 +55,71 @@ #define DP(x) #endif +static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */ + {"PCI0DLL_1 "}, /* 30 */ + {"PCI0DLL_0 "}, /* 29 */ + {"PCI1DLL_2 "}, /* 28 */ + {"PCI1DLL_1 "}, /* 27 */ + {"PCI1DLL_0 "}, /* 26 */ + {"BbEP2En "}, /* 25 */ + {"SDRAMRdDataDel"}, /* 24 */ + {"SDRAMRdDel "}, /* 23 */ + {"SDRAMSync "}, /* 22 */ + {"SDRAMPipeSel_1"}, /* 21 */ + {"SDRAMPipeSel_0"}, /* 20 */ + {"SDRAMAddDel "}, /* 19 */ + {"SDRAMClkSel "}, /* 18 */ + {"Reserved(1!) "}, /* 17 */ + {"PCIRty "}, /* 16 */ + {"BootCSWidth_1 "}, /* 15 */ + {"BootCSWidth_0 "}, /* 14 */ + {"PCI1PadsCal "}, /* 13 */ + {"PCI0PadsCal "}, /* 12 */ + {"MultiMVId_1 "}, /* 11 */ + {"MultiMVId_0 "}, /* 10 */ + {"MultiGTEn "}, /* 09 */ + {"Int60xArb "}, /* 08 */ + {"CPUBusConfig_1"}, /* 07 */ + {"CPUBusConfig_0"}, /* 06 */ + {"DefIntSpc "}, /* 05 */ + {0 }, /* 04 */ + {"SROMAdd_1 "}, /* 03 */ + {"SROMAdd_0 "}, /* 02 */ + {"DRAMPadCal "}, /* 01 */ + {"SInitEn "}, /* 00 */ + {0 }, /* 31 */ + {0 }, /* 30 */ + {0 }, /* 29 */ + {0 }, /* 28 */ + {0 }, /* 27 */ + {0 }, /* 26 */ + {0 }, /* 25 */ + {0 }, /* 24 */ + {0 }, /* 23 */ + {0 }, /* 22 */ + {"JTAGCalBy "}, /* 21 */ + {"GB2Sel "}, /* 20 */ + {"GB1Sel "}, /* 19 */ + {"DRAMPLL_MDiv_5"}, /* 18 */ + {"DRAMPLL_MDiv_4"}, /* 17 */ + {"DRAMPLL_MDiv_3"}, /* 16 */ + {"DRAMPLL_MDiv_2"}, /* 15 */ + {"DRAMPLL_MDiv_1"}, /* 14 */ + {"DRAMPLL_MDiv_0"}, /* 13 */ + {"GB0Sel "}, /* 12 */ + {"DRAMPLLPU "}, /* 11 */ + {"DRAMPLL_HIKVCO"}, /* 10 */ + {"DRAMPLLNP "}, /* 09 */ + {"DRAMPLL_NDiv_7"}, /* 08 */ + {"DRAMPLL_NDiv_6"}, /* 07 */ + {"CPUPadCal "}, /* 06 */ + {"DRAMPLL_NDiv_5"}, /* 05 */ + {"DRAMPLL_NDiv_4"}, /* 04 */ + {"DRAMPLL_NDiv_3"}, /* 03 */ + {"DRAMPLL_NDiv_2"}, /* 02 */ + {"DRAMPLL_NDiv_1"}, /* 01 */ + {"DRAMPLL_NDiv_0"}}; /* 00 */ + extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); extern flash_info_t flash_info[]; @@ -901,21 +966,37 @@ void board_prebootm_init () dcache_disable (); } - -int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { unsigned int reset_sample_low; unsigned int reset_sample_high; + unsigned int l, l1, l2; GT_REG_READ(0x3c4, &reset_sample_low); GT_REG_READ(0x3d4, &reset_sample_high); printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high); + l2 = 0; + for (l=0; l<63; l++) { + if (show_config_tab[l][0] != 0) { + printf("%14s:%1x ", show_config_tab[l], + ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01); + l2++; + if ((l2 % 4) == 0) + printf("\n"); + } else { + l1++; + } + if (l == 32) + reset_sample_low = reset_sample_high; + } + printf("\n"); + return(0); } U_BOOT_CMD( - show_cfg, 1, 1, do_show_cfg, - "show_cfg- Show Marvell strapping register\n", + show_config, 1, 1, do_show_config, + "show_config - Show Marvell strapping register\n", "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n" ); diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index 01b90c6..0adafe2 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -43,6 +43,8 @@ int ide_preinit (void) ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device (0x1103, 0x0004, 0); + if (devbusfn == -1) + devbusfn = pci_find_device (0x1095, 0x3114, 0); if (devbusfn != -1) { status = 0; diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile index ce7876c..0e5e57a 100644 --- a/board/esd/hh405/Makefile +++ b/board/esd/hh405/Makefile @@ -28,7 +28,10 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 9ef5907..67b5d54 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -5,7 +5,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -477,12 +477,6 @@ int misc_init_r (void) out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Reset touch-screen controller */ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST); @@ -690,20 +684,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - #if defined(CFG_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile index 4d75868..308f752 100644 --- a/board/esd/hub405/Makefile +++ b/board/esd/hub405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index dd3706e..25c8068 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -153,12 +153,6 @@ int misc_init_r (void) out32(GPIO0_OR, val); /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * check board type and setup AP power */ str = getenv("bd_type"); /* this is only set on non prototype hardware */ @@ -242,33 +236,5 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile index ce7876c..0e5e57a 100644 --- a/board/esd/plu405/Makefile +++ b/board/esd/plu405/Makefile @@ -28,7 +28,10 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 920f717..f026a7a 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> @@ -31,6 +32,8 @@ #define FPGA_DEBUG #endif +DECLARE_GLOBAL_DATA_PTR; + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); @@ -114,6 +117,10 @@ int misc_init_r (void) int index; int i; + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + dst = malloc(CFG_FPGA_MAX_SIZE); if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); @@ -177,18 +184,12 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -226,24 +227,10 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { @@ -262,31 +249,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - -#ifdef CONFIG_AUTO_UPDATE_SHOW -void board_auto_update_show(int au_active) -{ - if (au_active) { - printf("\n Dies ist die board-funktion: Updating!!!\n"); - } else { - printf("\n Dies ist die board-funktion: Updating done!!!\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile index 4d75868..308f752 100644 --- a/board/esd/voh405/Makefile +++ b/board/esd/voh405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 3e118e7..2857a0be 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -195,12 +195,6 @@ int misc_init_r (void) udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -340,17 +334,3 @@ void ide_set_reset(int on) } } #endif /* CONFIG_IDE_RESET */ - - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile index 4d75868..308f752 100644 --- a/board/esd/wuh405/Makefile +++ b/board/esd/wuh405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 61d1d6c..dba3ce8 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -170,12 +170,6 @@ int misc_init_r (void) udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -218,35 +212,5 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/fads/fads.h b/board/fads/fads.h index c6f7ccd..a7fe2e9 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -71,7 +71,10 @@ #undef CONFIG_BOOTARGS #undef CONFIG_WATCHDOG /* watchdog disabled */ + +#if !defined(CONFIG_MPC885ADS) #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#endif /* * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile new file mode 100644 index 0000000..44f613e --- /dev/null +++ b/board/freescale/common/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS := sys_eeprom.o \ + pixis.o \ + pq-mds-pib.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 99cc2ee..ae4bef1 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -27,6 +27,8 @@ #include <watchdog.h> #include <asm/cache.h> +#ifdef CONFIG_FSL_PIXIS + #include "pixis.h" @@ -470,3 +472,4 @@ U_BOOT_CMD( " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n" " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n" ); +#endif /* CONFIG_FSL_PIXIS */ diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c new file mode 100644 index 0000000..d79f2eb --- /dev/null +++ b/board/freescale/common/pq-mds-pib.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Tony Li <tony.li@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> + +#ifdef CONFIG_PQ_MDS_PIB + +#include "pq-mds-pib.h" + +int pib_init(void) +{ + u8 val8; + u8 orig_i2c_bus; + + /* Switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + val8 = 0; +#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) + /* Assign PIB PMC slot to desired PCI bus */ + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); +#if defined(CONFIG_MPC832XEMDS) + val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ +#else + val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ +#endif + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + + eieio(); + +#if defined(CONFIG_MPC832XEMDS) + printf("PCI 32bit bus on PMC2 &PMC3\n"); +#else + printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); +#endif +#endif + +#if defined(CONFIG_PQ_MDS_PIB_ATM) +#if defined(CONFIG_MPC8360EMDS) + val8 = 0; + i2c_write(0x20, 0x6, 1, &val8, 1); + i2c_write(0x20, 0x7, 1, &val8, 1); + + val8 = 0xdf; + i2c_write(0x20, 0x2, 1, &val8, 1); + val8 = 0xf7; + i2c_write(0x20, 0x3, 1, &val8, 1); + + eieio(); + + printf("QOC3 ATM card on PMC0\n"); +#elif defined(CONFIG_MPC832XEMDS) + val = 0; + i2c_write(0x26, 0x7, 1, &val, 1); + val = 0xf7; + i2c_write(0x26, 0x3, 1, &val, 1); + + val = 0; + i2c_write(0x21, 0x6, 1, &val, 1); + i2c_write(0x21, 0x7, 1, &val, 1); + + val = 0xdf; + i2c_write(0x21, 0x2, 1, &val, 1); + val = 0xef; + i2c_write(0x21, 0x3, 1, &val, 1); + + eieio(); + + printf("QOC3 ATM card on PMC1\n"); +#endif +#endif + /* Reset to original I2C bus */ + i2c_set_bus_num(orig_i2c_bus); + return 0; +} +#endif /* CONFIG_PQ_MDS_PIB */ diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h new file mode 100644 index 0000000..67066fd --- /dev/null +++ b/board/freescale/common/pq-mds-pib.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +extern int pib_init(void); diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 7bc663b..7bc663b 100644 --- a/board/mpc8641hpcn/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile new file mode 100644 index 0000000..74c2528 --- /dev/null +++ b/board/freescale/m5235evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5235evb/config.mk b/board/freescale/m5235evb/config.mk new file mode 100644 index 0000000..ada38dd --- /dev/null +++ b/board/freescale/m5235evb/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +/*TEXT_BASE = 0xFFC00000*/ +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
\ No newline at end of file diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c new file mode 100644 index 0000000..585854c --- /dev/null +++ b/board/freescale/m5235evb/m5235evb.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M5235 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 dramsize, i, dramclk; + + /* + * When booting from external Flash, the port-size is less than + * the port-size of SDRAM. In this case it is necessary to enable + * Data[15:0] on Port Address/Data. + */ + gpio->par_ad = + GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | + GPIO_PAR_AD_DATAL; + + /* Initialize PAR to enable SDRAM signals */ + gpio->par_sdram = + GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS | + GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3); + + dramsize = CFG_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) { + dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + + /* Initialize DRAM Control Register: DCR */ + sdram->dcr = SDRAMC_DCR_RTIM_9CLKS | + SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4); + + /* Initialize DACR0 */ + sdram->dacr0 = + SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | + SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32; + + /* Initialize DMR0 */ + sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V; + + /* Set IP (bit 3) in DACR */ + sdram->dacr0 |= SDRAMC_DARCn_IP; + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + sdram->dacr0 |= SDRAMC_DARCn_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 0x2000; i++) { + asm("nop"); + } + + /* Finish the configuration by issuing the MRS. */ + sdram->dacr0 |= SDRAMC_DARCn_IMRS; + + /* Write to the SDRAM Mode Register */ + *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + } + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c new file mode 100644 index 0000000..58fabdf --- /dev/null +++ b/board/freescale/m5235evb/mii.c @@ -0,0 +1,307 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5235evb/u-boot.16 b/board/freescale/m5235evb/u-boot.16 new file mode 100644 index 0000000..8ffd326 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.16 @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu_init.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5235evb/u-boot.32 b/board/freescale/m5235evb/u-boot.32 new file mode 100644 index 0000000..9b72f66 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.32 @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu.o (.text) + cpu/mcf523x/cpu_init.o (.text) + cpu/mcf523x/interrupts.o (.text) + cpu/mcf523x/speed.o (.text) + lib_m68k/libm68k.a (.text) + common/dlmalloc.o (.text) + common/cmd_bootm.o (.text) + common/cmd_flash.o (.text) + common/cmd_elf.o (.text) + common/cmd_mem.o (.text) + common/console.o (.text) + common/main.o (.text) + lib_generic/libgeneric.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds new file mode 100644 index 0000000..8ffd326 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu_init.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5249evb/Makefile b/board/freescale/m5249evb/Makefile new file mode 100644 index 0000000..424ab1c --- /dev/null +++ b/board/freescale/m5249evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5249evb/config.mk b/board/freescale/m5249evb/config.mk new file mode 100644 index 0000000..ccb2cf7 --- /dev/null +++ b/board/freescale/m5249evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c new file mode 100644 index 0000000..e8f621b --- /dev/null +++ b/board/freescale/m5249evb/m5249evb.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/immap.h> + + +/* Prototypes */ +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +int checkboard (void) { + ulong val; + uchar val8; + + puts ("Board: "); + puts("Freescale M5249EVB"); + val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; + printf(" (Switch=%1X)\n", val8); + + /* + * Set LED on + */ + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED; + mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ + + return 0; +}; + + +long int initdram (int board_type) { + unsigned long junk = 0xa5a59696; + + /* + * Note: + * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 + */ + +#ifdef CFG_FAST_CLK + /* + * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 + */ + mbar_writeShort(MCFSIM_DCR, 0x8239); +#elif CFG_PLL_BYPASS + /* + * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 + */ + mbar_writeShort(MCFSIM_DCR, 0x8202); +#else + /* + * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) + */ + mbar_writeShort(MCFSIM_DCR, 0x8222); +#endif + + /* + * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), + * PM=1 (continuous page mode) + */ + + /* RE=0 (keep auto-refresh disabled while setting up registers) */ + mbar_writeLong(MCFSIM_DACR0, 0x00003324); + + /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ + mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); + + /** Precharge sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ + *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ + udelay(0x10); /* Allow several Precharge cycles */ + + /** Refresh Sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ + udelay(0x7d0); /* Allow gobs of refresh cycles */ + + /** Mode Register initialization **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ + *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + + +int testdram (void) { + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds new file mode 100644 index 0000000..a803b1c --- /dev/null +++ b/board/freescale/m5249evb/u-boot.lds @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5253evbe/Makefile b/board/freescale/m5253evbe/Makefile new file mode 100644 index 0000000..424ab1c --- /dev/null +++ b/board/freescale/m5253evbe/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5253evbe/config.mk b/board/freescale/m5253evbe/config.mk new file mode 100644 index 0000000..ccb2cf7 --- /dev/null +++ b/board/freescale/m5253evbe/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c new file mode 100644 index 0000000..43aa84d --- /dev/null +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/immap.h> + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale MCF5253 EVBE\n"); + return 0; +}; + +long int initdram(int board_type) +{ + int i; + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { + u32 RC, dramsize; + + RC = (CFG_CLK / 1000000) >> 1; + RC = (RC * 15) >> 4; + + /* Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); + + mbar_writeLong(MCFSIM_DACR0, 0x00003224); + + /* Initialize DMR0 */ + dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; + mbar_writeLong(MCFSIM_DMR0, dramsize | 1); + + mbar_writeLong(MCFSIM_DACR0, 0x0000322c); + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; + + /* Set RE bit in DACR */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x8000); + + /* Wait for at least 8 auto refresh cycles to occur */ + udelay(500); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x0040); + + *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + } + + return CFG_SDRAM_SIZE * 1024 * 1024; +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CONFIG_CMD_IDE +#include <ata.h> +int ide_preinit(void) +{ + return (0); +} + +void ide_set_reset(int idereset) +{ + volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ + }; + + if (idereset) { + ata->cr = 0; /* control reset */ + udelay(100); + } else { + mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); + +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / (CFG_CLK / 2); /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + ata->t1 = CALC_TIMING(piotms[2][0]); + ata->t2w = CALC_TIMING(piotms[2][1]); + ata->t2r = CALC_TIMING(piotms[2][1]); + ata->ta = CALC_TIMING(piotms[2][8]); + ata->trd = CALC_TIMING(piotms[2][7]); + ata->t4 = CALC_TIMING(piotms[2][3]); + ata->t9 = CALC_TIMING(piotms[2][6]); + + ata->cr = 0x40; /* IORDY enable */ + udelay(2000); + ata->cr |= 0x01; /* IORDY enable */ + } +} +#endif /* CONFIG_CMD_IDE */ diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds new file mode 100644 index 0000000..e2fd070 --- /dev/null +++ b/board/freescale/m5253evbe/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile new file mode 100644 index 0000000..ab0f11e --- /dev/null +++ b/board/freescale/m5329evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o mii.o nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5329evb/config.mk b/board/freescale/m5329evb/config.mk new file mode 100644 index 0000000..ce014ed --- /dev/null +++ b/board/freescale/m5329evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c new file mode 100644 index 0000000..242eb1a --- /dev/null +++ b/board/freescale/m5329evb/m5329evb.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale FireEngine 5329 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + sdram->cs0 = (CFG_SDRAM_BASE | i); + sdram->cfg1 = CFG_SDRAM_CFG1; + sdram->cfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->ctrl = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + sdram->mode = CFG_SDRAM_EMOD; + sdram->mode = (CFG_SDRAM_MODE | 0x04000000); + + udelay(500); + + /* Issue PALL */ + sdram->ctrl = (CFG_SDRAM_CTRL | 2); + + /* Perform two refresh cycles */ + sdram->ctrl = CFG_SDRAM_CTRL | 4; + sdram->ctrl = CFG_SDRAM_CTRL | 4; + + sdram->mode = CFG_SDRAM_MODE; + + sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c new file mode 100644 index 0000000..31f1510 --- /dev/null +++ b/board/freescale/m5329evb/mii.c @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + } else { + gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c new file mode 100644 index 0000000..fefb42e --- /dev/null +++ b/board/freescale/m5329evb/nand.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NAND) +#include <nand.h> +#include <linux/mtd/mtd.h> + +#define SET_CLE 0x10 +#define CLR_CLE ~SET_CLE +#define SET_ALE 0x08 +#define CLR_ALE ~SET_ALE + +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + struct nand_chip *this = mtdinfo->priv; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + u32 nand_baseaddr = (u32) this->IO_ADDR_W; + + switch (cmd) { + case NAND_CTL_SETNCE: + case NAND_CTL_CLRNCE: + break; + case NAND_CTL_SETCLE: + nand_baseaddr |= SET_CLE; + break; + case NAND_CTL_CLRCLE: + nand_baseaddr &= CLR_CLE; + break; + case NAND_CTL_SETALE: + nand_baseaddr |= SET_ALE; + break; + case NAND_CTL_CLRALE: + nand_baseaddr |= CLR_ALE; + break; + case NAND_CTL_SETWP: + fbcs->csmr2 |= CSMR_WP; + break; + case NAND_CTL_CLRWP: + fbcs->csmr2 &= ~CSMR_WP; + break; + } + this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); +} + +static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) +{ + struct nand_chip *this = mtdinfo->priv; + *((volatile u8 *)(this->IO_ADDR_W)) = byte; +} + +static u8 nand_read_byte(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + return (u8) (*((volatile u8 *)this->IO_ADDR_R)); +} + +static int nand_dev_ready(struct mtd_info *mtdinfo) +{ + return 1; +} + +int board_nand_init(struct nand_chip *nand) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; + + /* set up pin configuration */ + gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; + gpio->pddr_timer |= 0x08; + gpio->ppd_timer |= 0x08; + gpio->pclrr_timer = 0; + gpio->podr_timer = 0; + + nand->chip_delay = 50; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = nand_hwcontrol; + nand->read_byte = nand_read_byte; + nand->write_byte = nand_write_byte; + nand->dev_ready = nand_dev_ready; + + return 0; +} +#endif diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds new file mode 100644 index 0000000..9b994a0 --- /dev/null +++ b/board/freescale/m5329evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf532x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile new file mode 100644 index 0000000..ca9a772 --- /dev/null +++ b/board/freescale/m54455evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
\ No newline at end of file diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk new file mode 100644 index 0000000..ce014ed --- /dev/null +++ b/board/freescale/m54455evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m54455evb/flash.c b/board/freescale/m54455evb/flash.c new file mode 100644 index 0000000..de2cca8 --- /dev/null +++ b/board/freescale/m54455evb/flash.c @@ -0,0 +1,974 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <asm/immap.h> + +#ifndef CFG_FLASH_CFI +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_WRSETUP 0x00400040 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CFIQRY 0x00980098 +#define INTEL_SUSERASE 0x00B000B0 +#define INTEL_PROTPROG 0x00C000C0 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_WRBLK 0x00e800e8 +#define INTEL_RESET 0x00FF00FF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 +#define INTEL_ERASESUS 0x00600060 +#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) + +/* 28F160C3B CFI Data offset - This could vary */ +#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ +#define INTEL_CFI_PART 0x01 /* Product ID */ +#define INTEL_CFI_LOCK 0x02 /* */ +#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ +#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ +#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ +#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ +#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ +#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ +#define INTEL_CFI_CAP 0x28 +#define INTEL_CFI_WRBUF 0x2A +#define INTEL_CFI_BANK 0x2C /* Number of Bank */ +#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */ +#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */ +#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ +#define INTEL_CFI_SZ1B 0x30 +#define INTEL_CFI_BLK2A 0x31 +#define INTEL_CFI_BLK2B 0x32 +#define INTEL_CFI_SZ2A 0x33 +#define INTEL_CFI_SZ2B 0x34 + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x0aaa + +#define WR_BLOCK 0x20 + +/* not in the flash.h yet */ +#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */ +#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */ +#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */ +#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */ +#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */ +#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */ + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int flash_cmd_rd(volatile u16 * addr, int index); +int write_data(flash_info_t * info, ulong dest, FPW data); +int write_data_block(flash_info_t * info, ulong src, ulong dest); +int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data); +void inline spin_wheel(void); +void flash_sync_real_protect(flash_info_t * info); +uchar intel_sector_protected(flash_info_t * info, ushort sector); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + int i; + ulong size = 0; + ulong fbase = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + switch (i) { + case 0: + fbase = (ulong) CFG_FLASH0_BASE; + break; + case 1: + fbase = (ulong) CFG_FLASH1_BASE; + break; + } + + flash_get_size((FPWV *) fbase, &flash_info[i]); + flash_get_offsets((ulong) fbase, &flash_info[i]); + fbase += flash_info[i].size; + size += flash_info[i].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +int flash_get_offsets(ulong base, flash_info_t * info) +{ + int i, j, k; + int sectors, bs, banks; + ulong start; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) { + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + + info->start[0] = base; + for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) { + for (j = 0; j < sect[i]; j++, k++) { + info->start[k + 1] = info->start[k] + sectsz[i]; + info->protect[k] = 0; + } + } + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + volatile u16 *addr16 = (volatile u16 *)base; + + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + *addr16 = (FPW) INTEL_READID; + + banks = addr16[INTEL_CFI_BANK] & 0xff; + + sectors = 0; + info->start[0] = base; + + for (k = 0, i = 0; i < banks; i++) { + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) + | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * + 0x100); + sectors = + (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; + + for (j = 0; j < sectors; j++, k++) { + info->start[k + 1] = info->start[k] + bs; + } + } + + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + } + + return ERR_OK; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + case FLASH_MAN_ATM: + printf("ATMEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AT040: + printf("AT49BV040A\n"); + break; + case FLASH_28F128J3A: + printf("Intel 28F128J3A\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size > 0x100000) { + int remainder; + + printf(" Size: %ld", info->size >> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder >>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + volatile u16 *addr16 = (volatile u16 *)addr; + int intel = 0, banks = 0; + u16 value; + int i; + + addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ + + switch (addr[0] & 0xff) { + case (u8) ATM_MANUFACT: + info->flash_id = FLASH_MAN_ATM; + value = addr[1]; + break; + case (u8) INTEL_MANUFACT: + /* Terminate Atmel ID read */ + addr[0] = (FPWV) 0x00F000F0; + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + *addr16 = (FPW) INTEL_READID; + + info->flash_id = FLASH_MAN_INTEL; + value = (addr16[INTEL_CFI_MFG] << 8); + value |= addr16[INTEL_CFI_PART] & 0xff; + intel = 1; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + + *addr = (FPW) 0x00F000F0; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u8) ATM_ID_LV040: + info->flash_id += FLASH_AT040; + break; + case (u16) INTEL_ID_28F128J3: + info->flash_id += FLASH_28F128J3A; + break; + case (u16) INTEL_ID_28F64P30T: + info->flash_id += FLASH_28F64P30T; + break; + case (u16) INTEL_ID_28F64P30B: + info->flash_id += FLASH_28F64P30B; + break; + case (u16) INTEL_ID_28F128P30T: + info->flash_id += FLASH_28F128P30T; + break; + case (u16) INTEL_ID_28F128P30B: + info->flash_id += FLASH_28F128P30B; + break; + case (u16) INTEL_ID_28F256P30T: + info->flash_id += FLASH_28F256P30T; + break; + case (u16) INTEL_ID_28F256P30B: + info->flash_id += FLASH_28F256P30B; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (intel) { + /* Intel spec. under CFI section */ + u32 sz; + int sectors, bs; + + banks = addr16[INTEL_CFI_BANK] & 0xff; + + sectors = sz = 0; + for (i = 0; i < banks; i++) { + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) + | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * + 0x100); + sectors += + (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; + sz += (bs * sectors); + } + + info->sector_count = sectors; + info->size = sz; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + } else { + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + + info->sector_count = 0; + info->size = 0; + for (i = 0; i < CFG_ATMEL_REGION; i++) { + info->sector_count += sect[i]; + info->size += sect[i] * sectsz[i]; + } + + /* reset ID mode */ + addr[0] = (FPWV) 0x00F000F0; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + return (info->size); +} + +int flash_cmd_rd(volatile u16 * addr, int index) +{ + return (int)addr[index]; +} + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +void flash_sync_real_protect(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +uchar intel_sector_protected(flash_info_t * info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + /*udelay(1); */ + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer(0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector]; + ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0, intel = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + + if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) { + if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) { + type = (info->flash_id & FLASH_VENDMASK); + printf + ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + } + + if (type == FLASH_MAN_INTEL) + intel = 1; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + start = get_timer(0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + FPWV *addr = (FPWV *) (info->start[sect]); + int min = 0; + + printf("."); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + if (intel) { + *addr = (FPW) INTEL_READID; + min = addr[INTEL_CFI_TERB] & 0xff; + min = 1 << min; /* ms */ + min = (min / info->sector_count) * 1000; + + /* start erase block */ + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while ((*addr & (FPW) INTEL_FINISHED) != + (FPW) INTEL_FINISHED) { + + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = (FPW) INTEL_RESET; /* resest to read mode */ + } else { + FPWV *base; /* first address in bank */ + FPWV *atmeladdr; + + flag = disable_interrupts(); + + atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */ + base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */ + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + *atmeladdr = (u8) 0x00300030; /* erase sector */ + + if (flag) + enable_interrupts(); + + while ((*atmeladdr & (u8) 0x00800080) != + (u8) 0x00800080) { + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + } /* Atmel or Intel */ + } + } + printf(" done\n"); + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_ATM: + { + u16 data = 0; + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= + sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } + + data = (data >> 8) | (data << 8); + res = write_word_atm(info, (FPWV *) addr, data); + } + return res; + } /* case FLASH_MAN_ATM */ + + case FLASH_MAN_INTEL: + { + ulong cp, wp; + u16 data; + int count, i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = sizeof(FPW); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_data(info, wp, data)) != 0) + return (rc); + + wp += port_width; + } + + if (cnt > WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= WR_BLOCK) { + + if ((rc = + write_data_block(info, + (ulong) src, + wp)) != 0) + return (rc); + + wp += WR_BLOCK; + src += WR_BLOCK; + cnt -= WR_BLOCK; + + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + } + + /* handle word aligned part */ + if (cnt < WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) + data = (data << 8) | *src++; + + if ((rc = + write_data(info, + (ulong) ((FPWV *) wp), + (FPW) (data))) != 0) + return (rc); + + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; + ++i, ++cp) { + data = (data << 8) | (*src++); + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return write_data(info, (ulong) ((FPWV *) wp), + (FPW) data); + + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data_block(flash_info_t * info, ulong src, ulong dest) +{ + FPWV *srcaddr = (FPWV *) src; + FPWV *dstaddr = (FPWV *) dest; + ulong start; + int flag, i; + + /* Check if Flash is (sufficiently) erased */ + for (i = 0; i < WR_BLOCK; i++) + if ((*dstaddr++ & 0xff) != 0xff) { + printf("not erased at %08lx (%lx)\n", + (ulong) dstaddr, *dstaddr); + return (2); + } + + dstaddr = (FPWV *) dest; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dstaddr = (FPW) INTEL_WRBLK; /* write block setup */ + + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */ + for (i = 0; i < WR_BLOCK; i++) + *dstaddr++ = *srcaddr++; + + dstaddr -= 1; + *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */ + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data(flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = (int)disable_interrupts(); + + *addr = (FPW) INTEL_CLEAR; + *addr = (FPW) INTEL_RESET; + + *addr = (FPW) INTEL_WRSETUP; /* write setup */ + *addr = data; + + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* reset */ + return (1); + } + } + + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for ATMEL FLASH + * A word is 16 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data) +{ + ulong start; + int flag, i; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u16 *)dest) & data) != data) { + return (2); + } + + base = (FPWV *) (CFG_ATMEL_BASE); + + for (i = 0; i < sizeof(u16); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (u8) 0x00800080) != + (data & (u8) 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (u8) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + *dest++ = (u8) 0x00F000F0; /* reset bank */ + data >>= 8; + } + + return (res); +} + +void inline spin_wheel(void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + *addr = (FPW) INTEL_RESET; /* make sure in read mode */ + *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ + + if (prot) + *addr = (FPW) INTEL_PROTECT; /* lock sector */ + else + *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) INTEL_READID; + + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) INTEL_PROTECT; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) INTEL_PROTECT) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect(info); + break; + + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif +#endif diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c new file mode 100644 index 0000000..6a02782 --- /dev/null +++ b/board/freescale/m54455evb/m54455evb.c @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M54455 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + gpio->mscr_sdram = 0xAA; + + sdram->sdcs0 = (CFG_SDRAM_BASE | i); + sdram->sdcs1 = (CFG_SDRAM_BASE1 | i); + + sdram->sdcfg1 = CFG_SDRAM_CFG1; + sdram->sdcfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + sdram->sdmr = CFG_SDRAM_EMOD | 0x408; + sdram->sdmr = CFG_SDRAM_MODE | 0x300; + + udelay(500); + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Perform two refresh cycles */ + sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CFG_SDRAM_CTRL | 4; + + sdram->sdmr = CFG_SDRAM_MODE | 0x200; + + sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return (dramsize << 1); +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#if defined(CONFIG_CMD_IDE) +#include <ata.h> + +int ide_preinit(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10; + gpio->par_feci2c |= + (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | + GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); + gpio->par_ata |= + (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | + GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 + | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | + GPIO_PAR_ATA_IORDY_IORDY); + gpio->par_pci |= + (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); + + return (0); +} + +void ide_set_reset(int idereset) +{ + volatile atac_t *ata = (atac_t *) MMAP_ATA; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { + {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} + }; /* PIO 4 */ + + if (idereset) { + ata->cr = 0; /* control reset */ + udelay(10000); + } else { +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / gd->bus_clk; /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + ata->t1 = CALC_TIMING(piotms[2][0]); + ata->t2w = CALC_TIMING(piotms[2][1]); + ata->t2r = CALC_TIMING(piotms[2][1]); + ata->ta = CALC_TIMING(piotms[2][8]); + ata->trd = CALC_TIMING(piotms[2][7]); + ata->t4 = CALC_TIMING(piotms[2][3]); + ata->t9 = CALC_TIMING(piotms[2][6]); + + ata->cr = 0x40; /* IORDY enable */ + udelay(200000); + ata->cr |= 0x01; /* IORDY enable */ + } +} +#endif + +#if defined(CONFIG_PCI) +/* + * Initialize PCI devices, report devices found. + */ +static struct pci_controller hose; +extern void pci_mcf5445x_init(struct pci_controller *hose); + +void pci_init_board(void) +{ + pci_mcf5445x_init(&hose); +} +#endif /* CONFIG_PCI */ diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c new file mode 100644 index 0000000..c067183 --- /dev/null +++ b/board/freescale/m54455evb/mii.c @@ -0,0 +1,320 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + else + gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; + else + gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + struct eth_device *dev; + int i, miispd; + u16 rst = 0; + + dev = eth_get_dev(); + + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET); + for (i = 0; i < FEC_RESET_DELAY; ++i) { + udelay(500); + miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst); + if ((rst & PHY_BMCR_RESET) == 0) + break; + } + if (i == FEC_RESET_DELAY) + printf("Mii reset timeout %d\n", i); +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds new file mode 100644 index 0000000..bda68e4 --- /dev/null +++ b/board/freescale/m54455evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5445x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile index a987e510..a987e510 100644 --- a/board/mpc8313erdb/Makefile +++ b/board/freescale/mpc8313erdb/Makefile diff --git a/board/mpc8313erdb/config.mk b/board/freescale/mpc8313erdb/config.mk index f768264..f768264 100644 --- a/board/mpc8313erdb/config.mk +++ b/board/freescale/mpc8313erdb/config.mk diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 999fe9e..861c143 100644 --- a/board/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -23,7 +23,11 @@ */ #include <common.h> +#if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif #include <pci.h> #include <mpc83xx.h> @@ -96,21 +100,22 @@ void pci_init_board(void) mpc83xx_pci_init(1, reg, warmboot); } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p) { + if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 4b67788..e6e8410 100644 --- a/board/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -112,8 +112,6 @@ long int initdram(int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ msize = fixed_sdram(); @@ -127,7 +125,6 @@ long int initdram(int board_type) resume_from_sleep(); #endif - puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return msize; } diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 1886f19..e738613 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -17,7 +17,6 @@ #include <miiphy.h> #include <command.h> #include <libfdt.h> -#include <libfdt_env.h> #if defined(CONFIG_PCI) #include <pci.h> #endif @@ -92,8 +91,6 @@ long int initdram(int board_type) msize = fixed_sdram(); - puts("\n DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -185,33 +182,21 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) - -/* - * Prototypes of functions that we use. - */ -void ft_cpu_setup(void *blob, bd_t *bd); - -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif - -void -ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { - int nodeoffset; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/memory"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); } - +#endif ft_cpu_setup(blob, bd); - #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif } -#endif /* CONFIG_OF_BOARD_SETUP */ +#endif diff --git a/board/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile index 5ec7a87..5ec7a87 100644 --- a/board/mpc832xemds/Makefile +++ b/board/freescale/mpc832xemds/Makefile diff --git a/board/mpc832xemds/config.mk b/board/freescale/mpc832xemds/config.mk index 6c3eca7..6c3eca7 100644 --- a/board/mpc832xemds/config.mk +++ b/board/freescale/mpc832xemds/config.mk diff --git a/board/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 772da67..6ba25d4 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -29,6 +29,11 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" #endif const qe_iop_conf_t qe_iop_conf_tab[] = { @@ -86,6 +91,14 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + int fixed_sdram(void); long int initdram(int board_type) @@ -101,8 +114,6 @@ long int initdram(int board_type) msize = fixed_sdram(); - puts("\n DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -155,22 +166,22 @@ int checkboard(void) return 0; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index d0a407a..6bc35c7 100644 --- a/board/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -20,6 +20,8 @@ #include <i2c.h> #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif #include <asm/fsl_i2c.h> @@ -129,7 +131,6 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - u8 val8, orig_i2c_bus; u16 reg16; u32 val32; u32 dev; @@ -198,43 +199,6 @@ void pci_init_board(void) PIWAR_IWS_2G; /* - * Assign PIB PMC slot to desired PCI bus - */ - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - - val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - - /* * Release PCI RST Output signal */ udelay(2000); @@ -290,8 +254,6 @@ void pci_init_board(void) pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - printf("PCI 32bit bus on PMC2 & PMC3\n"); - /* * Hose scan. */ @@ -299,7 +261,27 @@ void pci_init_board(void) } #endif /* CONFIG_PCISLAVE */ -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { diff --git a/board/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile index 5ec7a87..5ec7a87 100644 --- a/board/mpc8349emds/Makefile +++ b/board/freescale/mpc8349emds/Makefile diff --git a/board/mpc8349emds/config.mk b/board/freescale/mpc8349emds/config.mk index edf64d1..edf64d1 100644 --- a/board/mpc8349emds/config.mk +++ b/board/freescale/mpc8349emds/config.mk diff --git a/board/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 521d1bb..39c0916 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -34,6 +34,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif int fixed_sdram(void); @@ -68,8 +70,6 @@ long int initdram (int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) @@ -88,7 +88,7 @@ long int initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -189,9 +189,6 @@ void sdram_init(void) volatile lbus83xx_t *lbc= &immap->lbus; uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ @@ -253,26 +250,25 @@ void sdram_init(void) #else void sdram_init(void) { - puts(" SDRAM on Local Bus is NOT available!\n"); } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index d6a12b8..ae94a2f 100644 --- a/board/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -25,6 +25,12 @@ #include <pci.h> #include <asm/mpc8349_pci.h> #include <i2c.h> +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + DECLARE_GLOBAL_DATA_PTR; @@ -382,7 +388,40 @@ pci_init_board(void) } -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { diff --git a/board/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile index 31bcdb8..31bcdb8 100644 --- a/board/mpc8349itx/Makefile +++ b/board/freescale/mpc8349itx/Makefile diff --git a/board/mpc8349itx/config.mk b/board/freescale/mpc8349itx/config.mk index 79f1765..79f1765 100644 --- a/board/mpc8349itx/config.mk +++ b/board/freescale/mpc8349itx/config.mk diff --git a/board/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 178b1d3..c82f784 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -39,6 +39,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif #ifndef CONFIG_SPD_EEPROM @@ -74,7 +76,7 @@ int fixed_sdram(void) im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ - im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; + im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; im->ddr.sdram_mode = (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); im->ddr.sdram_interval = @@ -160,7 +162,6 @@ long int initdram(int board_type) ddr_enable_ecc(msize * 1048576); #endif - puts(" DDR RAM: "); /* return total bus RAM size(bytes) */ return msize * 1024 * 1024; } @@ -385,22 +386,22 @@ int misc_init_r(void) return rc; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index e81ad27..5ca094d 100644 --- a/board/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -31,6 +31,8 @@ #include <i2c.h> #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -332,8 +334,40 @@ void pci_init_board(void) #endif } -#endif /* CONFIG_PCI */ -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { @@ -355,3 +389,4 @@ ft_pci_setup(void *blob, bd_t *bd) #endif } #endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile index 5ec7a87..5ec7a87 100644 --- a/board/mpc8360emds/Makefile +++ b/board/freescale/mpc8360emds/Makefile diff --git a/board/mpc8360emds/config.mk b/board/freescale/mpc8360emds/config.mk index 9ace886..9ace886 100644 --- a/board/mpc8360emds/config.mk +++ b/board/freescale/mpc8360emds/config.mk diff --git a/board/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 3fa093d..e050cd4 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -29,7 +29,9 @@ #include <ft_build.h> #elif defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#include <libfdt_env.h> +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" #endif const qe_iop_conf_t qe_iop_conf_tab[] = { @@ -107,6 +109,14 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -139,7 +149,7 @@ long int initdram(int board_type) * Initialize SDRAM if it is on local bus. */ sdram_init(); - puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -224,8 +234,6 @@ void sdram_init(void) volatile lbus83xx_t *lbc = &immap->lbus; uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - puts("\n SDRAM on Local Bus: "); - print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ @@ -281,36 +289,13 @@ void sdram_init(void) #else void sdram_init(void) { - puts("SDRAM on Local Bus is NOT available!\n"); } #endif -#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ - && defined(CONFIG_OF_BOARD_SETUP) - -/* - * Prototypes of functions that we use. - */ -void ft_cpu_setup(void *blob, bd_t *bd); - -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif - -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_LIBFDT) - int nodeoffset; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/memory"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); - } -#else +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; @@ -320,10 +305,9 @@ ft_board_setup(void *blob, bd_t *bd) *p = cpu_to_be32(bd->bi_memsize); } #endif - + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif - ft_cpu_setup(blob, bd); } -#endif /* CONFIG_OF_x */ +#endif diff --git a/board/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index 8f90471..cf7ef90 100644 --- a/board/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -22,7 +22,6 @@ #include <ft_build.h> #elif defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#include <libfdt_env.h> #endif #include <asm/fsl_i2c.h> @@ -132,7 +131,6 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - u8 val8, orig_i2c_bus; u16 reg16; u32 val32; u32 dev; @@ -201,43 +199,6 @@ void pci_init_board(void) PIWAR_IWS_2G; /* - * Assign PIB PMC slot to desired PCI bus - */ - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - - val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - - /* * Release PCI RST Output signal */ udelay(2000); @@ -293,8 +254,6 @@ void pci_init_board(void) pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n"); - /* * Hose scan. */ @@ -314,7 +273,12 @@ ft_pci_setup(void *blob, bd_t *bd) if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(hose[0].first_busno); tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); } } #elif defined(CONFIG_OF_FLAT_TREE) diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 308f707..006fdc9 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -24,14 +24,9 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ - ../common/pixis.o +COBJS := $(BOARD).o SOBJS := init.o diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index ea7d54d..68ccba7 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -218,7 +218,7 @@ law_entry: .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) @@ -226,18 +226,17 @@ law_entry: .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) - /* To keep to 10 LAWs, PCIE1_IO_PHYS must use top of mem region */ + .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) + /* contains both PCIE3 MEM & IO space */ .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_256M) - - .long (CFG_PCIE3_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) 4: entry_end diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 8ddbb01..76d9091 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/immap_85xx.h> #include <asm/immap_fsl_pci.h> +#include <asm/io.h> #include <spd.h> #include <miiphy.h> @@ -222,6 +223,11 @@ pci_init_board(void) printf (" PCIE3 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + */ + in_be32(CFG_PCIE3_MEM_BASE); } else { printf (" PCIE3: disabled\n"); } @@ -516,8 +522,16 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif #ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; @@ -525,7 +539,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif #ifdef CONFIG_PCIE2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; @@ -533,19 +547,12 @@ ft_board_setup(void *blob, bd_t *bd) } #endif #ifdef CONFIG_PCIE3 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;; debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]); } #endif - ft_cpu_setup(blob, bd); - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } } #endif diff --git a/board/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile index df56b31..201da3e 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -23,14 +23,9 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../freescale/common) -endif - LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o sys_eeprom.o \ - ../freescale/common/pixis.o +COBJS := $(BOARD).o SOBJS := init.o diff --git a/board/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk index f778dcb..f778dcb 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/freescale/mpc8641hpcn/config.mk diff --git a/board/mpc8641hpcn/init.S b/board/freescale/mpc8641hpcn/init.S index cb21ba6..cb21ba6 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/freescale/mpc8641hpcn/init.S diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 1bfbe88..931be9f 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -33,7 +33,7 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #endif -#include "../freescale/common/pixis.h" +#include "../common/pixis.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -338,6 +338,22 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci2_hose.last_busno - pci2_hose.first_busno; + debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif } #endif diff --git a/board/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds index 5864464..fd16362 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/freescale/mpc8641hpcn/u-boot.lds @@ -51,7 +51,7 @@ SECTIONS .text : { cpu/mpc86xx/start.o (.text) - board/mpc8641hpcn/init.o (.bootpg) + board/freescale/mpc8641hpcn/init.o (.bootpg) cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/cpu_init.o (.text) diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index c027f6f..07ba245 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -28,10 +28,7 @@ #include <mpc5xxx.h> #include <pci.h> #include <asm/processor.h> - -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif +#include <libfdt.h> #if defined(CONFIG_LITE5200B) #include "mt46v32m16.h" @@ -386,7 +383,7 @@ void ide_set_reset (int idereset) } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/idmr/Makefile b/board/idmr/Makefile index cf07cf4..be704b7 100644 --- a/board/idmr/Makefile +++ b/board/idmr/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c index 58cdba1..081c375 100644 --- a/board/idmr/idmr.c +++ b/board/idmr/idmr.c @@ -22,8 +22,7 @@ */ #include <common.h> -#include <asm/m5271.h> -#include <asm/immap_5271.h> +#include <asm/immap.h> int checkboard (void) { puts ("Board: iDMR\n"); diff --git a/board/idmr/mii.c b/board/idmr/mii.c new file mode 100644 index 0000000..f6c63c3 --- /dev/null +++ b/board/idmr/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index b227487..efdc333 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -28,11 +28,7 @@ #include <mpc5xxx.h> #include <pci.h> #include <asm/processor.h> - -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif - +#include <libfdt.h> #define SDRAM_DDR 0 #if 1 @@ -308,7 +304,7 @@ void ide_set_reset (int idereset) } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile index 06ef7f9..2a93571 100644 --- a/board/lwmon5/Makefile +++ b/board/lwmon5/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o sdram.o +COBJS = $(BOARD).o kbd.o sdram.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c new file mode 100644 index 0000000..1e5349a --- /dev/null +++ b/board/lwmon5/kbd.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2001, 2002 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include <common.h> +#include <i2c.h> +#include <command.h> +#include <post.h> +#include <serial.h> +#include <malloc.h> + +#include <linux/types.h> +#include <linux/string.h> /* for strdup */ + +DECLARE_GLOBAL_DATA_PTR; + +static void kbd_init (void); +static int compare_magic (uchar *kbd_data, uchar *str); + +/*--------------------- Local macros and constants --------------------*/ +#define _NOT_USED_ 0xFFFFFFFF + +/*------------------------- Keyboard controller -----------------------*/ +/* command codes */ +#define KEYBD_CMD_READ_KEYS 0x01 +#define KEYBD_CMD_READ_VERSION 0x02 +#define KEYBD_CMD_READ_STATUS 0x03 +#define KEYBD_CMD_RESET_ERRORS 0x10 + +/* status codes */ +#define KEYBD_STATUS_MASK 0x3F +#define KEYBD_STATUS_H_RESET 0x20 +#define KEYBD_STATUS_BROWNOUT 0x10 +#define KEYBD_STATUS_WD_RESET 0x08 +#define KEYBD_STATUS_OVERLOAD 0x04 +#define KEYBD_STATUS_ILLEGAL_WR 0x02 +#define KEYBD_STATUS_ILLEGAL_RD 0x01 + +/* Number of bytes returned from Keyboard Controller */ +#define KEYBD_VERSIONLEN 2 /* version information */ + +/* + * This is different from the "old" lwmon dsPIC kbd controller + * implementation. Now the controller still answers with 9 bytes, + * but the last 3 bytes are always "0x06 0x07 0x08". So we just + * set the length to compare to 6 instead of 9. + */ +#define KEYBD_DATALEN 6 /* normal key scan data */ + +/* maximum number of "magic" key codes that can be assigned */ + +static uchar kbd_addr = CFG_I2C_KEYBD_ADDR; + +static uchar *key_match (uchar *); + +#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ + +/*********************************************************************** +F* Function: int board_postclk_init (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: This function is the board_postclk_init() method implementation +Z* for the lwmon board. + * + ***********************************************************************/ +int board_postclk_init (void) +{ + kbd_init(); + + return (0); +} + +static void kbd_init (void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar tmp_data[KEYBD_DATALEN]; + uchar val, errcd; + int i; + + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + gd->kbd_status = 0; + + /* Forced by PIC. Delays <= 175us loose */ + udelay(1000); + + /* Read initial keyboard error code */ + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &errcd, 1); + /* clear unused bits */ + errcd &= KEYBD_STATUS_MASK; + /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ + errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); + if (errcd) { + gd->kbd_status |= errcd << 8; + } + /* Reset error code and verify */ + val = KEYBD_CMD_RESET_ERRORS; + i2c_write (kbd_addr, 0, 0, &val, 1); + udelay(1000); /* delay NEEDED by keyboard PIC !!! */ + + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &val, 1); + + val &= KEYBD_STATUS_MASK; /* clear unused bits */ + if (val) { /* permanent error, report it */ + gd->kbd_status |= val; + return; + } + + /* + * Read current keyboard state. + * + * After the error reset it may take some time before the + * keyboard PIC picks up a valid keyboard scan - the total + * scan time is approx. 1.6 ms (information by Martin Rajek, + * 28 Sep 2002). We read a couple of times for the keyboard + * to stabilize, using a big enough delay. + * 10 times should be enough. If the data is still changing, + * we use what we get :-( + */ + + memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ + for (i=0; i<10; ++i) { + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { + /* consistent state, done */ + break; + } + /* remeber last state, delay, and retry */ + memcpy (tmp_data, kbd_data, KEYBD_DATALEN); + udelay (5000); + } +} + +/*********************************************************************** +F* Function: int misc_init_r (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned, even in the case of a keyboard +P* error. + * +Z* Intention: This function is the misc_init_r() method implementation +Z* for the lwmon board. +Z* The keyboard controller is initialized and the result +Z* of a read copied to the environment variable "keybd". +Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for +Z* this key, and if found display to the LCD will be enabled. +Z* The keys in "keybd" are checked against the magic +Z* keycommands defined in the environment. +Z* See also key_match(). + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int misc_init_r_kbd (void) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar kbd_init_status = gd->kbd_status >> 8; + uchar kbd_status = gd->kbd_status; + uchar val; + char *str; + int i; + + if (kbd_init_status) { + printf ("KEYBD: Error %02X\n", kbd_init_status); + } + if (kbd_status) { /* permanent error, report it */ + printf ("*** Keyboard error code %02X ***\n", kbd_status); + sprintf (keybd_env, "%02X", kbd_status); + setenv ("keybd", keybd_env); + return 0; + } + + /* + * Now we know that we have a working keyboard, so disable + * all output to the LCD except when a key press is detected. + */ + + if ((console_assign (stdout, "serial") < 0) || + (console_assign (stderr, "serial") < 0)) { + printf ("Can't assign serial port as output device\n"); + } + + /* Read Version */ + val = KEYBD_CMD_READ_VERSION; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); + printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); + + /* Read current keyboard state */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + } + setenv ("keybd", keybd_env); + + str = strdup ((char *)key_match (kbd_data)); /* decode keys */ +#ifdef KEYBD_SET_DEBUGMODE + if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ + if ((console_assign (stdout, "lcd") < 0) || + (console_assign (stderr, "lcd") < 0)) { + printf ("Can't assign LCD display as output device\n"); + } + } +#endif /* KEYBD_SET_DEBUGMODE */ +#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + setenv ("preboot", str); /* set or delete definition */ +#endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } + return (0); +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +static int compare_magic (uchar *kbd_data, uchar *str) +{ + uchar compare[KEYBD_DATALEN-1]; + char *nxt; + int i; + + /* Don't include modifier byte */ + memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); + + for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { + uchar c; + int k; + + c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); + + if (str == (uchar *)nxt) { /* invalid character */ + break; + } + + /* + * Check if this key matches the input. + * Set matches to zero, so they match only once + * and we can find duplicates or extra keys + */ + for (k = 0; k < sizeof(compare); ++k) { + if (compare[k] == '\0') /* only non-zero entries */ + continue; + if (c == compare[k]) { /* found matching key */ + compare[k] = '\0'; + break; + } + } + if (k == sizeof(compare)) { + return -1; /* unmatched key */ + } + } + + /* + * A full match leaves no keys in the `compare' array, + */ + for (i = 0; i < sizeof(compare); ++i) { + if (compare[i]) + { + return -1; + } + } + + return 0; +} + +/*********************************************************************** +F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* + * +P* Parameters: uchar *kbd_data +P* - The keys to match against our magic definitions +P* +P* Returnvalue: uchar * +P* - != NULL: Pointer to the corresponding command(s) +P* NULL: No magic is about to happen + * +Z* Intention: Check if pressed key(s) match magic sequence, +Z* and return the command string associated with that key(s). +Z* +Z* If no key press was decoded, NULL is returned. +Z* +Z* Note: the first character of the argument will be +Z* overwritten with the "magic charcter code" of the +Z* decoded key(s), or '\0'. +Z* +Z* Note: the string points to static environment data +Z* and must be saved before you call any function that +Z* modifies the environment. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +static uchar *key_match (uchar *kbd_data) +{ + char magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); + debug ("### Check magic \"%s\"\n", magic); + if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + + cmd = getenv (cmd_name); + debug ("### Set PREBOOT to $(%s): \"%s\"\n", + cmd_name, cmd ? cmd : "<<NULL>>"); + *kbd_data = *suffix; + return ((uchar *)cmd); + } + } + debug ("### Delete PREBOOT\n"); + *kbd_data = '\0'; + return (NULL); +} +#endif /* CONFIG_PREBOOT */ + +/*********************************************************************** +F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, +F* int argc, char *argv[]) P*A*Z* + * +P* Parameters: cmd_tbl_t *cmdtp +P* - Pointer to our command table entry +P* int flag +P* - If the CMD_FLAG_REPEAT bit is set, then this call is +P* a repetition +P* int argc +P* - Argument count +P* char *argv[] +P* - Array of the actual arguments +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: Implement the "kbd" command. +Z* The keyboard status is read. The result is printed on +Z* the console and written into the "keybd" environment +Z* variable. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar val; + int i; + +#if 0 /* Done in kbd_init */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); +#endif + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + puts ("Keys:"); + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + printf (" %02x", kbd_data[i]); + } + putc ('\n'); + setenv ("keybd", keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL +); + +/*----------------------------- Utilities -----------------------------*/ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar val; + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); +} +#endif diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 830ec19..77f9989 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -19,6 +19,7 @@ */ #include <common.h> +#include <command.h> #include <ppc440.h> #include <asm/processor.h> #include <asm/gpio.h> @@ -28,7 +29,8 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -ulong flash_get_size (ulong base, int banknum); +ulong flash_get_size(ulong base, int banknum); +int misc_init_r_kbd(void); int board_early_init_f(void) { @@ -295,6 +297,11 @@ int misc_init_r(void) out_be32((void *)0xc4000024, 0x64); out_be32((void *)0xc4000020, 0x701); + /* + * Init matrix keyboard + */ + misc_init_r_kbd(); + return 0; } @@ -522,13 +529,28 @@ void hw_watchdog_reset(void) gpio_write_bit(CFG_GPIO_WATCHDOG, val); } -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) +int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - return (ctrlc()); + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((strcmp(argv[1], "on") == 0)) { + gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1); + } else if ((strcmp(argv[1], "off") == 0)) { + gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0); + } else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + + return 0; } -#endif + +U_BOOT_CMD( + eepromwp, 2, 0, do_eeprom_wp, + "eepromwp- eeprom write protect off/on\n", + "<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n" +); diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index f906b85..d4547e2 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -57,7 +57,6 @@ void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); -#ifdef CONFIG_ADD_RAM_INFO static u32 is_ecc_enabled(void) { u32 val; @@ -87,7 +86,6 @@ void board_add_ram_info(int use_default) val = DDR0_03_CASLAT_DECODE(val); printf(", CL%d)", val); } -#endif static int wait_for_dlllock(void) { diff --git a/board/m5271evb/Makefile b/board/m5271evb/Makefile index 424ab1c..2ec71ee 100644 --- a/board/m5271evb/Makefile +++ b/board/m5271evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c index c26c91d..9caad63 100644 --- a/board/m5271evb/m5271evb.c +++ b/board/m5271evb/m5271evb.c @@ -22,8 +22,7 @@ */ #include <common.h> -#include <asm/m5271.h> -#include <asm/immap_5271.h> +#include <asm/immap.h> int checkboard (void) { puts ("Board: Freescale M5271EVB\n"); diff --git a/board/m5271evb/mii.c b/board/m5271evb/mii.c new file mode 100644 index 0000000..f6c63c3 --- /dev/null +++ b/board/m5271evb/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5272c3/Makefile b/board/m5272c3/Makefile index cf07cf4..be704b7 100644 --- a/board/m5272c3/Makefile +++ b/board/m5272c3/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c index 0dfeaf2..6dcda4f 100644 --- a/board/m5272c3/m5272c3.c +++ b/board/m5272c3/m5272c3.c @@ -22,18 +22,17 @@ */ #include <common.h> -#include <asm/m5272.h> -#include <asm/immap_5272.h> +#include <asm/immap.h> int checkboard (void) { puts ("Board: "); - puts("MOTOROLA MCF5272C3 EVB\n"); + puts ("Freescale MCF5272C3 EVB\n"); return 0; }; long int initdram (int board_type) { - volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR); + volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); sdp->sdram_sdtr = 0xf539; sdp->sdram_sdcr = 0x4211; diff --git a/board/m5272c3/mii.c b/board/m5272c3/mii.c new file mode 100644 index 0000000..fadcbb3 --- /dev/null +++ b/board/m5272c3/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5282evb/Makefile b/board/m5282evb/Makefile index cf07cf4..2ec71ee 100644 --- a/board/m5282evb/Makefile +++ b/board/m5282evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5282evb/config.mk b/board/m5282evb/config.mk index 8484307..0aa2361 100644 --- a/board/m5282evb/config.mk +++ b/board/m5282evb/config.mk @@ -22,4 +22,4 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x20000 +TEXT_BASE = 0xFFE00000 diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c deleted file mode 100644 index 36a7c31..0000000 --- a/board/m5282evb/flash.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_PL160CB & FLASH_TYPEMASK): - printf ("AM29PL160CB (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_PL160CB & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 32 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 34)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x10000 + 0x10000 * (j - - 4); - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0xffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c index a08af68..243d6a4 100644 --- a/board/m5282evb/m5282evb.c +++ b/board/m5282evb/m5282evb.c @@ -22,14 +22,71 @@ */ #include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; int checkboard (void) { - puts ("MOTOROLA M5272EVB Evaluation Board\n"); + puts ("Board: Freescale M5282EVB Evaluation Board\n"); return 0; } long int initdram (int board_type) { - return 0x1000000; + u32 dramsize, i, dramclk; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) + { + dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + + /* Initialize DRAM Control Register: DCR */ + MCFSDRAMC_DCR = (0 + | MCFSDRAMC_DCR_RTIM_6 + | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); + + /* Initialize DACR0 */ + MCFSDRAMC_DACR0 = (0 + | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_32); + + /* Initialize DMR0 */ + MCFSDRAMC_DMR0 = (0 + | ((dramsize - 1) & 0xFFFC0000) + | MCFSDRAMC_DMR_V); + + /* Set IP (bit 3) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm ("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 2000; i++) { + asm(" nop"); + } + + /* Finish the configuration by issuing the IMRS. */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; + + /* Write to the SDRAM Mode Register */ + *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + } } diff --git a/board/m5282evb/mii.c b/board/m5282evb/mii.c new file mode 100644 index 0000000..ebd3ed9 --- /dev/null +++ b/board/m5282evb/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CFG_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 6eb5fe9..f83998e 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -29,9 +29,7 @@ #include <common.h> #include <mpc5xxx.h> #include <miiphy.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif +#include <libfdt.h> #if defined(CONFIG_STATUS_LED) #include <status_led.h> @@ -196,12 +194,12 @@ int checkboard(void) } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); } -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ #if defined(CONFIG_STATUS_LED) diff --git a/board/netstal/common/flash.c b/board/netstal/common/hcu_flash.c index be2cb37..be2cb37 100644 --- a/board/netstal/common/flash.c +++ b/board/netstal/common/hcu_flash.c diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile index d9825a5..af90821 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/netstal/hcu4/Makefile @@ -22,16 +22,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath flash.c ../common -COBJS = $(BOARD).o flash.o +vpath hcu_flash.c ../common + +# NOBJS : Netstal common objects +NOBJS = hcu_flash.o +COBJS = $(BOARD).o SOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj),$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 2b95604..48a3f13 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -43,7 +43,7 @@ enum { HW_GENERATION_MCU25 = 0x09, }; -void sysLedSet(u32 value); +void hcu_led_set(u32 value); long int spd_sdram(int(read_spd)(uint addr)); #ifdef CONFIG_SPD_EEPROM @@ -121,22 +121,24 @@ int checkboard (void) printf ("HCU3: index %d\n\n", index); else if (generation == HW_GENERATION_HCU4) printf ("HCU4: index %d\n\n", index); - /* GPIO here noch nicht richtig initialisert !!! */ - sysLedSet(0); + hcu_led_set(0); for (j = 0; j < 7; j++) { - sysLedSet(1 << j); + hcu_led_set(1 << j); udelay(50 * 1000); } return 0; } -u32 sysLedGet(void) +u32 hcu_led_get(void) { return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff; } -void sysLedSet(u32 value /* value to place in LEDs */) +/*---------------------------------------------------------------------------+ + * hcu_led_set value to be placed into the LEDs (max 6 bit) + *---------------------------------------------------------------------------*/ +void hcu_led_set(u32 value) { u32 tmp = ~value; u32 *ledReg; @@ -243,9 +245,9 @@ long int fixed_hcu4_sdram (int board_type) } /*---------------------------------------------------------------------------+ - * getSerialNr + * hcu_serial_number *---------------------------------------------------------------------------*/ -static u32 getSerialNr(void) +static u32 hcu_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; @@ -265,7 +267,7 @@ int misc_init_r(void) char *s = getenv("ethaddr"); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = hcu_serial_number(); for (i = 0; i < 6; ++i) { gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index eee310b..27398b9 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -22,16 +22,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath flash.c ../common -COBJS = $(BOARD).o sdram.o flash.o +vpath hcu_flash.c ../common + +# NOBJS : Netstal common objects +NOBJS = hcu_flash.o +COBJS = $(BOARD).o sdram.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj),$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 23df081..b9b10fd 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -22,10 +22,11 @@ #include <asm/processor.h> #include <ppc440.h> #include <asm/mmu.h> +#include <net.h> DECLARE_GLOBAL_DATA_PTR; -void sysLedSet(u32 value); +void hcu_led_set(u32 value); extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; @@ -41,7 +42,8 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define SDR0_ECID2 0x0082 #define SDR0_ECID3 0x0083 -#define SYS_IO_ADDRESS 0xcce00000 +#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) +#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000) #define DEFAULT_ETH_ADDR "ethaddr" /* ethaddr for first or etha1ddr for second ethernet */ @@ -182,11 +184,14 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_BOARD_PRE_INIT int board_pre_init(void) { return board_early_init_f(); } +#endif + int checkboard(void) { unsigned int j; @@ -211,38 +216,51 @@ int checkboard(void) printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); for (j = 0;j < 6; j++) { - sysLedSet(1 << j); + hcu_led_set(1 << j); udelay(200 * 1000); } return 0; } -u32 sysLedGet(void) +u32 hcu_led_get(void) { return in16(SYS_IO_ADDRESS) & 0x3f; } -void sysLedSet(u32 value /* value to place in LEDs */) +/*---------------------------------------------------------------------------+ + * hcu_led_set value to be placed into the LEDs (max 6 bit) + *---------------------------------------------------------------------------*/ +void hcu_led_set(u32 value) { out16(SYS_IO_ADDRESS, value); } /*---------------------------------------------------------------------------+ - * getSerialNr + * get_serial_number *---------------------------------------------------------------------------*/ -static u32 getSerialNr(void) +static u32 get_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; if (*serial == 0xffffffff) - return get_ticks(); + return 0; return *serial; } /*---------------------------------------------------------------------------+ + * hcu_get_slot + *---------------------------------------------------------------------------*/ +u32 hcu_get_slot(void) +{ + u16 *slot = (u16 *)SYS_SLOT_ADDRESS; + return (*slot) & 0x7f; +} + + +/*---------------------------------------------------------------------------+ * misc_init_r. *---------------------------------------------------------------------------*/ int misc_init_r(void) @@ -250,7 +268,7 @@ int misc_init_r(void) char *s = getenv(DEFAULT_ETH_ADDR); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = get_serial_number(); unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; @@ -272,8 +290,7 @@ int misc_init_r(void) gd->bd->bi_enetaddr[2] = 0x13; gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; - /* byte[5].bit 0 must be zero */ - gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + gd->bd->bi_enetaddr[5] = hcu_get_slot(); sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], @@ -283,6 +300,25 @@ int misc_init_r(void) setenv(DEFAULT_ETH_ADDR, ethaddr); } + /* IP-Adress update */ + { + IPaddr_t ipaddr; + char *ipstring; + + ipstring = getenv("ipaddr"); + if (ipstring == 0) + ipaddr = string_to_ip("172.25.1.99"); + else + ipaddr = string_to_ip(ipstring); + if ((ipaddr & 0xff) != (32 + hcu_get_slot())) { + char tmp[22]; + + ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot(); + ip_to_string (ipaddr, tmp); + printf("%s: enforce %s\n", __FUNCTION__, tmp); + setenv("ipaddr", tmp); + } + } #ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, @@ -346,6 +382,7 @@ int misc_init_r(void) return 0; } +#if defined(CONFIG_PCI) /************************************************************************* * pci_pre_init * @@ -358,7 +395,6 @@ int misc_init_r(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -411,7 +447,6 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init @@ -421,7 +456,6 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*-------------------------------------------------------------+ @@ -478,13 +512,11 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -499,8 +531,6 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif -/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host @@ -517,9 +547,8 @@ void pci_master_init(struct pci_controller *hose) * * ************************************************************************/ -#if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) */ diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 4039195..9ee9ab5 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -36,7 +36,7 @@ #include <asm/mmu.h> #include <ppc440.h> -void sysLedSet(u32 value); +void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); @@ -70,7 +70,6 @@ void dflush(void); void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); -#ifdef CONFIG_ADD_RAM_INFO void board_add_ram_info(int use_default) { PPC440_SYS_INFO board_cfg; @@ -99,7 +98,6 @@ void board_add_ram_info(int use_default) val = DDR0_03_CASLAT_DECODE(val); printf(", CL%d)", val); } -#endif /*-------------------------------------------------------------------- * wait_for_dlllock. @@ -138,7 +136,7 @@ static int wait_for_dlllock(void) void sdram_panic(const char *reason) { printf("\n%s: reason %s", __FUNCTION__, reason); - sysLedSet(0xff); + hcu_led_set(0xff); while (1) { } /* Never return */ @@ -197,6 +195,13 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes, mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + /* + * Clear possible errors + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + mtspr(mcsr, mfspr(mcsr)); + /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | @@ -244,7 +249,6 @@ long int initdram (int board_type) sdram_panic(INVALID_HW_CONFIG); break; } - dram_size -= 16 * 1024 * 1024; mtsdram(DDR0_07, 0x00090100); /* * TCPD=200 cycles of clock input is required to lock the DLL. @@ -283,6 +287,7 @@ long int initdram (int board_type) /* * Program tlb entries for this size (dynamic) */ + remove_tlb(CFG_SDRAM_BASE, 256 << 20); program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); /* @@ -291,6 +296,8 @@ long int initdram (int board_type) */ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + /* Diminish RAM to initialize */ + dram_size = dram_size - 32 ; #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. diff --git a/board/omap2420h4/flash.c b/board/omap2420h4/flash.c deleted file mode 100644 index d5e106a..0000000 --- a/board/omap2420h4/flash.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/sizes.h> -#include <linux/byteorder/swab.h> - -#define PHYS_FLASH_SECT_SIZE SZ_128K -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -# define FLASH_PORT_WIDTH ushort -# define FLASH_PORT_WIDTHV vu_short -# define SWAP(x) __swab16(x) -#else -# define FLASH_PORT_WIDTH ulong -# define FLASH_PORT_WIDTHV vu_long -# define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, SZ_32K}, /* 4 * 32kBytes sectors */ - {255, SZ_128K}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -void flash_unlock(flash_info_t * info, int bank); -int flash_probe(void); - -/*----------------------------------------------------------------------- - */ - -/* see if flash is ok */ -int flash_probe(void) -{ - return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0])); -} - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i],i); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i],i); - break; - - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - -#ifdef CFG_ENV_IS_IN_FLASH - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_unlock(flash_info_t * info, int bank) -{ - int j; - if (!bank) - j=2; /* leave 0,1 locked for boot bank */ - else - j=0; /* get the whole bank for #2 */ - - for (;j<CFG_MAX_FLASH_SECT;j++) { - FPWV *addr = (FPWV *) (info->start[j]); - if (addr == NULL) { - printf("Warning Flash probe failed\n"); - break; - } - flash_unprotect_sectors (addr); - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - } -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - volatile int r; /* gcc 3.4.0-1 strangeness, need to follow up.*/ - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 254) { /* 255,256,257,258 */ - r=i; - info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE)); - info->protect[i] = 0; - } else { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - /* mb(); this one makes ARM11 err go away, but I want it :) as a guide to problems */ - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0] & 0xFF; /* just looking for 89 (8989 is hw pat)*/ - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return(0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): /* 880D */ - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; /*0-258*/ - info->size = SZ_32M; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return(info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start, last; - int rcode = 0; -#ifdef CONFIG_USE_IRQ - int iflag; -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - -#ifdef CONFIG_USE_IRQ - /* Disable interrupts which might cause a timeout here */ - iflag = disable_interrupts (); -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } -#ifdef CONFIG_USE_IRQ - if (iflag) - enable_interrupts(); -#endif - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return(rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return(rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return(0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return(write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; -#ifdef CONFIG_USE_IRQ - int iflag; -#endif - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return(2); - } - /* Disable interrupts which might cause a timeout here */ -#ifdef CONFIG_USE_IRQ - iflag = disable_interrupts (); -#endif - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return(1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - -#ifdef CONFIG_USE_IRQ - if (iflag) - enable_interrupts(); -#endif - - return(0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index e247fee..90e99d3 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -30,6 +30,7 @@ #include <spd_sdram.h> #include <status_led.h> #include <sha1.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -867,6 +868,29 @@ U_BOOT_CMD( ); #endif +#if defined (CONFIG_CMD_IDE) +/* These addresses need to be shifted one place to the left + * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) + * These values are shifted + */ +extern ulong *ide_bus_offset; +void inline ide_outb(int dev, int port, unsigned char val) +{ + debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", + dev, port, val, (ATA_CURR_BASE(dev)+port)); + + out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val); +} +unsigned char inline ide_inb(int dev, int port) +{ + uchar val; + val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1))); + debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", + dev, port, (ATA_CURR_BASE(dev)+port), val); + return (val); +} +#endif + #ifdef CONFIG_IDE_PREINIT int ide_preinit (void) { diff --git a/board/r5200/Makefile b/board/r5200/Makefile index 424ab1c..2ec71ee 100644 --- a/board/r5200/Makefile +++ b/board/r5200/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/r5200/mii.c b/board/r5200/mii.c new file mode 100644 index 0000000..706c90f --- /dev/null +++ b/board/r5200/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 4cd447e..86166ea 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -64,8 +64,6 @@ long int initdram (int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) @@ -84,7 +82,6 @@ long int initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -130,7 +127,7 @@ int fixed_sdram(void) #if defined(CONFIG_DDR_2T_TIMING) | SDRAM_CFG_2T_EN #endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; + | SDRAM_CFG_SDRAM_TYPE_DDR1; #if defined (CONFIG_DDR_32BIT) /* for 32-bit mode burst length is 8 */ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 51f4aeb..21f67aa 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -31,10 +31,7 @@ #include <mpc5xxx.h> #include <pci.h> #include <asm/processor.h> - -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif +#include <libfdt.h> #ifdef CONFIG_VIDEO_SM501 #include <sm501.h> @@ -780,9 +777,9 @@ int board_get_height (void) #endif /* CONFIG_VIDEO_SM501 */ -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); } -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index 9c35e22..7d0b055 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -114,7 +114,7 @@ long int initdram (int board_type) /* enable DDR controller */ im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR); + SDRAM_CFG_SDRAM_TYPE_DDR1); SYNC; /* size detection */ @@ -388,7 +388,7 @@ static void set_ddr_config(void) { /* don't enable DDR controller yet */ im->ddr.sdram_cfg = SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR; + SDRAM_CFG_SDRAM_TYPE_DDR1; SYNC; /* Set SDRAM mode */ diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile new file mode 100644 index 0000000..115e17d --- /dev/null +++ b/board/trizepsiv/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := conxs.o eeprom.o +SOBJS := lowlevel_init.o pxavoltage.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk new file mode 100644 index 0000000..4486f6b --- /dev/null +++ b/board/trizepsiv/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f00000 +# 0xa1700000 +#TEXT_BASE = 0 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c new file mode 100644 index 0000000..7c6c855 --- /dev/null +++ b/board/trizepsiv/conxs.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/pxa-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ + +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +void usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(RH_A_NPS); + UHCRHDA |= RH_A_PSM; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + puts("Called USB STOP\n"); + return; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ConXS Board */ + gd->bd->bi_arch_number = 776; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_SERIAL_MULTI) + char *console=getenv("boot_console"); + + if ((strcmp(console,"serial_btuart") == 0) || + (strcmp(console,"serial_stuart") == 0) || + (strcmp(console,"serial_ffuart") == 0)) { + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); + } else { + setenv("stdout", "serial"); + setenv("stdin", "serial"); + setenv("stderr", "serial"); + } +#endif + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c new file mode 100644 index 0000000..3d3bc00 --- /dev/null +++ b/board/trizepsiv/eeprom.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +static unsigned char srom[128]; +extern u16 read_srom_word(int); +extern void write_srom_word(int offset, u16 val); + +static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int i; + + for (i=0; i < 0x40; i++) { + if (!(i % 0x10)) + printf("\n%08lx:", i); + printf(" %04x", read_srom_word(i)); + } + printf ("\n"); + return (0); +} + +static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int offset,value; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset=simple_strtoul(argv[2],NULL,16); + value=simple_strtoul(argv[3],NULL,16); + if (offset > 0x40) { + printf("Wrong offset : 0x%x\n",offset); + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + write_srom_word(offset, value); + return (0); +} + +int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp (argv[1],"read") == 0) { + return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else if (strcmp (argv[1],"write") == 0) { + return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + dm9000ee,4,1,do_dm9000_eeprom, + "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", + "\ndm9000ee write <word offset> <value> \n" + "\tdm9000ee read \n" + "\tword:\t\t00-02 : MAC Address\n" + "\t\t\t03-07 : DM9000 Configuration\n" + "\t\t\t08-63 : User data\n"); diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S new file mode 100644 index 0000000..d886938 --- /dev/null +++ b/board/trizepsiv/lowlevel_init.S @@ -0,0 +1,503 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GRER3 + ldr r1, =CFG_GRER3_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GFER3 + ldr r1, =CFG_GFER3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +#if 1 + b initirqs +#endif + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S new file mode 100644 index 0000000..9659c2b --- /dev/null +++ b/board/trizepsiv/pxavoltage.S @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/pxa-regs.h> + + .global initPXAvoltage + +initPXAvoltage: + mov pc, lr diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/trizepsiv/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index ccb826b..ef15a00 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -207,6 +207,71 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } +#elif defined(CONFIG_M68K) /* M68K */ +static void print_str(const char *, const char *); + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + bd_t *bd = gd->bd; + char buf[32]; + + print_num ("memstart", (ulong)bd->bi_memstart); + print_num ("memsize", (ulong)bd->bi_memsize); + print_num ("flashstart", (ulong)bd->bi_flashstart); + print_num ("flashsize", (ulong)bd->bi_flashsize); + print_num ("flashoffset", (ulong)bd->bi_flashoffset); +#if defined(CFG_INIT_RAM_ADDR) + print_num ("sramstart", (ulong)bd->bi_sramstart); + print_num ("sramsize", (ulong)bd->bi_sramsize); +#endif +#if defined(CFG_MBAR) + print_num ("mbar", bd->bi_mbar_base); +#endif + print_str ("busfreq", strmhz(buf, bd->bi_busfreq)); +#ifdef CONFIG_PCI + print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq)); +#endif +#ifdef CONFIG_EXTRA_CLOCK + print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq)); + print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); + print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq)); +#endif +#if defined(CONFIG_CMD_NET) + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + +#if defined(CONFIG_HAS_ETH1) + puts ("\neth1addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]); + } +#endif + +#if defined(CONFIG_HAS_ETH2) + puts ("\neth2addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]); + } +#endif + +#if defined(CONFIG_HAS_ETH3) + puts ("\neth3addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]); + } +#endif + + puts ("\nip_addr = "); + print_IPaddr (bd->bi_ip_addr); +#endif + printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + #else /* ! PPC, which leaves MIPS */ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -270,7 +335,7 @@ static void print_num(const char *name, ulong value) printf ("%-12s= 0x%08lX\n", name, value); } -#ifdef CONFIG_PPC +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) static void print_str(const char *name, const char *str) { printf ("%-12s= %6s MHz\n", name, str); diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index df1d038..6ebedfb 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -817,27 +817,34 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int i; /* skip kernel length, initrd length, and terminator */ - of_data = (ulong)(&len_ptr[3]); + of_flat_tree = (char *)(&len_ptr[3]); /* skip any additional image length fields */ for (i=2; len_ptr[i]; ++i) - of_data += 4; + of_flat_tree += 4; /* add kernel length, and align */ - of_data += ntohl(len_ptr[0]); + of_flat_tree += ntohl(len_ptr[0]); if (tail) { - of_data += 4 - tail; + of_flat_tree += 4 - tail; } /* add initrd length, and align */ tail = ntohl(len_ptr[1]) % 4; - of_data += ntohl(len_ptr[1]); + of_flat_tree += ntohl(len_ptr[1]); if (tail) { - of_data += 4 - tail; + of_flat_tree += 4 - tail; } +#ifndef CFG_NO_FLASH + /* move the blob if it is in flash (set of_data to !null) */ + if (addr2info ((ulong)of_flat_tree) != NULL) + of_data = (ulong)of_flat_tree; +#endif + + #if defined(CONFIG_OF_FLAT_TREE) - if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { + if (*((ulong *)(of_flat_tree)) != OF_DT_HEADER) { #else - if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) { + if (fdt_check_header (of_flat_tree) != 0) { #endif puts ("ERROR: image is not a fdt - " "must RESET the board to recover.\n"); @@ -845,9 +852,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #if defined(CONFIG_OF_FLAT_TREE) - if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) { + if (((struct boot_param_header *)of_flat_tree)->totalsize != + ntohl (len_ptr[2])) { #else - if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) { + if (be32_to_cpu (fdt_totalsize (of_flat_tree)) != + ntohl(len_ptr[2])) { #endif puts ("ERROR: fdt size != image size - " "must RESET the board to recover.\n"); @@ -932,7 +941,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, * so we flag it to be copied if it is not. */ if (of_flat_tree >= (char *)CFG_BOOTMAPSZ) - of_data = of_flat_tree; + of_data = (ulong)of_flat_tree; #endif /* move of_flat_tree if needed */ @@ -957,36 +966,48 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, "must RESET the board to recover.\n"); do_reset (cmdtp, flag, argc, argv); } + puts ("OK\n"); } /* * Add the chosen node if it doesn't exist, add the env and bd_t * if the user wants it (the logic is in the subroutines). */ - if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { - puts ("ERROR: /chosen node create failed - " - "must RESET the board to recover.\n"); - do_reset (cmdtp, flag, argc, argv); - } + if (of_flat_tree) { + if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { + puts ("ERROR: /chosen node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); + } #ifdef CONFIG_OF_HAS_UBOOT_ENV - if (fdt_env(of_flat_tree) < 0) { - puts ("ERROR: /u-boot-env node create failed - " - "must RESET the board to recover.\n"); - do_reset (cmdtp, flag, argc, argv); - } + if (fdt_env(of_flat_tree) < 0) { + puts ("ERROR: /u-boot-env node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); + } #endif #ifdef CONFIG_OF_HAS_BD_T - if (fdt_bd_t(of_flat_tree) < 0) { - puts ("ERROR: /bd_t node create failed - " - "must RESET the board to recover.\n"); - do_reset (cmdtp, flag, argc, argv); - } + if (fdt_bd_t(of_flat_tree) < 0) { + puts ("ERROR: /bd_t node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); + } #endif #ifdef CONFIG_OF_BOARD_SETUP - /* Call the board-specific fixup routine */ - ft_board_setup(of_flat_tree, gd->bd); + /* Call the board-specific fixup routine */ + ft_board_setup(of_flat_tree, gd->bd); #endif + } #endif /* CONFIG_OF_LIBFDT */ #if defined(CONFIG_OF_FLAT_TREE) +#ifdef CFG_BOOTMAPSZ + /* + * The blob must be within CFG_BOOTMAPSZ, + * so we flag it to be copied if it is not. + */ + if (of_flat_tree >= (char *)CFG_BOOTMAPSZ) + of_data = (ulong)of_flat_tree; +#endif + /* move of_flat_tree if needed */ if (of_data) { ulong of_start, of_len; @@ -1002,6 +1023,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, printf (" Loading Device Tree to %08lx, end %08lx ... ", of_start, of_start + of_len - 1); memmove ((void *)of_start, (void *)of_data, of_len); + puts ("OK\n"); } /* * Create the /chosen node and modify the blob with board specific diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 89fefed..bb064ea 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -31,6 +31,7 @@ #include <command.h> #include <image.h> #include <asm/byteorder.h> +#include <asm/io.h> #if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA) # include <pcmcia.h> @@ -128,8 +129,6 @@ ulong ide_bus_offset[CFG_IDE_MAXBUS] = { }; -#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) - #ifndef CONFIG_AMIGAONEG3SE static int ide_bus_ok[CFG_IDE_MAXBUS]; #else @@ -172,8 +171,8 @@ static uchar ide_wait (int dev, ulong t); #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */ -static void __inline__ ide_outb(int dev, int port, unsigned char val); -static unsigned char __inline__ ide_inb(int dev, int port); +void inline ide_outb(int dev, int port, unsigned char val); +unsigned char inline ide_inb(int dev, int port); static void input_data(int dev, ulong *sect_buf, int words); static void output_data(int dev, ulong *sect_buf, int words); static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); @@ -805,45 +804,27 @@ set_pcmcia_timing (int pmode) /* ------------------------------------------------------------------------- */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) -static void __inline__ -ide_outb(int dev, int port, unsigned char val) +void inline +__ide_outb(int dev, int port, unsigned char val) { debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", - dev, port, val, (ATA_CURR_BASE(dev)+port)); - - /* Ensure I/O operations complete */ - EIEIO; - *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))) = val; -} -#else /* ! __PPC__ */ -static void __inline__ -ide_outb(int dev, int port, unsigned char val) -{ - outb(val, ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)); + dev, port, val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); + outb(val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); } -#endif /* __PPC__ */ - +void inline ide_outb (int dev, int port, unsigned char val) + __attribute__((weak, alias("__ide_outb"))); -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) -static unsigned char __inline__ -ide_inb(int dev, int port) +unsigned char inline +__ide_inb(int dev, int port) { uchar val; - /* Ensure I/O operations complete */ - EIEIO; - val = *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); + val = inb((ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", - dev, port, (ATA_CURR_BASE(dev)+port), val); - return (val); + dev, port, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)), val); + return val; } -#else /* ! __PPC__ */ -static unsigned char __inline__ -ide_inb(int dev, int port) -{ - return inb(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)); -} -#endif /* __PPC__ */ +unsigned char inline ide_inb(int dev, int port) + __attribute__((weak, alias("__ide_inb"))); #ifdef __PPC__ # ifdef CONFIG_AMIGAONEG3SE diff --git a/common/cmd_mii.c b/common/cmd_mii.c index f6b98d1..72e11d5 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -438,7 +438,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int rcode = 0; char *devname; -#ifdef CONFIG_8xx +#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x) mii_init (); #endif diff --git a/common/cmd_nand.c b/common/cmd_nand.c index c72612d..254a775 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -468,14 +468,31 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) { int r; - char *ep; + char *ep, *s; ulong cnt; image_header_t *hdr; + int jffs2 = 0; + + s = strchr(cmd, '.'); + if (s != NULL && + (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) + jffs2 = 1; printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset); cnt = nand->oobblock; - r = nand_read(nand, offset, &cnt, (u_char *) addr); + if (jffs2) { + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = cnt; + opts.offset = offset; + opts.quiet = 1; + r = nand_read_opts(nand, &opts); + } else { + r = nand_read(nand, offset, &cnt, (u_char *) addr); + } + if (r) { puts("** Read error\n"); show_boot_progress (-56); @@ -495,8 +512,18 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, print_image_hdr(hdr); cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t)); + if (jffs2) { + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = cnt; + opts.offset = offset; + opts.quiet = 1; + r = nand_read_opts(nand, &opts); + } else { + r = nand_read(nand, offset, &cnt, (u_char *) addr); + } - r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); show_boot_progress (-58); @@ -545,7 +572,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (argc > 3) goto usage; if (argc == 3) - addr = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[1], NULL, 16); else addr = CFG_LOAD_ADDR; return nand_load_image(cmdtp, &nand_info[dev->id->num], @@ -604,7 +631,7 @@ usage: U_BOOT_CMD(nboot, 4, 1, do_nandboot, "nboot - boot from NAND device\n", - "[partition] | [[[loadAddr] dev] offset]\n"); + "[.jffs2] [partition] | [[[loadAddr] dev] offset]\n"); #endif diff --git a/common/env_flash.c b/common/env_flash.c index 7a37e55..eccfb62 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -107,13 +107,6 @@ int env_init(void) ulong addr1 = (ulong)&(flash_addr->data); ulong addr2 = (ulong)&(flash_addr_new->data); -#ifdef CONFIG_OMAP2420H4 - int flash_probe(void); - - if(flash_probe() == 0) - goto bad_flash; -#endif - crc1_ok = (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc); crc2_ok = (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc); @@ -143,9 +136,6 @@ int env_init(void) gd->env_valid = 2; } -#ifdef CONFIG_OMAP2420H4 -bad_flash: -#endif return (0); } @@ -259,20 +249,12 @@ Done: int env_init(void) { -#ifdef CONFIG_OMAP2420H4 - int flash_probe(void); - - if(flash_probe() == 0) - goto bad_flash; -#endif if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { gd->env_addr = (ulong)&(env_ptr->data); gd->env_valid = 1; return(0); } -#ifdef CONFIG_OMAP2420H4 -bad_flash: -#endif + gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 0; return (0); diff --git a/common/fdt_support.c b/common/fdt_support.c index caaa682..175d59e 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -46,7 +46,6 @@ struct fdt_header *fdt; int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) { - bd_t *bd = gd->bd; int nodeoffset; int err; u32 tmp; /* used to set 32 bit integer properties */ diff --git a/common/serial.c b/common/serial.c index 13e9f30..dee1cc0 100644 --- a/common/serial.c +++ b/common/serial.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct serial_device *serial_devices = NULL; static struct serial_device *serial_current = NULL; -#ifndef CONFIG_LWMON +#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X) struct serial_device *default_serial_console (void) { #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) @@ -65,7 +65,7 @@ struct serial_device *default_serial_console (void) } #endif -static int serial_register (struct serial_device *dev) +int serial_register (struct serial_device *dev) { dev->init += gd->reloc_off; dev->setbrg += gd->reloc_off; @@ -110,6 +110,15 @@ void serial_initialize (void) serial_register(&eserial4_device); #endif #endif /* CFG_NS16550_SERIAL */ +#if defined (CONFIG_FFUART) + serial_register(&serial_ffuart_device); +#endif +#if defined (CONFIG_BTUART) + serial_register(&serial_btuart_device); +#endif +#if defined (CONFIG_STUART) + serial_register(&serial_stuart_device); +#endif serial_assign (default_serial_console ()->name); } diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk index e39e774..6ab0dd3 100644 --- a/cpu/arm1136/config.mk +++ b/cpu/arm1136/config.mk @@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv5 # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/mcf523x/Makefile b/cpu/mcf523x/Makefile new file mode 100644 index 0000000..d0e9b45 --- /dev/null +++ b/cpu/mcf523x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = start.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf523x/config.mk b/cpu/mcf523x/config.mk new file mode 100644 index 0000000..ba324a8 --- /dev/null +++ b/cpu/mcf523x/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf523x/cpu.c b/cpu/mcf523x/cpu.c new file mode 100644 index 0000000..f0d954b --- /dev/null +++ b/cpu/mcf523x/cpu.c @@ -0,0 +1,109 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> + +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + + ccm->rcr = CCM_RCR_SOFTRST; + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x31: + id = 5235; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000)); + } + + return 0; +}; + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + wdp->sr = 0x5555; /* Count register */ + asm("nop"); + wdp->sr = 0xAAAA; /* Count register */ +} + +int watchdog_disable(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ + wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + + puts("WATCHDOG:disabled\n"); + return (0); +} + +int watchdog_init(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + u32 wdog_module = 0; + + /* set timeout and enable watchdog */ + wdog_module = ((CFG_CLK / CFG_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module |= (wdog_module / 8192); + wdp->mr = wdog_module; + + wdp->cr = WTM_WCR_EN; + puts("WATCHDOG:enabled\n"); + + return (0); +} +#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c new file mode 100644 index 0000000..55c9cd3 --- /dev/null +++ b/cpu/mcf523x/cpu_init.c @@ -0,0 +1,145 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> + +#include <asm/immap.h> + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + volatile scm_t *scm = (scm_t *) MMAP_SCM; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + wdog->cr = 0; +#endif + + scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + + /* Port configuration */ + gpio->par_cs = 0; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS1; + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS2; + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS3; + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS4; + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS5; + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS6; + fbcs->csar6 = CFG_CS6_BASE; + fbcs->cscr6 = CFG_CS6_CTRL; + fbcs->csmr6 = CFG_CS6_MASK; +#endif + +#if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS7; + fbcs->csar7 = CFG_CS7_BASE; + fbcs->cscr7 = CFG_CS7_CTRL; + fbcs->csmr7 = CFG_CS7_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK); + gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA); +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + break; + case 2: + gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + break; + } +} diff --git a/cpu/mcf523x/interrupts.c b/cpu/mcf523x/interrupts.c new file mode 100644 index 0000000..125c53b --- /dev/null +++ b/cpu/mcf523x/interrupts.c @@ -0,0 +1,49 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include <common.h> +#include <asm/immap.h> + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrl0 |= 0x1; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrl0 &= ~INTC_IPRL_INT0; + intp->imrl0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf523x/speed.c b/cpu/mcf523x/speed.c new file mode 100644 index 0000000..247d318 --- /dev/null +++ b/cpu/mcf523x/speed.c @@ -0,0 +1,49 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + + pll->syncr = PLL_SYNCR_MFD(1); + + while (!(pll->synsr & PLL_SYNSR_LOCK)); + + gd->bus_clk = CFG_CLK; + gd->cpu_clk = (gd->bus_clk * 2); + + return (0); +} diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S new file mode 100644 index 0000000..2bd603d --- /dev/null +++ b/cpu/mcf523x/start.S @@ -0,0 +1,340 @@ +/* + * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> + * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + /* invalidate and disable cache */ + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + nop + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2 + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the + first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + nop + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + move.l #(CFG_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR1 /* Enable cache */ + + move.l #0x80400100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #0x00000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable cache */ + clr.l %d0 /* Setup cache mask */ + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #0x80600100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + rts + + .globl dcache_enable +dcache_enable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + /* No dcache, just a dummy function */ + .globl dcache_disable +dcache_disable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_status +dcache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/mcf52x2/Makefile b/cpu/mcf52x2/Makefile index 70d57cf..937cdd0 100644 --- a/cpu/mcf52x2/Makefile +++ b/cpu/mcf52x2/Makefile @@ -27,8 +27,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = -COBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o +START = start.o +COBJS = interrupts.o cpu.o speed.o cpu_init.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index ce59d39..71ea408 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -28,33 +28,15 @@ #include <common.h> #include <watchdog.h> #include <command.h> +#include <asm/immap.h> #ifdef CONFIG_M5271 -#include <asm/immap_5271.h> -#include <asm/m5271.h> -#endif - -#ifdef CONFIG_M5272 -#include <asm/immap_5272.h> -#include <asm/m5272.h> -#endif - -#ifdef CONFIG_M5282 -#include <asm/m5282.h> -#include <asm/immap_5282.h> -#endif - -#ifdef CONFIG_M5249 -#include <asm/m5249.h> -#endif - -#ifdef CONFIG_M5271 /* * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to * determine which one we are running on, based on the Chip Identification * Register (CIR). */ -int checkcpu (void) +int checkcpu(void) { char buf[32]; unsigned short cir; /* Chip Identification Register */ @@ -80,156 +62,194 @@ int checkcpu (void) if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CFG_CLK)); + cpu_model, prn, strmhz(buf, CFG_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" - " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CFG_CLK)); + " (PIN: 0x%x) rev. %hu, at %s MHz\n", + pin, prn, strmhz(buf, CFG_CLK)); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ mbar_writeByte(MCF_RCM_RCR, - MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); + MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); return 0; }; #if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) +void watchdog_reset(void) { mbar_writeShort(MCF_WTM_WSR, 0x5555); mbar_writeShort(MCF_WTM_WSR, 0xAAAA); } -int watchdog_disable (void) +int watchdog_disable(void) { mbar_writeShort(MCF_WTM_WCR, 0); return (0); } -int watchdog_init (void) +int watchdog_init(void) { mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_WATCHDOG */ #endif #ifdef CONFIG_M5272 -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR); +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); wdp->wdog_wrrr = 0; - udelay (1000); + udelay(1000); /* enable watchdog, set timeout to 0 and wait */ wdp->wdog_wrrr = 1; - while (1); + while (1) ; /* we don't return! */ return 0; }; -int checkcpu(void) { - ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR); +int checkcpu(void) +{ + volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); uchar msk; - char *suf; + char *suf; - puts ("CPU: "); - msk = (*dirp > 28) & 0xf; + puts("CPU: "); + msk = (sysctrl->sc_dir > 28) & 0xf; switch (msk) { - case 0x2: suf = "1K75N"; break; - case 0x4: suf = "3K75N"; break; - default: - suf = NULL; - printf ("Freescale MCF5272 (Mask:%01x)\n", msk); - break; - } + case 0x2: + suf = "1K75N"; + break; + case 0x4: + suf = "3K75N"; + break; + default: + suf = NULL; + printf("Freescale MCF5272 (Mask:%01x)\n", msk); + break; + } if (suf) - printf ("Freescale MCF5272 %s\n", suf); + printf("Freescale MCF5272 %s\n", suf); return 0; }; #if defined(CONFIG_WATCHDOG) /* Called by macro WATCHDOG_RESET */ -void watchdog_reset (void) +void watchdog_reset(void) { - volatile immap_t * regp = (volatile immap_t *)CFG_MBAR; - regp->wdog_reg.wdog_wcr = 0; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdt->wdog_wcr = 0; } -int watchdog_disable (void) +int watchdog_disable(void) { - volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ - regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ - regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */ + wdt->wdog_wcr = 0; /* reset watchdog counter */ + wdt->wdog_wirr = 0; /* disable watchdog interrupt */ + wdt->wdog_wrrr = 0; /* disable watchdog timer */ - puts ("WATCHDOG:disabled\n"); + puts("WATCHDOG:disabled\n"); return (0); } -int watchdog_init (void) +int watchdog_init(void) { - volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ + wdt->wdog_wirr = 0; /* disable watchdog interrupt */ /* set timeout and enable watchdog */ - regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; - regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ + wdt->wdog_wrrr = + ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; + wdt->wdog_wcr = 0; /* reset watchdog counter */ - puts ("WATCHDOG:enabled\n"); + puts("WATCHDOG:enabled\n"); return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ - -#endif /* #ifdef CONFIG_M5272 */ +#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_M5272 */ #ifdef CONFIG_M5282 -int checkcpu (void) +int checkcpu(void) { unsigned char resetsource = MCFRESET_RSR; - printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", - MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); - printf ("Reset:%s%s%s%s%s%s%s\n", - (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", - (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", - (resetsource & MCFRESET_RSR_EXT) ? " External" : "", - (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", - (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", - (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", - (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "" - ); + printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", + MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); + printf("Reset:%s%s%s%s%s%s%s\n", + (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", + (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", + (resetsource & MCFRESET_RSR_EXT) ? " External" : "", + (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", + (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", + (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", + (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { MCFRESET_RCR = MCFRESET_RCR_SOFTRST; return 0; }; #endif -#ifdef CONFIG_M5249 /* test-only: todo... */ -int checkcpu (void) +#ifdef CONFIG_M5249 +int checkcpu(void) { char buf[32]; - printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); + printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", + strmhz(buf, CFG_CLK)); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ /* enable watchdog, set timeout to 0 and wait */ mbar_writeByte(MCFSIM_SYPCR, 0xc0); - while (1); + while (1) ; + + /* we don't return! */ + return 0; +}; +#endif + +#ifdef CONFIG_M5253 +int checkcpu(void) +{ + char buf[32]; + + unsigned char resetsource = mbar_readLong(SIM_RSR); + printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", + strmhz(buf, CFG_CLK)); + + if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { + printf("Reset:%s%s\n", + (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" + : "", + (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : + ""); + } + return 0; +} + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + /* enable watchdog, set timeout to 0 and wait */ + mbar_writeByte(SIM_SYPCR, 0xc0); + while (1) ; /* we don't return! */ return 0; diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 1748ea9..458b85e 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -6,6 +6,10 @@ * (C) Copyright 2005 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * Hayden Fraser (Hayden.Fraser@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -27,28 +31,78 @@ #include <common.h> #include <watchdog.h> +#include <asm/immap.h> -#ifdef CONFIG_M5271 -#include <asm/m5271.h> -#include <asm/immap_5271.h> -#endif +#if defined(CONFIG_M5253) +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_SYPCR, 0x00); + mbar_writeByte(MCFSIM_SWIVR, 0x0f); + mbar_writeByte(MCFSIM_SWSR, 0x00); + mbar_writeByte(MCFSIM_SWDICR, 0x00); + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); + mbar_writeByte(MCFSIM_I2CICR, 0x00); + mbar_writeByte(MCFSIM_UART1ICR, 0x00); + mbar_writeByte(MCFSIM_UART2ICR, 0x00); + mbar_writeByte(MCFSIM_ICR6, 0x00); + mbar_writeByte(MCFSIM_ICR7, 0x00); + mbar_writeByte(MCFSIM_ICR8, 0x00); + mbar_writeByte(MCFSIM_ICR9, 0x00); + mbar_writeByte(MCFSIM_QSPIICR, 0x00); -#ifdef CONFIG_M5272 -#include <asm/m5272.h> -#include <asm/immap_5272.h> -#endif + mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); + mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ + mbar2_writeByte(MCFSIM_SPURVEC, 0x00); -#ifdef CONFIG_M5282 -#include <asm/m5282.h> -#include <asm/immap_5282.h> -#endif + /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ -#ifdef CONFIG_M5249 -#include <asm/m5249.h> -#endif + /* + * Setup chip selects... + */ + + mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); + mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); + mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); + + mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); + mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); + mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); + + /* enable instruction cache now */ + icache_enable(); +} + +/*initialize higher level parts of CPU like timers */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(void) +{ + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + break; + case 1: + break; + case 2: + break; + } +} +#endif /* #if defined(CONFIG_M5253) */ #if defined(CONFIG_M5271) -void cpu_init_f (void) +void cpu_init_f(void) { #ifndef CONFIG_WATCHDOG /* Disable the watchdog if we aren't using it */ @@ -58,25 +112,35 @@ void cpu_init_f (void) /* Set clockspeed to 100MHz */ mbar_writeShort(MCF_FMPLL_SYNCR, MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); - while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK); - - /* Enable UART pins */ - mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | - MCF_GPIO_PAR_UART_U0RXD | - MCF_GPIO_PAR_UART_U1RXD_UART1 | - MCF_GPIO_PAR_UART_U1TXD_UART1); - - /* Enable Ethernet pins */ - mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; } /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { return (0); } + +void uart_port_conf(void) +{ + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | + MCF_GPIO_PAR_UART_U0RXD); + break; + case 1: + mbar_writeShort(MCF_GPIO_PAR_UART, + MCF_GPIO_PAR_UART_U1RXD_UART1 | + MCF_GPIO_PAR_UART_U1TXD_UART1); + break; + case 2: + mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000); + break; + } +} #endif #if defined(CONFIG_M5272) @@ -87,69 +151,68 @@ int cpu_init_r (void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f (void) +void cpu_init_f(void) { /* if we come from RAM we assume the CPU is * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - volatile immap_t *regp = (immap_t *)CFG_MBAR; - - volatile unsigned char *mbar; - mbar = (volatile unsigned char *) CFG_MBAR; + volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR); + volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); + volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - regp->sysctrl_reg.sc_scr = CFG_SCR; - regp->sysctrl_reg.sc_spr = CFG_SPR; + sysctrl->sc_scr = CFG_SCR; + sysctrl->sc_spr = CFG_SPR; /* Setup Ports: */ - regp->gpio_reg.gpio_pacnt = CFG_PACNT; - regp->gpio_reg.gpio_paddr = CFG_PADDR; - regp->gpio_reg.gpio_padat = CFG_PADAT; - regp->gpio_reg.gpio_pbcnt = CFG_PBCNT; - regp->gpio_reg.gpio_pbddr = CFG_PBDDR; - regp->gpio_reg.gpio_pbdat = CFG_PBDAT; - regp->gpio_reg.gpio_pdcnt = CFG_PDCNT; + gpio->gpio_pacnt = CFG_PACNT; + gpio->gpio_paddr = CFG_PADDR; + gpio->gpio_padat = CFG_PADAT; + gpio->gpio_pbcnt = CFG_PBCNT; + gpio->gpio_pbddr = CFG_PBDDR; + gpio->gpio_pbdat = CFG_PBDAT; + gpio->gpio_pdcnt = CFG_PDCNT; /* Memory Controller: */ - regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM; - regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM; + csctrl->cs_br0 = CFG_BR0_PRELIM; + csctrl->cs_or0 = CFG_OR0_PRELIM; #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM; - regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM; + csctrl->cs_br1 = CFG_BR1_PRELIM; + csctrl->cs_or1 = CFG_OR1_PRELIM; #endif #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM; - regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM; + csctrl->cs_br2 = CFG_BR2_PRELIM; + csctrl->cs_or2 = CFG_OR2_PRELIM; #endif #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM; - regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM; + csctrl->cs_br3 = CFG_BR3_PRELIM; + csctrl->cs_or3 = CFG_OR3_PRELIM; #endif #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) - regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM; - regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM; + csctrl->cs_br4 = CFG_BR4_PRELIM; + csctrl->cs_or4 = CFG_OR4_PRELIM; #endif #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) - regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM; - regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM; + csctrl->cs_br5 = CFG_BR5_PRELIM; + csctrl->cs_or5 = CFG_OR5_PRELIM; #endif #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) - regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM; - regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM; + csctrl->cs_br6 = CFG_BR6_PRELIM; + csctrl->cs_or6 = CFG_OR6_PRELIM; #endif #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) - regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM; - regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM; + csctrl->cs_br7 = CFG_BR7_PRELIM; + csctrl->cs_or7 = CFG_OR7_PRELIM; #endif -#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ +#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ /* enable instruction cache now */ icache_enable(); @@ -159,14 +222,30 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { return (0); } -#endif /* #if defined(CONFIG_M5272) */ +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; -#ifdef CONFIG_M5282 + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); + gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); + break; + case 1: + gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); + gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); + break; + } +} +#endif /* #if defined(CONFIG_M5272) */ + +#if defined(CONFIG_M5282) /* * Breath some life into the CPU... * @@ -174,7 +253,7 @@ int cpu_init_r (void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f (void) +void cpu_init_f(void) { #ifndef CONFIG_WATCHDOG /* disable watchdog if we aren't using it */ @@ -183,7 +262,11 @@ void cpu_init_f (void) #ifndef CONFIG_MONITOR_IS_IN_RAM /* Set speed /PLL */ - MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); + MCFCLOCK_SYNCR = + MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); + while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; + + MCFGPIO_PBCDPAR = 0xc0; /* Set up the GPIO ports */ #ifdef CFG_PEPAR @@ -228,29 +311,28 @@ void cpu_init_f (void) defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \ defined(CFG_CS0_WS) - MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; - - #if (CFG_CS0_WIDTH == 8) - #define CFG_CS0_PS MCFCSM_CSCR_PS_8 - #elif (CFG_CS0_WIDTH == 16) - #define CFG_CS0_PS MCFCSM_CSCR_PS_16 - #elif (CFG_CS0_WIDTH == 32) - #define CFG_CS0_PS MCFCSM_CSCR_PS_32 - #else - #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" - #endif - MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) - |CFG_CS0_PS - |MCFCSM_CSCR_AA; - - #if (CFG_CS0_RO != 0) - MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1) - |MCFCSM_CSMR_WP|MCFCSM_CSMR_V; - #else - MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V; - #endif + MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; + +#if (CFG_CS0_WIDTH == 8) +#define CFG_CS0_PS MCFCSM_CSCR_PS_8 +#elif (CFG_CS0_WIDTH == 16) +#define CFG_CS0_PS MCFCSM_CSCR_PS_16 +#elif (CFG_CS0_WIDTH == 32) +#define CFG_CS0_PS MCFCSM_CSCR_PS_32 +#else +#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" +#endif + MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) + | CFG_CS0_PS | MCFCSM_CSCR_AA; + +#if (CFG_CS0_RO != 0) + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) + | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; #else - #waring "Chip Select 0 are not initialized/used" + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V; +#endif +#else +#waring "Chip Select 0 are not initialized/used" #endif #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ @@ -259,29 +341,27 @@ void cpu_init_f (void) MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF; - #if (CFG_CS1_WIDTH == 8) - #define CFG_CS1_PS MCFCSM_CSCR_PS_8 - #elif (CFG_CS1_WIDTH == 16) - #define CFG_CS1_PS MCFCSM_CSCR_PS_16 - #elif (CFG_CS1_WIDTH == 32) - #define CFG_CS1_PS MCFCSM_CSCR_PS_32 - #else - #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" - #endif - MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) - |CFG_CS1_PS - |MCFCSM_CSCR_AA; - - #if (CFG_CS1_RO != 0) - MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1) - |MCFCSM_CSMR_WP - |MCFCSM_CSMR_V; - #else - MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1) - |MCFCSM_CSMR_V; - #endif +#if (CFG_CS1_WIDTH == 8) +#define CFG_CS1_PS MCFCSM_CSCR_PS_8 +#elif (CFG_CS1_WIDTH == 16) +#define CFG_CS1_PS MCFCSM_CSCR_PS_16 +#elif (CFG_CS1_WIDTH == 32) +#define CFG_CS1_PS MCFCSM_CSCR_PS_32 +#else +#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" +#endif + MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) + | CFG_CS1_PS | MCFCSM_CSCR_AA; + +#if (CFG_CS1_RO != 0) + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) + | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; +#else + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) + | MCFCSM_CSMR_V; +#endif #else - #warning "Chip Select 1 are not initialized/used" +#warning "Chip Select 1 are not initialized/used" #endif #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \ @@ -290,29 +370,27 @@ void cpu_init_f (void) MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF; - #if (CFG_CS2_WIDTH == 8) - #define CFG_CS2_PS MCFCSM_CSCR_PS_8 - #elif (CFG_CS2_WIDTH == 16) - #define CFG_CS2_PS MCFCSM_CSCR_PS_16 - #elif (CFG_CS2_WIDTH == 32) - #define CFG_CS2_PS MCFCSM_CSCR_PS_32 - #else - #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" - #endif - MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) - |CFG_CS2_PS - |MCFCSM_CSCR_AA; - - #if (CFG_CS2_RO != 0) - MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1) - |MCFCSM_CSMR_WP - |MCFCSM_CSMR_V; - #else - MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1) - |MCFCSM_CSMR_V; - #endif +#if (CFG_CS2_WIDTH == 8) +#define CFG_CS2_PS MCFCSM_CSCR_PS_8 +#elif (CFG_CS2_WIDTH == 16) +#define CFG_CS2_PS MCFCSM_CSCR_PS_16 +#elif (CFG_CS2_WIDTH == 32) +#define CFG_CS2_PS MCFCSM_CSCR_PS_32 #else - #warning "Chip Select 2 are not initialized/used" +#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" +#endif + MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) + | CFG_CS2_PS | MCFCSM_CSCR_AA; + +#if (CFG_CS2_RO != 0) + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) + | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; +#else + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) + | MCFCSM_CSMR_V; +#endif +#else +#warning "Chip Select 2 are not initialized/used" #endif #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \ @@ -321,32 +399,30 @@ void cpu_init_f (void) MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF; - #if (CFG_CS3_WIDTH == 8) - #define CFG_CS3_PS MCFCSM_CSCR_PS_8 - #elif (CFG_CS3_WIDTH == 16) - #define CFG_CS3_PS MCFCSM_CSCR_PS_16 - #elif (CFG_CS3_WIDTH == 32) - #define CFG_CS3_PS MCFCSM_CSCR_PS_32 - #else - #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" - #endif - MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) - |CFG_CS3_PS - |MCFCSM_CSCR_AA; - - #if (CFG_CS3_RO != 0) - MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1) - |MCFCSM_CSMR_WP - |MCFCSM_CSMR_V; - #else - MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1) - |MCFCSM_CSMR_V; - #endif +#if (CFG_CS3_WIDTH == 8) +#define CFG_CS3_PS MCFCSM_CSCR_PS_8 +#elif (CFG_CS3_WIDTH == 16) +#define CFG_CS3_PS MCFCSM_CSCR_PS_16 +#elif (CFG_CS3_WIDTH == 32) +#define CFG_CS3_PS MCFCSM_CSCR_PS_32 #else - #warning "Chip Select 3 are not initialized/used" +#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" #endif + MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) + | CFG_CS3_PS | MCFCSM_CSCR_AA; -#endif /* CONFIG_MONITOR_IS_IN_RAM */ +#if (CFG_CS3_RO != 0) + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) + | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; +#else + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) + | MCFCSM_CSMR_V; +#endif +#else +#warning "Chip Select 3 are not initialized/used" +#endif + +#endif /* CONFIG_MONITOR_IS_IN_RAM */ /* defer enabling cache until boot (see do_go) */ /* icache_enable(); */ @@ -355,10 +431,29 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { return (0); } + +void uart_port_conf(void) +{ + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + MCFGPIO_PUAPAR &= 0xFc; + MCFGPIO_PUAPAR |= 0x03; + break; + case 1: + MCFGPIO_PUAPAR &= 0xF3; + MCFGPIO_PUAPAR |= 0x0C; + break; + case 2: + MCFGPIO_PASPAR &= 0xFF0F; + MCFGPIO_PASPAR |= 0x00A0; + break; + } +} #endif #if defined(CONFIG_M5249) @@ -369,33 +464,13 @@ int cpu_init_r (void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f (void) +void cpu_init_f(void) { -#ifndef CFG_PLL_BYPASS - /* - * Setup the PLL to run at the specified speed - * - */ - volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); - unsigned long pllcr; -#ifdef CFG_FAST_CLK - pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ -#else - pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ -#endif - cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ - pllcr ^= 0x00000001; /* Set pll bypass to 1 */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ - udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CFG_PLL_BYPASS */ - /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins - * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins - * which is their primary function. - * ~Jeremy + * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins + * which is their primary function. + * ~Jeremy */ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); @@ -411,7 +486,7 @@ void cpu_init_f (void) * ~Jeremy * */ - mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); mbar_writeByte(MCFSIM_SWSR, 0x00); @@ -431,7 +506,7 @@ void cpu_init_f (void) mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ + mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ /* Setup interrupt priorities for gpio7 */ /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ @@ -459,8 +534,19 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { return (0); } -#endif /* #if defined(CONFIG_M5249) */ + +void uart_port_conf(void) +{ + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + break; + case 1: + break; + } +} +#endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c deleted file mode 100644 index ef9c798..0000000 --- a/cpu/mcf52x2/fec.c +++ /dev/null @@ -1,605 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <malloc.h> -#include <asm/fec.h> - -#ifdef CONFIG_M5271 -#include <asm/m5271.h> -#include <asm/immap_5271.h> -#endif - -#ifdef CONFIG_M5272 -#include <asm/m5272.h> -#include <asm/immap_5272.h> -#endif - -#ifdef CONFIG_M5282 -#include <asm/m5282.h> -#include <asm/immap_5282.h> -#endif - -#include <net.h> -#include <command.h> - -#ifdef CONFIG_M5272 -#define FEC_ADDR (CFG_MBAR + 0x840) -#endif -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) -#define FEC_ADDR (CFG_MBAR + 0x1000) -#endif - -#undef ET_DEBUG -#undef MII_DEBUG - -#if defined(CONFIG_CMD_NET) && defined(FEC_ENET) - -#ifdef CFG_DISCOVER_PHY -#include <miiphy.h> -static void mii_discover_phy (void); -#endif - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FEC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx = NULL; - -int eth_send (volatile void *packet, int length) -{ - int j, rc; - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - /* section 16.9.23.3 - * Wait for ready - */ - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) - && (j < TOUT_LOOP)) { - udelay (1); - j++; - } - if (j >= TOUT_LOOP) { - printf ("TX not ready\n"); - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; - - /* Activate transmit Buffer Descriptor polling */ - fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ - - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) - && (j < TOUT_LOOP)) { - udelay (1); - j++; - } - if (j >= TOUT_LOOP) { - printf ("TX timeout\n"); - } -#ifdef ET_DEBUG - printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", - __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc, - (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2); -#endif - - /* return only status bits */ ; - rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); - - txIdx = (txIdx + 1) % TX_BUF_CNT; - - return rc; -} - -int eth_rx (void) -{ - int length; - volatile fec_t *fecp = (fec_t *) FEC_ADDR; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("%s[%d] err: %x\n", - __FUNCTION__, __LINE__, - rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - /* Pass the packet up to the protocol layers. */ - NetReceive (NetRxPackets[rxIdx], length - 4); - } - - /* Give the buffer back to the FEC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - - /* Try to fill Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - } - - return length; -} - -/************************************************************** - * - * FEC Ethernet Initialization Routine - * - *************************************************************/ -#define FEC_ECNTRL_ETHER_EN 0x00000002 -#define FEC_ECNTRL_RESET 0x00000001 - -#define FEC_RCNTRL_BC_REJ 0x00000010 -#define FEC_RCNTRL_PROM 0x00000008 -#define FEC_RCNTRL_MII_MODE 0x00000004 -#define FEC_RCNTRL_DRT 0x00000002 -#define FEC_RCNTRL_LOOP 0x00000001 - -#define FEC_TCNTRL_FDEN 0x00000004 -#define FEC_TCNTRL_HBC 0x00000002 -#define FEC_TCNTRL_GTS 0x00000001 - -#define FEC_RESET_DELAY 50000 - -int eth_init (bd_t * bd) -{ -#ifndef CFG_ENET_BD_BASE - DECLARE_GLOBAL_DATA_PTR; -#endif - int i; - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - fecp->fec_ecntrl = FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return 0; - } - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt */ - fecp->fec_ievent = 0xffffffff; - - /* Set station address */ -#define ea bd->bi_enetaddr - fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | - (ea[2] << 8) | (ea[3]); - fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16); -#ifdef ET_DEBUG - printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", - ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); -#endif -#undef ea - -#ifdef CONFIG_M5271 - /* Clear multicast address hash table - */ - fecp->fec_ghash_table_high = 0; - fecp->fec_ghash_table_low = 0; - - /* Clear individual address hash table - */ - fecp->fec_ihash_table_high = 0; - fecp->fec_ihash_table_low = 0; -#else - /* Clear multicast address hash table - */ -#ifdef CONFIG_M5282 - fecp->fec_ihash_table_high = 0; - fecp->fec_ihash_table_low = 0; -#else - fecp->fec_hash_table_high = 0; - fecp->fec_hash_table_low = 0; -#endif -#endif - - /* Set maximum receive buffer size. - */ - fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; - - /* - * Setup Buffers and Buffer Desriptors - */ - rxIdx = 0; - txIdx = 0; - - if (!rtx) { -#ifdef CFG_ENET_BD_BASE - rtx = (RTXBD *) CFG_ENET_BD_BASE; -#else - rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off - - (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t) - +0xFF) - & ~0xFF) - ); - debug("set ENET_DB_BASE to %lX\n",(long) rtx); -#endif - } - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; - } - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Last, Tx CRC - */ - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* Set receive and transmit descriptor base - */ - fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); - fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); - - /* Enable MII mode - */ - -#if 0 /* Full duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; - fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; -#else /* Half duplex mode */ - fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ - fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; - fecp->fec_x_cntrl = 0; -#endif - /* Set MII speed */ - fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10; - fecp->fec_mii_speed *= 2; - - /* Configure port B for MII. - */ - /* port initialization was already made in cpu_init_f() */ - - /* Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; - -#ifdef CFG_DISCOVER_PHY - /* wait for the PHY to wake up after reset */ - mii_discover_phy (); -#endif - - /* And last, try to fill Rx Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - - return 1; -} - -void eth_halt (void) -{ - volatile fec_t *fecp = (fec_t *) FEC_ADDR; - - fecp->fec_ecntrl = 0; -} - - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) - -static int phyaddr = -1; /* didn't find a PHY yet */ -static uint phytype; - -/* Make MII read/write commands for the FEC. -*/ - -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18) | \ - (VAL & 0xffff)) - -/* Interrupt events/masks. -*/ -#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ -#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ -#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ -#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ -#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ -#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ -#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ -#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ -#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ -#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ - -/* PHY identification - */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ - -/* send command to phy using mii, wait for result */ -static uint mii_send (uint mii_cmd) -{ - uint mii_reply; - volatile fec_t *ep = (fec_t *) (FEC_ADDR); - - ep->fec_mii_data = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */ - mii_reply = ep->fec_mii_data; /* result from phy */ - ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif - -#if defined(CFG_DISCOVER_PHY) -static void mii_discover_phy (void) -{ -#define MAX_PHY_PASSES 11 - uint phyno; - int pass; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay (10000); /* wait 10ms */ - } - for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf ("PHY type 0x%x pass %d type ", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= mii_send (mk_mii_read (phyno, - PHY_PHYIDR2)); - -#ifdef ET_DEBUG - printf ("PHY @ 0x%x pass %d type ", phyno, - pass); - switch (phytype & 0xfffffff0) { - case PHY_ID_LXT970: - printf ("LXT970\n"); - break; - case PHY_ID_LXT971: - printf ("LXT971\n"); - break; - case PHY_ID_82555: - printf ("82555\n"); - break; - case PHY_ID_QS6612: - printf ("QS6612\n"); - break; - case PHY_ID_AMD79C784: - printf ("AMD79C784\n"); - break; - case PHY_ID_LSI80225B: - printf ("LSI L80225/B\n"); - break; - default: - printf ("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) { - printf ("No PHY device found.\n"); - } -} -#endif /* CFG_DISCOVER_PHY */ - -#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII) - -static int mii_init_done = 0; - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_init (void) -{ - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - int i; - - if (mii_init_done != 0) { - return; - } - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return; - } - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffffffff; - - /* Set MII speed */ - fecp->fec_mii_speed = 0x0e; - - /* Configure port B for MII. - */ - /* port initialization was already made in cpu_init_f() */ - - /* Now enable the transmit and receive processing */ - fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; - - mii_init_done = 1; -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcf52x2_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send (mk_mii_read (addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf ("0x%04x\n", *value); -#endif - - return 0; -} - -int mcf52x2_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send (mk_mii_write (addr, reg, value)); - -#ifdef MII_DEBUG - printf ("0x%04x\n", value); -#endif - - return 0; -} -#endif -#endif - -int mcf52x2_miiphy_initialize(bd_t *bis) -{ -#if defined(CONFIG_CMD_NET) && defined(FEC_ENET) -#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII) - miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write); -#endif -#endif - return 0; -} diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index 116747a..2ccbde5 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -1,9 +1,10 @@ /* - * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> - * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -26,168 +27,75 @@ #include <common.h> #include <watchdog.h> #include <asm/processor.h> - -#ifdef CONFIG_M5271 -#include <asm/m5271.h> -#include <asm/immap_5271.h> -#endif +#include <asm/immap.h> #ifdef CONFIG_M5272 -#include <asm/m5272.h> -#include <asm/immap_5272.h> -#endif - -#ifdef CONFIG_M5282 -#include <asm/m5282.h> -#include <asm/immap_5282.h> -#endif - -#ifdef CONFIG_M5249 -#include <asm/m5249.h> -#endif - - -#define NR_IRQS 31 - -/* - * Interrupt vector functions. - */ -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; -}; - -static struct interrupt_action irq_vecs[NR_IRQS]; - -static __inline__ unsigned short get_sr (void) +int interrupt_init(void) { - unsigned short sr; - - asm volatile ("move.w %%sr,%0":"=r" (sr):); + volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC); - return sr; -} - -static __inline__ void set_sr (unsigned short sr) -{ - asm volatile ("move.w %0,%%sr"::"r" (sr)); -} - -/************************************************************************/ -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) -{ -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec_base = 0; - -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif - - if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { - printf ("irq_install_handler: wrong interrupt vector %d\n", - vec); - return; - } - - irq_vecs[vec - vec_base].handler = handler; - irq_vecs[vec - vec_base].arg = arg; -} - -void irq_free_handler (int vec) -{ -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec_base = 0; - -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif + /* disable all external interrupts */ + intp->int_icr1 = 0x88888888; + intp->int_icr2 = 0x88888888; + intp->int_icr3 = 0x88888888; + intp->int_icr4 = 0x88888888; + intp->int_pitr = 0x00000000; + /* initialize vector register */ + intp->int_pivr = 0x40; - if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { - return; - } + enable_interrupts(); - irq_vecs[vec - vec_base].handler = NULL; - irq_vecs[vec - vec_base].arg = NULL; + return 0; } -void enable_interrupts (void) +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) { - unsigned short sr; + volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE); - sr = get_sr (); - set_sr (sr & ~0x0700); + intp->int_icr1 &= ~INT_ICR1_TMR3MASK; + intp->int_icr1 |= CFG_TMRINTR_PRI; } +#endif /* CONFIG_MCFTMR */ +#endif /* CONFIG_M5272 */ -int disable_interrupts (void) +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) +int interrupt_init(void) { - unsigned short sr; + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); - sr = get_sr (); - set_sr (sr | 0x0700); + /* Make sure all interrupts are disabled */ + intp->imrl0 |= 0x1; - return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ + enable_interrupts(); + return 0; } -void int_handler (struct pt_regs *fp) +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) { -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec, vec_base = 0; - - vec = (fp->vector >> 2) & 0xff; -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); - if (irq_vecs[vec - vec_base].handler != NULL) { - irq_vecs[vec - - vec_base].handler (irq_vecs[vec - vec_base].arg); - } else { - printf ("\nBogus External Interrupt Vector %d\n", vec); - } + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrl0 &= ~0xFFFFFFFE; + intp->imrl0 &= ~CFG_TMRINTR_MASK; } +#endif /* CONFIG_MCFTMR */ +#endif /* CONFIG_M5282 | CONFIG_M5271 */ - -#ifdef CONFIG_M5272 -int interrupt_init (void) +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) +int interrupt_init(void) { - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); - - /* disable all external interrupts */ - intp->int_icr1 = 0x88888888; - intp->int_icr2 = 0x88888888; - intp->int_icr3 = 0x88888888; - intp->int_icr4 = 0x88888888; - intp->int_pitr = 0x00000000; - /* initialize vector register */ - intp->int_pivr = 0x40; + enable_interrupts(); - enable_interrupts (); - - return 0; -} -#endif - -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) -int interrupt_init (void) -{ return 0; } -#endif -#ifdef CONFIG_M5249 -int interrupt_init (void) +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) { - enable_interrupts (); - - return 0; + mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); + mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI); } -#endif +#endif /* CONFIG_MCFTMR */ +#endif /* CONFIG_M5249 || CONFIG_M5253 */ diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c deleted file mode 100644 index 8be09e3..0000000 --- a/cpu/mcf52x2/serial.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <watchdog.h> - -#include <asm/mcfuart.h> - -#ifdef CONFIG_M5271 -#include <asm/m5271.h> -#endif - -#ifdef CONFIG_M5272 -#include <asm/m5272.h> -#endif - -#ifdef CONFIG_M5282 -#include <asm/m5282.h> -#endif - -#ifdef CONFIG_M5249 -#include <asm/m5249.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_M5249) || defined(CONFIG_M5271) -#define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a)) -#else -#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a)) -#endif - -void rs_serial_setbaudrate(int port,int baudrate) -{ -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271) - volatile unsigned char *uartp; -# ifndef CONFIG_M5271 - double fraction; -# endif - double clock; - - if (port == 0) - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - else - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - - clock = DoubleClock(baudrate); /* Set baud above */ - - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ - -# ifndef CONFIG_M5271 - fraction = ((clock - (int)clock) * 16.0) + 0.5; - uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ -# endif -#endif - -#if defined(CONFIG_M5282) - volatile unsigned char *uartp; - long clock; - - switch (port) { - case 1: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - break; - case 2: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); - break; - default: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - } - - clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */ - - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */ - -#endif -}; - -void rs_serial_init (int port, int baudrate) -{ - volatile unsigned char *uartp; - - /* - * Reset UART, get it into known state... - */ - switch (port) { - case 1: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - break; -#if defined(CONFIG_M5282) - case 2: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); - break; -#endif - default: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - } - - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ - - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ - - /* - * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity. - */ - uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8; - uartp[MCFUART_UMR] = MCFUART_MR2_STOP1; - - /* Mask UART interrupts */ - uartp[MCFUART_UIMR] = 0; - - /* Set clock Select Register: Tx/Rx clock is timer */ - uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; - - rs_serial_setbaudrate (port, baudrate); - - /* Enable Tx/Rx */ - uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; - - return; -} - -/****************************************************************************/ -/* - * Output a single character, using UART polled mode. - * This is used for console output. - */ - -void rs_put_char(char ch) -{ - volatile unsigned char *uartp; - int i; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - - for (i = 0; (i < 0x10000); i++) { - if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY) - break; - } - uartp[MCFUART_UTB] = ch; - return; -} - -int rs_is_char(void) -{ - volatile unsigned char *uartp; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0); -} - -int rs_get_char(void) -{ - volatile unsigned char *uartp; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - return(uartp[MCFUART_URB]); -} - -void serial_setbrg(void) { - rs_serial_setbaudrate(0,gd->bd->bi_baudrate); -} - -int serial_init(void) { - rs_serial_init(0,gd->baudrate); - return 0; -} - - -void serial_putc(const char c) { - if (c == '\n') - serial_putc ('\r'); - rs_put_char(c); -} - -void serial_puts (const char *s) { - while (*s) - serial_putc(*s++); -} - -int serial_getc(void) { - while(!rs_is_char()) - WATCHDOG_RESET(); - - return rs_get_char(); -} - -int serial_tstc() { - return rs_is_char(); -} diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c index ac860b2..bc1e200 100644 --- a/cpu/mcf52x2/speed.c +++ b/cpu/mcf52x2/speed.c @@ -2,6 +2,9 @@ * (C) Copyright 2003 * Josef Baumgartner <josef.baumgartner@telex.de> * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -23,6 +26,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/immap.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,8 +35,37 @@ DECLARE_GLOBAL_DATA_PTR; */ int get_clocks (void) { - gd->cpu_clk = CFG_CLK; +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) + volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); + unsigned long pllcr; + +#ifndef CFG_PLL_BYPASS + #ifdef CONFIG_M5249 + /* Setup the PLL to run at the specified speed */ +#ifdef CFG_FAST_CLK + pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ +#else + pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ +#endif +#endif /* CONFIG_M5249 */ + +#ifdef CONFIG_M5253 + pllcr = CFG_PLLCR; +#endif /* CONFIG_M5253 */ + + cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ + pllcr ^= 0x00000001; /* Set pll bypass to 1 */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ + udelay(0x20); /* Wait for a lock ... */ +#endif /* #ifndef CFG_PLL_BYPASS */ + +#endif /* CONFIG_M5249 || CONFIG_M5253 */ + + gd->cpu_clk = CFG_CLK; +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) gd->bus_clk = gd->cpu_clk / 2; #else gd->bus_clk = gd->cpu_clk; diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 7c9a7d2..686e2a5 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -121,7 +121,7 @@ _start: nop move.w #0x2700,%sr -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ move.c %d0, %MBAR @@ -133,7 +133,7 @@ _start: move.l #(CFG_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 -#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ +#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ @@ -159,7 +159,7 @@ _copy_flash: _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 movec %d0, %RAMBAR0 jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: @@ -167,7 +167,7 @@ _flashbar_setup_end: _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 movec %d0, %RAMBAR0 #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ @@ -326,10 +326,10 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ - #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ - defined(CFG_HALT_BEFOR_RAM_JUMP) - halt - #endif +#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ + defined(CFG_HALT_BEFOR_RAM_JUMP) + halt +#endif jsr (%a1) /*------------------------------------------------------------------------------*/ @@ -356,6 +356,24 @@ _int_handler: /*------------------------------------------------------------------------------*/ /* cache functions */ +#ifdef CONFIG_M5271 + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + + move.l #0x80000200, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts +#endif + #ifdef CONFIG_M5272 .globl icache_enable icache_enable: @@ -389,7 +407,7 @@ icache_state_access_1: rts #endif -#ifdef CONFIG_M5249 +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) .globl icache_enable icache_enable: /* @@ -426,13 +444,29 @@ icache_state_access_2: .globl icache_status icache_status: icache_state_access_3: - move.l icache_state, %d0 + move.l #(icache_state), %a0 + move.l (%a0), %d0 rts .data icache_state: .long 0 /* cache is diabled on inirialization */ + .globl dcache_enable +dcache_enable: + /* dummy function */ + rts + + .globl dcache_disable +dcache_disable: + /* dummy function */ + rts + + .globl dcache_status +dcache_status: + /* dummy function */ + rts + /*------------------------------------------------------------------------------*/ .globl version_string diff --git a/cpu/mcf532x/Makefile b/cpu/mcf532x/Makefile new file mode 100644 index 0000000..6790d90 --- /dev/null +++ b/cpu/mcf532x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = +COBJS = cpu.o speed.o cpu_init.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk new file mode 100644 index 0000000..ba324a8 --- /dev/null +++ b/cpu/mcf532x/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c new file mode 100644 index 0000000..520f5d6 --- /dev/null +++ b/cpu/mcf532x/cpu.c @@ -0,0 +1,119 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> + +#include <asm/immap.h> + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + wdp->cr = 0; + udelay(1000); + + /* enable watchdog, set timeout to 0 and wait */ + wdp->cr = WTM_WCR_EN; + while (1) ; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x54: + id = 5329; + break; + case 0x59: + id = 5328; + break; + case 0x61: + id = 5327; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000)); + } + + return 0; +}; + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + wdp->sr = 0x5555; /* Count register */ +} + +int watchdog_disable(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ + wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + + puts("WATCHDOG:disabled\n"); + return (0); +} + +int watchdog_init(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + u32 wdog_module = 0; + + /* set timeout and enable watchdog */ + wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module |= (wdog_module / 8192); + wdp->mr = wdog_module; + + wdp->cr = WTM_WCR_EN; + puts("WATCHDOG:enabled\n"); + + return (0); +} +#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c new file mode 100644 index 0000000..93086f7 --- /dev/null +++ b/cpu/mcf532x/cpu_init.c @@ -0,0 +1,141 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> + +#include <asm/immap.h> + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + wdog->cr = 0; +#endif + + scm1->mpr0 = 0x77777777; + scm2->pacra = 0; + scm2->pacrb = 0; + scm2->pacrc = 0; + scm2->pacrd = 0; + scm2->pacre = 0; + scm2->pacrf = 0; + scm2->pacrg = 0; + scm1->pacrh = 0; + + /* Port configuration */ + gpio->par_cs = 0; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + /* Latch chipselect */ + gpio->par_cs |= GPIO_PAR_CS1; + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + gpio->par_cs |= GPIO_PAR_CS2; + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + gpio->par_cs |= GPIO_PAR_CS3; + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + gpio->par_cs |= GPIO_PAR_CS4; + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + gpio->par_cs |= GPIO_PAR_CS5; + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + break; + case 2: + gpio->par_timer &= 0x0F; + gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); + break; + } +} diff --git a/cpu/mcf532x/interrupts.c b/cpu/mcf532x/interrupts.c new file mode 100644 index 0000000..ff50d7d --- /dev/null +++ b/cpu/mcf532x/interrupts.c @@ -0,0 +1,49 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include <common.h> +#include <asm/immap.h> + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrh0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c new file mode 100644 index 0000000..cf72609 --- /dev/null +++ b/cpu/mcf532x/speed.c @@ -0,0 +1,216 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#include <asm/immap.h> + +/* PLL min/max specifications */ +#define MAX_FVCO 500000 /* KHz */ +#define MAX_FSYS 80000 /* KHz */ +#define MIN_FSYS 58333 /* KHz */ +#define FREF 16000 /* KHz */ +#define MAX_MFD 135 /* Multiplier */ +#define MIN_MFD 88 /* Multiplier */ +#define BUSDIV 6 /* Divider */ +/* + * Low Power Divider specifications + */ +#define MIN_LPD (1 << 0) /* Divider (not encoded) */ +#define MAX_LPD (1 << 15) /* Divider (not encoded) */ +#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ + +/* + * Get the value of the current system clock + * + * Parameters: + * none + * + * Return Value: + * The current output system frequency + */ +int get_sys_clock(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + int divider; + + /* Test to see if device is in LIMP mode */ + if (ccm->misccr & CCM_MISCCR_LIMP) { + divider = ccm->cdr & CCM_CDR_LPDIV(0xF); + return (FREF / (2 << divider)); + } else { + return ((FREF * pll->pfdr) / (BUSDIV * 4)); + } +} + +/* + * Initialize the Low Power Divider circuit + * + * Parameters: + * div Desired system frequency divider + * + * Return Value: + * The resulting output system frequency + */ +int clock_limp(int div) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + u32 temp; + + /* Check bounds of divider */ + if (div < MIN_LPD) + div = MIN_LPD; + if (div > MAX_LPD) + div = MAX_LPD; + + /* Save of the current value of the SSIDIV so we don't overwrite the value */ + temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF)); + + /* Apply the divider to the system clock */ + ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); + + ccm->misccr |= CCM_MISCCR_LIMP; + + return (FREF / (3 * (1 << div))); +} + +/* + * Exit low power LIMP mode + * + * Parameters: + * div Desired system frequency divider + * + * Return Value: + * The resulting output system frequency + */ +int clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + int fout; + + /* Exit LIMP mode */ + ccm->misccr &= (~CCM_MISCCR_LIMP); + + /* Wait for PLL to lock */ + while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ; + + fout = get_sys_clock(); + + return fout; +} + +/* Initialize the PLL + * + * Parameters: + * fref PLL reference clock frequency in KHz + * fsys Desired PLL output frequency in KHz + * flags Operating parameters + * + * Return Value: + * The resulting output system frequency + */ +int clock_pll(int fsys, int flags) +{ + volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + int fref, temp, fout, mfd; + u32 i; + + fref = FREF; + + if (fsys == 0) { + /* Return current PLL output */ + mfd = pll->pfdr; + + return (fref * mfd / (BUSDIV * 4)); + } + + /* Check bounds of requested system clock */ + if (fsys > MAX_FSYS) + fsys = MAX_FSYS; + + if (fsys < MIN_FSYS) + fsys = MIN_FSYS; + + /* Multiplying by 100 when calculating the temp value, + and then dividing by 100 to calculate the mfd allows + for exact values without needing to include floating + point libraries. */ + temp = (100 * fsys) / fref; + mfd = (4 * BUSDIV * temp) / 100; + + /* Determine the output frequency for selected values */ + fout = ((fref * mfd) / (BUSDIV * 4)); + + /* + * Check to see if the SDRAM has already been initialized. + * If it has then the SDRAM needs to be put into self refresh + * mode before reprogramming the PLL. + */ + + /* + * Initialize the PLL to generate the new system clock frequency. + * The device must be put into LIMP mode to reprogram the PLL. + */ + + /* Enter LIMP mode */ + clock_limp(DEFAULT_LPD); + + /* Reprogram PLL for desired fsys */ + pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); + + pll->pfdr = mfd; + + /* Exit LIMP mode */ + clock_exit_limp(); + + /* + * Return the SDRAM to normal operation if it is in use. + */ + + /* software workaround for SDRAM opeartion after exiting LIMP mode errata */ + *sdram_workaround = CFG_SDRAM_BASE; + + /* wait for DQS logic to relock */ + for (i = 0; i < 0x200; i++) ; + + return fout; +} + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000; + gd->cpu_clk = (gd->bus_clk * 3); + return (0); +} diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S new file mode 100644 index 0000000..5cc1c87 --- /dev/null +++ b/cpu/mcf532x/start.S @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> + * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR0 + + /* invalidate and disable cache */ + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2 + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the + first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0 + movec %d0, %ACR0 /* Enable cache */ + + move.l #0x80000200, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable cache */ + clr.l %d0 /* Setup cache mask */ + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #0x81000200, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + rts + + .globl dcache_enable +dcache_enable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + /* No dcache, just a dummy function */ + .globl dcache_disable +dcache_disable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_status +dcache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile new file mode 100644 index 0000000..26ec298 --- /dev/null +++ b/cpu/mcf5445x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = start.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf5445x/config.mk b/cpu/mcf5445x/config.mk new file mode 100644 index 0000000..d0c72fb --- /dev/null +++ b/cpu/mcf5445x/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5407 -fPIC diff --git a/cpu/mcf5445x/cpu.c b/cpu/mcf5445x/cpu.c new file mode 100644 index 0000000..e601b89 --- /dev/null +++ b/cpu/mcf5445x/cpu.c @@ -0,0 +1,97 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> + +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + udelay(1000); + rcm->rcr |= RCM_RCR_SOFTRST; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x48: + id = 54455; + break; + case 0x49: + id = 54454; + break; + case 0x4a: + id = 54453; + break; + case 0x4b: + id = 54452; + break; + case 0x4d: + id = 54451; + break; + case 0x4f: + id = 54450; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000), + (int)(gd->flb_clk / 1000000)); +#ifdef CONFIG_PCI + printf(" PCI CLK %d Mhz INP CLK %d Mhz VCO CLK %d Mhz\n", + (int)(gd->pci_clk / 1000000), + (int)(gd->inp_clk / 1000000), + (int)(gd->vco_clk / 1000000)); +#else + printf(" INP CLK %d Mhz VCO CLK %d Mhz\n", + (int)(gd->inp_clk / 1000000), + (int)(gd->vco_clk / 1000000)); +#endif + } + + return 0; +} diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c new file mode 100644 index 0000000..6622eee --- /dev/null +++ b/cpu/mcf5445x/cpu_init.c @@ -0,0 +1,140 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> + +#include <asm/immap.h> +#include <asm/rtc.h> + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + + /* FlexBus */ + gpio->par_be = + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | + GPIO_PAR_BE_BE0_BE0; + gpio->par_fbctl = + GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | + GPIO_PAR_FBCTL_TS_TS; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + /* Latch chipselect */ + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFTMR + volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); + volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + u32 oscillator = CFG_RTC_OSCILLATOR; + + rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; +#endif + + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = + (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + break; + } +} diff --git a/cpu/mcf5445x/interrupts.c b/cpu/mcf5445x/interrupts.c new file mode 100644 index 0000000..9572a7b --- /dev/null +++ b/cpu/mcf5445x/interrupts.c @@ -0,0 +1,52 @@ +/* + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include <common.h> +#include <asm/immap.h> + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrh0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c new file mode 100644 index 0000000..8ace536 --- /dev/null +++ b/cpu/mcf5445x/pci.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI Configuration space access support + */ +#include <common.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/immap.h> + +#if defined(CONFIG_PCI) +/* System RAM mapped over PCI */ +#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define cfg_read(val, addr, type, op) *val = op((type)(addr)); +#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); + +#define PCI_OP(rw, size, type, op, mask) \ +int pci_##rw##_cfg_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 addr = 0; \ + u16 cfg_type = 0; \ + addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ + out_be32(hose->cfg_addr, addr); \ + __asm__ __volatile__("nop"); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + out_be32(hose->cfg_addr, addr & 0x7fffffff); \ + __asm__ __volatile__("nop"); \ + return 0; \ +} + +PCI_OP(read, byte, u8 *, in_8, 3) +PCI_OP(read, word, u16 *, in_le16, 2) +PCI_OP(write, byte, u8, out_8, 3) +PCI_OP(write, word, u16, out_le16, 2) +PCI_OP(write, dword, u32, out_le32, 0) + +int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, + int offset, u32 * val) +{ + u32 addr; + u32 tmpv; + u32 mask = 2; /* word access */ + /* Read lower 16 bits */ + addr = ((offset & 0xfc) | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + __asm__ __volatile__("nop"); + *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + __asm__ __volatile__("nop"); + + /* Read upper 16 bits */ + offset += 2; + addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + __asm__ __volatile__("nop"); + tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + __asm__ __volatile__("nop"); + + /* combine results into dword value */ + *val = (tmpv << 16) | *val; + + return 0; +} + +void pci_mcf5445x_init(struct pci_controller *hose) +{ + volatile pci_t *pci = (volatile pci_t *)MMAP_PCI; + volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u32 barEn = 0; + + pciarb->acr = 0x001f001f; + + /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, + PCIREQ2, PCIGNT2 */ + gpio->par_pci = + GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 | + GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | + GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0; + + pci->tcr1 |= PCI_TCR1_P; + + /* Initiator windows */ + pci->iw0btar = CFG_PCI_MEM_PHYS; + pci->iw1btar = CFG_PCI_IO_PHYS; + pci->iw2btar = CFG_PCI_CFG_PHYS; + + pci->iwcr = + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + + /* Enable bus master and mem access */ + pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M; + + /* Cache line size and master latency */ + pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF); + pci->cr2 = 0; + +#ifdef CFG_PCI_BAR0 + pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); + pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B0E; +#endif +#ifdef CFG_PCI_BAR1 + pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); + pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B1E; +#endif +#ifdef CFG_PCI_BAR2 + pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2); + pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B2E; +#endif +#ifdef CFG_PCI_BAR3 + pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3); + pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B3E; +#endif +#ifdef CFG_PCI_BAR4 + pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4); + pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B4E; +#endif +#ifdef CFG_PCI_BAR5 + pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5); + pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B5E; +#endif + + pci->tcr2 = barEn; + + /* Deassert reset bit */ + pci->gscr &= ~PCI_GSCR_PR; + udelay(1000); + + /* Enable PCI bus master support */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, + CFG_PCI_IO_SIZE, PCI_REGION_IO); + + pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS, + CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 3; + + hose->cfg_addr = &(pci->car); + hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS; + + pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, + pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, + pci_write_cfg_dword); + + /* Hose scan */ + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCI */ diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c new file mode 100644 index 0000000..967becf --- /dev/null +++ b/cpu/mcf5445x/speed.c @@ -0,0 +1,186 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Low Power Divider specifications + */ +#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ +#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ + +#define CLOCK_PLL_FVCO_MAX 540000000 +#define CLOCK_PLL_FVCO_MIN 300000000 + +#define CLOCK_PLL_FSYS_MAX 266666666 +#define CLOCK_PLL_FSYS_MIN 100000000 +#define MHZ 1000000 + +void clock_enter_limp(int lpdiv) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + int i, j; + + /* Check bounds of divider */ + if (lpdiv < CLOCK_LPD_MIN) + lpdiv = CLOCK_LPD_MIN; + if (lpdiv > CLOCK_LPD_MAX) + lpdiv = CLOCK_LPD_MAX; + + /* Round divider down to nearest power of two */ + for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; + + /* Apply the divider to the system clock */ + ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + + /* Enable Limp Mode */ + ccm->misccr |= CCM_MISCCR_LIMP; +} + +/* + * brief Exit Limp mode + * warning The PLL should be set and locked prior to exiting Limp mode + */ +void clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + + /* Exit Limp mode */ + ccm->misccr &= ~CCM_MISCCR_LIMP; + + /* Wait for the PLL to lock */ + while (!(pll->psr & PLL_PSR_LOCK)) ; +} + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3); + volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14); + int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; + int pllmult_pci[] = { 12, 6, 16, 8 }; + int vco, bPci, temp, fbtemp, pcrvalue; + int *pPllmult = NULL; + u16 fbpll_mask; + u8 cpldmode; + + /* To determine PCI is present or not */ + if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || + ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { + pPllmult = &pllmult_pci[0]; + fbpll_mask = 3; + bPci = 1; + } else { + pPllmult = &pllmult_nopci[0]; + fbpll_mask = 7; +#ifdef CONFIG_PCI + gd->pci_clk = 0; +#endif + bPci = 0; + } + +#ifdef CONFIG_M54455EVB + /* Temporary place here, belongs in board/freescale/... */ + /* Temporary read from CCR- fixed fb issue, must be the same clock + as pci or input clock, causing cpld/fpga read inconsistancy */ + fbtemp = pPllmult[ccm->ccr & fbpll_mask]; + + /* Break down into small pieces, code still in flex bus */ + pcrvalue = pll->pcr & 0xFFFFF0FF; + temp = fbtemp - 1; + pcrvalue |= PLL_PCR_OUTDIV3(temp); + + pll->pcr = pcrvalue; + + cpldmode = *cpld & 0x03; + if (cpldmode == 0) { + /* RCON mode */ + vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC; + + if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { + /* invaild range, re-set in PCR */ + int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + int i, j, bus; + + j = (pll->pcr & 0xFF000000) >> 24; + for (i = j; i < 0xFF; i++) { + vco = i * CFG_INPUT_CLKSRC; + if (vco >= CLOCK_PLL_FVCO_MIN) { + bus = vco / temp; + if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) + continue; + else + break; + } + } + pcrvalue = pll->pcr & 0x00FF00FF; + fbtemp = ((i - 1) << 8) | ((i - 1) << 12); + pcrvalue |= ((i << 24) | fbtemp); + + pll->pcr = pcrvalue; + } + gd->vco_clk = vco; /* Vco clock */ + } else if (cpldmode == 2) { + /* Normal mode */ + vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC; + gd->vco_clk = vco; /* Vco clock */ + } else if (cpldmode == 3) { + /* serial mode */ + } +#endif /* CONFIG_M54455EVB */ + + if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + /* Limp mode */ + } else { + gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */ + + temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + gd->cpu_clk = vco / temp; /* cpu clock */ + + temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + gd->bus_clk = vco / temp; /* bus clock */ + + temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; + gd->flb_clk = vco / temp; /* FlexBus clock */ + +#ifdef CONFIG_PCI + if (bPci) { + temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; + gd->pci_clk = vco / temp; /* PCI clock */ + } +#endif + } + + return (0); +} diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S new file mode 100644 index 0000000..cd989ab --- /dev/null +++ b/cpu/mcf5445x/start.S @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> + * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* last three long word reserved for cache status */ +#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) +#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) +#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR0 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CACR_STATUS), %a1 /* CACR */ + move.l #(ICACHE_STATUS), %a2 /* icache */ + move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) + + /* invalidate and disable cache */ + move.l #0x01004100, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + + /* set stackpointer to end of internal ram to get some stackspace for + the first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d1 + + move.l #0x00040100, %d0 /* Invalidate icache */ + or.l %d1, %d0 + movec %d0, %CACR + + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */ + movec %d0, %ACR2 + + or.l #0x00088400, %d1 /* Enable bcache and icache */ + movec %d1, %CACR + + move.l #(ICACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + and.l #0xFFF77BFF, %d0 + or.l #0x00040100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Invalidate icache */ + clr.l %d0 + movec %d0, %ACR2 + movec %d0, %ACR3 + + move.l #(ICACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(ICACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + or.l #0x00040100, %d0 /* Invalidate icache */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_enable +dcache_enable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d1 + + move.l #0x01000000, %d0 + or.l %d1, %d0 + movec %d0, %CACR /* Invalidate dcache */ + + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 + movec %d0, %ACR0 + move.l #0, %d0 + movec %d0, %ACR1 + + or.l #0x80000000, %d1 /* Enable bcache and icache */ + movec %d1, %CACR + + move.l #(DCACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_disable +dcache_disable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + and.l #0x7FFFFFFF, %d0 + or.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable dcache */ + clr.l %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(DCACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_invalid +dcache_invalid: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + or.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_status +dcache_status: + move.l #(DCACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk index 8a07c5a..3259d53 100644 --- a/cpu/mpc512x/config.mk +++ b/cpu/mpc512x/config.mk @@ -19,7 +19,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index 3c142a9..8104576 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -32,6 +32,9 @@ int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * re int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); +static uchar rx_buff[FEC_MAX_PKT_SIZE]; +static int rx_buff_idx = 0; + /********************************************************************/ #if (DEBUG & 0x2) static void mpc512x_fec_phydump (char *devname) @@ -235,7 +238,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) fec->eth->op_pause = 0x00010020; /* Frame length=1518; MII mode */ - fec->eth->r_cntrl = 0x05ee000c; + fec->eth->r_cntrl = 0x05ee0024; /* Half-duplex, heartbeat disabled */ fec->eth->x_cntrl = 0x00000000; @@ -520,8 +523,7 @@ static int mpc512x_fec_recv (struct eth_device *dev) mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex]; unsigned long ievent; - int frame_length, len = 0; - uchar buff[FEC_MAX_PKT_SIZE]; + int frame_length = 0; #if (DEBUG & 0x1) printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex); @@ -555,31 +557,37 @@ static int mpc512x_fec_recv (struct eth_device *dev) } if (!(pRbd->status & FEC_RBD_EMPTY)) { - if ((pRbd->status & FEC_RBD_LAST) && - !(pRbd->status & FEC_RBD_ERR) && + if (!(pRbd->status & FEC_RBD_ERR) && ((pRbd->dataLength - 4) > 14)) { /* * Get buffer size */ - frame_length = pRbd->dataLength - 4; - + if (pRbd->status & FEC_RBD_LAST) + frame_length = pRbd->dataLength - 4; + else + frame_length = pRbd->dataLength; #if (DEBUG & 0x20) { int i; - printf ("recv data hdr:"); + printf ("recv data length 0x%08x data hdr: ", + pRbd->dataLength); for (i = 0; i < 14; i++) printf ("%x ", *((uint8*)pRbd->dataPointer + i)); printf("\n"); } #endif - /* * Fill the buffer and pass it to upper layers */ - memcpy (buff, (void*)pRbd->dataPointer, frame_length); - NetReceive ((uchar*)buff, frame_length); - len = frame_length; + memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer, + frame_length - rx_buff_idx); + rx_buff_idx = frame_length; + + if (pRbd->status & FEC_RBD_LAST) { + NetReceive ((uchar*)rx_buff, frame_length); + rx_buff_idx = 0; + } } /* @@ -590,7 +598,7 @@ static int mpc512x_fec_recv (struct eth_device *dev) /* Try to fill Buffer Descriptors */ fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ - return len; + return frame_length; } /********************************************************************/ diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 1eac2bb..7f16b92 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -29,10 +29,12 @@ #include <watchdog.h> #include <command.h> #include <mpc5xxx.h> +#include <asm/io.h> #include <asm/processor.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <libfdt_env.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -111,29 +113,43 @@ unsigned long get_tbclk (void) /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_OF_FLAT_TREE -void -ft_cpu_setup(void *blob, bd_t *bd) +#ifdef CONFIG_OF_LIBFDT +static void do_fixup(void *fdt, const char *node, const char *prop, + const void *val, int len, int create) { - u32 *p; - int len; - - /* Core XLB bus frequency */ - p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(bd->bi_busfreq); - - /* SOC peripherals use the IPB bus frequency */ - p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(bd->bi_ipbfreq); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); +#if defined(DEBUG) + int i; + debug("Updating property '%s/%s' = ", node, prop); + for (i = 0; i < len; i++) + debug(" %.2x", *(u8*)(val+i)); + debug("\n"); +#endif + int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create); + if (rc) + printf("Unable to update property %s:%s, err=%s\n", + node, prop, fdt_strerror(rc)); +} + +static void do_fixup_u32(void *fdt, const char *node, const char *prop, + u32 val, int create) +{ + val = cpu_to_fdt32(val); + do_fixup(fdt, node, prop, &val, sizeof(val), create); +} + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4; + char * cpu_path = "/cpus/" OF_CPU; + char * eth_path = "/" OF_SOC "/ethernet@3000"; + + do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); + do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); + do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1); + do_fixup_u32(blob, "/" OF_SOC, "system-frequency", + bd->bi_busfreq*div, 1); + do_fixup(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0); + do_fixup(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0); } #endif diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index 087ddac..df5b4ac 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -54,11 +54,19 @@ int ide_preinit (void) /* All sample codes do that... */ *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0; +#if defined(CONFIG_UC101) + /* Configure and reset host */ + *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = + MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; + udelay (10); + *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0; +#else /* Configure and reset host */ *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY | MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; udelay (10); *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY; +#endif /* Disable prefetch on Commbus */ psdma->PtdCntrl |= 1; diff --git a/cpu/mpc5xxx/usb.c b/cpu/mpc5xxx/usb.c index ce709fc..ed467ab 100644 --- a/cpu/mpc5xxx/usb.c +++ b/cpu/mpc5xxx/usb.c @@ -27,7 +27,7 @@ #include <mpc5xxx.h> -int usb_cpu_init() +int usb_cpu_init(void) { /* Set the USB Clock */ *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; @@ -41,12 +41,12 @@ int usb_cpu_init() return 0; } -int usb_cpu_stop() +int usb_cpu_stop(void) { return 0; } -int usb_cpu_init_fail() +int usb_cpu_init_fail(void) { return 0; } diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index adf8083..e634f0a 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -35,12 +35,10 @@ #include <ft_build.h> #elif defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#include <libfdt_env.h> #endif DECLARE_GLOBAL_DATA_PTR; - int checkcpu(void) { volatile immap_t *immr; @@ -333,9 +331,7 @@ void watchdog_reset (void) */ static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd) { - /* - * Fix it up if it exists, don't create it if it doesn't exist. - */ + /* Fix it up if it exists, don't create it if it doesn't exist */ if (fdt_get_property(blob, nodeoffset, name, 0)) { return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6); } @@ -345,9 +341,7 @@ static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd) /* second onboard ethernet port */ static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd) { - /* - * Fix it up if it exists, don't create it if it doesn't exist. - */ + /* Fix it up if it exists, don't create it if it doesn't exist */ if (fdt_get_property(blob, nodeoffset, name, 0)) { return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6); } @@ -358,9 +352,7 @@ static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd) /* third onboard ethernet port */ static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd) { - /* - * Fix it up if it exists, don't create it if it doesn't exist. - */ + /* Fix it up if it exists, don't create it if it doesn't exist */ if (fdt_get_property(blob, nodeoffset, name, 0)) { return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6); } @@ -371,9 +363,7 @@ static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd) /* fourth onboard ethernet port */ static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd) { - /* - * Fix it up if it exists, don't create it if it doesn't exist. - */ + /* Fix it up if it exists, don't create it if it doesn't exist */ if (fdt_get_property(blob, nodeoffset, name, 0)) { return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6); } @@ -384,9 +374,7 @@ static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd) static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) { u32 tmp; - /* - * Create or update the property. - */ + /* Create or update the property */ tmp = cpu_to_be32(bd->bi_busfreq); return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); } @@ -394,14 +382,38 @@ static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *b static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) { u32 tmp; - /* - * Create or update the property. - */ + /* Create or update the property */ tmp = cpu_to_be32(OF_TBCLK); return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); } +static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) +{ + u32 tmp; + /* Create or update the property */ + tmp = cpu_to_be32(gd->core_clk); + return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); +} + +#ifdef CONFIG_QE +static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) +{ + u32 tmp; + /* Create or update the property */ + tmp = cpu_to_be32(gd->qe_clk); + return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); +} + +static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) +{ + u32 tmp; + /* Create or update the property */ + tmp = cpu_to_be32(gd->brg_clk); + return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); +} +#endif + /* * Fixups to the fdt. */ @@ -420,6 +432,10 @@ static const struct { }, { "/cpus/" OF_CPU, "clock-frequency", + fdt_set_clockfreq + }, + { "/" OF_SOC, + "bus-frequency", fdt_set_busfreq }, { "/" OF_SOC "/serial@4500", @@ -450,6 +466,15 @@ static const struct { fdt_set_eth1 }, #endif +#ifdef CONFIG_QE + { "/" OF_QE, + "brg-frequency", + fdt_set_qe_brgfreq + }, + { "/" OF_QE, + "bus-frequency", + fdt_set_qe_busfreq + }, #ifdef CONFIG_UEC_ETH1 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */ { "/" OF_QE "/ucc@2000", @@ -481,7 +506,7 @@ static const struct { "local-mac-address", fdt_set_eth1 }, -#elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */ +#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */ { "/" OF_QE "/ucc@3200", "mac-address", fdt_set_eth1 @@ -492,14 +517,16 @@ static const struct { }, #endif #endif /* CONFIG_UEC_ETH2 */ +#endif /* CONFIG_QE */ }; void ft_cpu_setup(void *blob, bd_t *bd) { - int nodeoffset; - int err; - int j; + int nodeoffset; + int err; + int j; + int tmp[2]; for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) { nodeoffset = fdt_find_node_by_path(blob, fixup_props[j].node); @@ -508,15 +535,29 @@ ft_cpu_setup(void *blob, bd_t *bd) fixup_props[j].prop, bd); if (err < 0) debug("Problem setting %s = %s: %s\n", - fixup_props[j].node, - fixup_props[j].prop, - fdt_strerror(err)); + fixup_props[j].node, fixup_props[j].prop, + fdt_strerror(err)); } else { debug("Couldn't find %s: %s\n", - fixup_props[j].node, - fdt_strerror(nodeoffset)); + fixup_props[j].node, fdt_strerror(nodeoffset)); } } + + /* update, or add and update /memory node */ + nodeoffset = fdt_find_node_by_path(blob, "/memory"); + if (nodeoffset < 0) { + nodeoffset = fdt_add_subnode(blob, 0, "memory"); + if (nodeoffset < 0) + debug("failed to add /memory node: %s\n", + fdt_strerror(nodeoffset)); + } + if (nodeoffset >= 0) { + fdt_setprop(blob, nodeoffset, "device_type", + "memory", sizeof("memory")); + tmp[0] = cpu_to_be32(bd->bi_memstart); + tmp[1] = cpu_to_be32(bd->bi_memsize); + fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); + } } #elif defined(CONFIG_OF_FLAT_TREE) void diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 2298218..5675afe 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -28,7 +28,6 @@ #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#include <libfdt_env.h> #elif defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> #endif @@ -184,7 +183,12 @@ void ft_pci_setup(void *blob, bd_t *bd) if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(pci_hose[0].first_busno); tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); } if (pci_num_buses < 2) @@ -194,7 +198,12 @@ void ft_pci_setup(void *blob, bd_t *bd) if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(pci_hose[0].first_busno); tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); } } #elif CONFIG_OF_FLAT_TREE diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 54f0c83..ee2d038 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -34,6 +34,30 @@ #include <asm/mmu.h> #include <spd_sdram.h> +void board_add_ram_info(int use_default) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ddr83xx_t *ddr = &immap->ddr; + + printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) + >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); + + if (ddr->sdram_cfg & SDRAM_CFG_32_BE) + puts(", 32-bit"); + else + puts(", 64-bit"); + + if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) + puts(", ECC on)"); + else + puts(", ECC off)"); + +#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE) + puts("\nSDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); +#endif +} + #ifdef CONFIG_SPD_EEPROM DECLARE_GLOBAL_DATA_PTR; @@ -109,7 +133,7 @@ long int spd_sdram() unsigned int n_ranks; unsigned int odt_rd_cfg, odt_wr_cfg; unsigned char twr_clk, twtr_clk; - unsigned char sdram_type; + unsigned int sdram_type; unsigned int memsize; unsigned int law_size; unsigned char caslat, caslat_ctrl; @@ -137,7 +161,7 @@ long int spd_sdram() #endif /* Check the memory type */ if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { - printf("DDR: Module mem type is %02X\n", spd.mem_type); + debug("DDR: Module mem type is %02X\n", spd.mem_type); return 0; } @@ -578,17 +602,17 @@ long int spd_sdram() burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ else burstlen = 0x02; /* 32 bit data bus, burst len is 4 */ - printf("\n DDR DIMM: data bus width is 32 bit"); + debug("\n DDR DIMM: data bus width is 32 bit"); } else { burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */ - printf("\n DDR DIMM: data bus width is 64 bit"); + debug("\n DDR DIMM: data bus width is 64 bit"); } /* Is this an ECC DDR chip? */ if (spd.config == 0x02) - printf(" with ECC\n"); + debug(" with ECC\n"); else - printf(" without ECC\n"); + debug(" without ECC\n"); /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, Burst type is sequential @@ -718,26 +742,26 @@ long int spd_sdram() * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) */ if (spd.mem_type == SPD_MEMTYPE_DDR) - sdram_type = 2; + sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1; else - sdram_type = 3; + sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2; sdram_cfg = (0 - | (1 << 31) /* DDR enable */ - | (1 << 30) /* Self refresh */ - | (sdram_type << 24) /* SDRAM type */ + | SDRAM_CFG_MEM_EN /* DDR enable */ + | SDRAM_CFG_SREN /* Self refresh */ + | sdram_type /* SDRAM type */ ); /* sdram_cfg[3] = RD_EN - registered DIMM enable */ if (spd.mod_attr & 0x02) - sdram_cfg |= 0x10000000; + sdram_cfg |= SDRAM_CFG_RD_EN; /* The DIMM is 32bit width */ if (spd.dataw_lsb == 0x20) { if (spd.mem_type == SPD_MEMTYPE_DDR) - sdram_cfg |= 0x000C0000; + sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE; if (spd.mem_type == SPD_MEMTYPE_DDR2) - sdram_cfg |= 0x00080000; + sdram_cfg |= SDRAM_CFG_32_BE; } ddrc_ecc_enable = 0; @@ -758,7 +782,7 @@ long int spd_sdram() debug("DDR:err_disable=0x%08x\n", ddr->err_disable); debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); #endif - printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); + debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); #if defined(CONFIG_DDR_2T_TIMING) /* diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index bf30616..cba57fa 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -351,6 +351,7 @@ int get_clocks(void) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif + gd->pci_clk = pci_sync_in; gd->cpu_clk = gd->core_clk; gd->bus_clk = gd->csb_clk; return 0; diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 7b99610..79ad20c 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -247,7 +247,7 @@ int cpu_init_r(void) switch (cache_ctl & 0x30000000) { case 0x20000000: if (ver == SVR_8548 || ver == SVR_8548_E || - ver == SVR_8544) { + ver == SVR_8544 || ver == SVR_8568_E) { printf ("L2 cache 512KB:"); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 2837929..282e7a1 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -443,7 +443,7 @@ void pci_init_board(void) static struct pci_controller ppc440_hose = {0}; -void pci_440_init (struct pci_controller *hose) +int pci_440_init (struct pci_controller *hose) { int reg_num = 0; @@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose) if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } #elif defined(CONFIG_440GP) unsigned long strap; @@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose) if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } #endif #endif /* CONFIG_DISABLE_PISE_TEST */ @@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose) * PCI controller init *--------------------------------------------------------------------------*/ hose->first_busno = 0; - hose->last_busno = 0xff; + hose->last_busno = 0; /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, @@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose) if (pci_pre_init (hose) == 0) { printf("PCI: Board-specific initialization failed.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } pci_register_hose( hose ); @@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose) #endif hose->last_busno = pci_hose_scan(hose); } + return hose->last_busno; } void pci_init_board(void) { - pci_440_init (&ppc440_hose); + int busno; + + busno = pci_440_init (&ppc440_hose); #if defined(CONFIG_440SPE) - pcie_setup_hoses(); + pcie_setup_hoses(busno + 1); #endif } diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index bf68cc1..158f1c5 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -40,73 +40,126 @@ enum { LNKW_X8 = 0x8 }; -static inline int pcie_in_8(const volatile unsigned char __iomem *addr) +static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) { - int ret; - - PCIE_IN(lbzx, ret, addr); + u8 *base = (u8*)hose->cfg_data; + + /* use local configuration space for the first bus */ + if (PCI_BUS(devfn) == 0) { + if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE) + base = (u8*)CFG_PCIE0_XCFGBASE; + if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) + base = (u8*)CFG_PCIE1_XCFGBASE; + if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) + base = (u8*)CFG_PCIE2_XCFGBASE; + } - return ret; + return base; } -static inline int pcie_in_le16(const volatile unsigned short __iomem *addr) +static void pcie_dmer_disable(void) { - int ret; - - PCIE_IN(lhbrx, ret, addr) - - return ret; + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); } -static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr) +static void pcie_dmer_enable(void) { - unsigned ret; - - PCIE_IN(lwbrx, ret, addr); - - return ret; + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); } - static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 *val) { + u8 *address; *val = 0; + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + /* - * 440SPE implements only one function per port + * NOTICE: configuration space ranges are currenlty mapped only for + * the first 16 buses, so such limit must be imposed. In case more + * buses are required the TLB settings in board/amcc/<board>/init.S + * need to be altered accordingly (one bus takes 1 MB of memory space). */ - if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + if (PCI_BUS(devfn) >= 16) return 0; - devfn = PCI_BDF(0,0,0); + /* + * Only single device/single function is supported for the primary and + * secondary buses of the 440SPe host bridge. + */ + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); offset += devfn << 4; + /* + * Reading from configuration space of non-existing device can + * generate transaction errors. For the read duration we suppress + * assertion of machine check exceptions to avoid those. + */ + pcie_dmer_disable (); + switch (len) { case 1: - *val = pcie_in_8(hose->cfg_data + offset); + *val = in_8(hose->cfg_data + offset); break; case 2: - *val = pcie_in_le16((u16 *)(hose->cfg_data + offset)); + *val = in_le16((u16 *)(hose->cfg_data + offset)); break; default: - *val = pcie_in_le32((u32*)(hose->cfg_data + offset)); + *val = in_le32((u32*)(hose->cfg_data + offset)); break; } + + pcie_dmer_enable (); + return 0; } static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 val) { + u8 *address; + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + /* - * 440SPE implements only one function per port + * Same constraints as in pcie_read_config(). */ - if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + if (PCI_BUS(devfn) >= 16) return 0; - devfn = PCI_BDF(0,0,0); + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); offset += devfn << 4; + /* + * Suppress MCK exceptions, similar to pcie_read_config() + */ + pcie_dmer_disable (); + switch (len) { case 1: out_8(hose->cfg_data + offset, val); @@ -118,6 +171,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, out_le32((u32 *)(hose->cfg_data + offset), val); break; } + + pcie_dmer_enable (); + return 0; } @@ -126,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u u32 v; int rv; - rv = pcie_read_config(hose, dev, offset, 1, &v); + rv = pcie_read_config(hose, dev, offset, 1, &v); *val = (u8)v; return rv; } @@ -783,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) volatile void *rmbase = NULL; pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); switch (port) { case 0: @@ -811,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) /* * Set bus numbers on our root port */ - if (ppc440spe_revB()) { - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); - } else { - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); - } + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); /* * Set up outbound translation to hose->mem_space from PLB @@ -875,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); printf("PCIE:%d successfully set as rootpoint\n",port); + + /* Set Device and Vendor Id */ + switch (port) { + case 0: + out_le16(mbase + 0x200, 0xaaa0); + out_le16(mbase + 0x202, 0xbed0); + break; + case 1: + out_le16(mbase + 0x200, 0xaaa1); + out_le16(mbase + 0x202, 0xbed1); + break; + case 2: + out_le16(mbase + 0x200, 0xaaa2); + out_le16(mbase + 0x202, 0xbed2); + break; + default: + out_le16(mbase + 0x200, 0xaaa3); + out_le16(mbase + 0x202, 0xbed3); + } + + /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ + out_le32(mbase + 0x208, 0x06040001); + } int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) @@ -952,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ attempts = 10; diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h index eb7cecf..38745eb 100644 --- a/cpu/ppc4xx/440spe_pcie.h +++ b/cpu/ppc4xx/440spe_pcie.h @@ -38,6 +38,7 @@ #define DCRN_PEGPL_REGBAL(base) (base + 0x13) #define DCRN_PEGPL_REGMSK(base) (base + 0x14) #define DCRN_PEGPL_SPECIAL(base) (base + 0x15) +#define DCRN_PEGPL_CFG(base) (base + 0x16) /* * System DCRs (SDRs) @@ -161,20 +162,7 @@ mtdcr(DCRN_SDR0_CFGADDR, offset); \ mtdcr(DCRN_SDR0_CFGDATA,data);}) -#define PCIE_IN(opcode, ret, addr) \ - __asm__ __volatile__( \ - "sync\n" \ - #opcode " %0,0,%1\n" \ - "1: twi 0,%0,0\n" \ - "isync\n" \ - "b 3f\n" \ - "2: li %0,-1\n" \ - "3:\n" \ - ".section __ex_table,\"a\"\n" \ - ".balign 4\n" \ - ".long 1b,2b\n" \ - ".previous\n" \ - : "=r" (ret) : "r" (addr), "m" (*addr)); +#define GPL_DMER_MASK_DISA 0x02000000 int ppc440spe_init_pcie(void); int ppc440spe_init_pcie_rootport(int port); diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 18b90ba..67ba5bd 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -621,7 +621,6 @@ static void get_spd_info(unsigned long *dimm_populated, } } -#ifdef CONFIG_ADD_RAM_INFO void board_add_ram_info(int use_default) { PPC440_SYS_INFO board_cfg; @@ -642,7 +641,6 @@ void board_add_ram_info(int use_default) val = (val & SDRAM_MMODE_DCL_MASK) >> 4; printf(", CL%d)", val); } -#endif /*------------------------------------------------------------------ * For the memory DIMMs installed, this routine verifies that they diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index f5365cb..38b6f89 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -151,12 +151,6 @@ MachineCheckException(struct pt_regs *regs) int uncorr_ecc = 0; #endif - /* Probing PCI(E) using config cycles may cause this exception - * when a device is not present. To gracefully recover in such - * scenarios config read/write routines need to be instrumented in - * order to return via fixup handler. For examples refer to - * pcie_in_8(), pcie_in_le16() and pcie_in_le32() - */ if ((fixup = search_exception_table(regs->nip)) != 0) { regs->nip = fixup; val = mfspr(MCSR); diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c index cb3a478..51e7f65 100644 --- a/cpu/pxa/serial.c +++ b/cpu/pxa/serial.c @@ -30,11 +30,28 @@ #include <common.h> #include <watchdog.h> +#include <serial.h> #include <asm/arch/pxa-regs.h> DECLARE_GLOBAL_DATA_PTR; -void serial_setbrg (void) +#define FFUART 0 +#define BTUART 1 +#define STUART 2 + +#ifndef CONFIG_SERIAL_MULTI +#if defined (CONFIG_FFUART) +#define UART_INDEX FFUART +#elif defined (CONFIG_BTUART) +#define UART_INDEX BTUART +#elif defined (CONFIG_STUART) +#define UART_INDEX STUART +#else +#error "Bad: you didn't configure serial ..." +#endif +#endif + +void pxa_setbrg_dev (unsigned int uart_index) { unsigned int quot = 0; @@ -53,63 +70,68 @@ void serial_setbrg (void) else hang (); -#ifdef CONFIG_FFUART + switch (uart_index) { + case FFUART: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_22_FFUART; + CKENA |= CKENA_22_FFUART; #else - CKEN |= CKEN6_FFUART; + CKEN |= CKEN6_FFUART; #endif /* CONFIG_CPU_MONAHANS */ - FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ + FFIER = 0; /* Disable for now */ + FFFCR = 0; /* No fifos enabled */ - /* set baud rate */ - FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - FFDLL = quot & 0xff; - FFDLH = quot >> 8; - FFLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; + FFDLL = quot & 0xff; + FFDLH = quot >> 8; + FFLCR = LCR_WLS0 | LCR_WLS1; - FFIER = IER_UUE; /* Enable FFUART */ + FFIER = IER_UUE; /* Enable FFUART */ + break; -#elif defined(CONFIG_BTUART) + case BTUART: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_21_BTUART; + CKENA |= CKENA_21_BTUART; #else - CKEN |= CKEN7_BTUART; + CKEN |= CKEN7_BTUART; #endif /* CONFIG_CPU_MONAHANS */ - BTIER = 0; - BTFCR = 0; + BTIER = 0; + BTFCR = 0; - /* set baud rate */ - BTLCR = LCR_DLAB; - BTDLL = quot & 0xff; - BTDLH = quot >> 8; - BTLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + BTLCR = LCR_DLAB; + BTDLL = quot & 0xff; + BTDLH = quot >> 8; + BTLCR = LCR_WLS0 | LCR_WLS1; - BTIER = IER_UUE; /* Enable BFUART */ + BTIER = IER_UUE; /* Enable BFUART */ -#elif defined(CONFIG_STUART) + break; + + case STUART: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_23_STUART; + CKENA |= CKENA_23_STUART; #else - CKEN |= CKEN5_STUART; + CKEN |= CKEN5_STUART; #endif /* CONFIG_CPU_MONAHANS */ - STIER = 0; - STFCR = 0; + STIER = 0; + STFCR = 0; - /* set baud rate */ - STLCR = LCR_DLAB; - STDLL = quot & 0xff; - STDLH = quot >> 8; - STLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + STLCR = LCR_DLAB; + STDLL = quot & 0xff; + STDLH = quot >> 8; + STLCR = LCR_WLS0 | LCR_WLS1; - STIER = IER_UUE; /* Enable STUART */ + STIER = IER_UUE; /* Enable STUART */ + break; -#else -#error "Bad: you didn't configure serial ..." -#endif + default: + hang(); + } } @@ -118,9 +140,9 @@ void serial_setbrg (void) * are always 8 data bits, no parity, 1 stop bit, no start bits. * */ -int serial_init (void) +int pxa_init_dev (unsigned int uart_index) { - serial_setbrg (); + pxa_setbrg_dev (uart_index); return (0); } @@ -129,26 +151,32 @@ int serial_init (void) /* * Output a single byte to the serial port. */ -void serial_putc (const char c) -{ -#ifdef CONFIG_FFUART - /* wait for room in the tx FIFO on FFUART */ - while ((FFLSR & LSR_TEMT) == 0) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - FFTHR = c; -#elif defined(CONFIG_BTUART) - while ((BTLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - BTTHR = c; -#elif defined(CONFIG_STUART) - while ((STLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - STTHR = c; -#endif +void pxa_putc_dev (unsigned int uart_index,const char c) +{ + switch (uart_index) { + case FFUART: + /* wait for room in the tx FIFO on FFUART */ + while ((FFLSR & LSR_TEMT) == 0) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + FFTHR = c; + break; + + case BTUART: + while ((BTLSR & LSR_TEMT ) == 0 ) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + BTTHR = c; + break; + + case STUART: + while ((STLSR & LSR_TEMT ) == 0 ) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + STTHR = c; + break; + } /* If \n, also do \r */ if (c == '\n') - serial_putc ('\r'); + pxa_putc_dev (uart_index,'\r'); } /* @@ -156,15 +184,17 @@ void serial_putc (const char c) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int serial_tstc (void) -{ -#ifdef CONFIG_FFUART - return FFLSR & LSR_DR; -#elif defined(CONFIG_BTUART) - return BTLSR & LSR_DR; -#elif defined(CONFIG_STUART) - return STLSR & LSR_DR; -#endif +int pxa_tstc_dev (unsigned int uart_index) +{ + switch (uart_index) { + case FFUART: + return FFLSR & LSR_DR; + case BTUART: + return BTLSR & LSR_DR; + case STUART: + return STLSR & LSR_DR; + } + return -1; } /* @@ -172,27 +202,184 @@ int serial_tstc (void) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int serial_getc (void) -{ -#ifdef CONFIG_FFUART - while (!(FFLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) FFRBR & 0xff; -#elif defined(CONFIG_BTUART) - while (!(BTLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) BTRBR & 0xff; -#elif defined(CONFIG_STUART) - while (!(STLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) STRBR & 0xff; -#endif +int pxa_getc_dev (unsigned int uart_index) +{ + switch (uart_index) { + case FFUART: + while (!(FFLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) FFRBR & 0xff; + + case BTUART: + while (!(BTLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) BTRBR & 0xff; + case STUART: + while (!(STLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) STRBR & 0xff; + } + return -1; } void -serial_puts (const char *s) +pxa_puts_dev (unsigned int uart_index,const char *s) { while (*s) { - serial_putc (*s++); + pxa_putc_dev (uart_index,*s++); } } + +#if defined (CONFIG_FFUART) +static int ffuart_init(void) +{ + return pxa_init_dev(FFUART); +} + +static void ffuart_setbrg(void) +{ + return pxa_setbrg_dev(FFUART); +} + +static void ffuart_putc(const char c) +{ + return pxa_putc_dev(FFUART,c); +} + +static void ffuart_puts(const char *s) +{ + return pxa_puts_dev(FFUART,s); +} + +static int ffuart_getc(void) +{ + return pxa_getc_dev(FFUART); +} + +static int ffuart_tstc(void) +{ + return pxa_tstc_dev(FFUART); +} + +struct serial_device serial_ffuart_device = +{ + "serial_ffuart", + "PXA", + ffuart_init, + ffuart_setbrg, + ffuart_getc, + ffuart_tstc, + ffuart_putc, + ffuart_puts, +}; +#endif + +#if defined (CONFIG_BTUART) +static int btuart_init(void) +{ + return pxa_init_dev(BTUART); +} + +static void btuart_setbrg(void) +{ + return pxa_setbrg_dev(BTUART); +} + +static void btuart_putc(const char c) +{ + return pxa_putc_dev(BTUART,c); +} + +static void btuart_puts(const char *s) +{ + return pxa_puts_dev(BTUART,s); +} + +static int btuart_getc(void) +{ + return pxa_getc_dev(BTUART); +} + +static int btuart_tstc(void) +{ + return pxa_tstc_dev(BTUART); +} + +struct serial_device serial_btuart_device = +{ + "serial_btuart", + "PXA", + btuart_init, + btuart_setbrg, + btuart_getc, + btuart_tstc, + btuart_putc, + btuart_puts, +}; +#endif + +#if defined (CONFIG_STUART) +static int stuart_init(void) +{ + return pxa_init_dev(STUART); +} + +static void stuart_setbrg(void) +{ + return pxa_setbrg_dev(STUART); +} + +static void stuart_putc(const char c) +{ + return pxa_putc_dev(STUART,c); +} + +static void stuart_puts(const char *s) +{ + return pxa_puts_dev(STUART,s); +} + +static int stuart_getc(void) +{ + return pxa_getc_dev(STUART); +} + +static int stuart_tstc(void) +{ + return pxa_tstc_dev(STUART); +} + +struct serial_device serial_stuart_device = +{ + "serial_stuart", + "PXA", + stuart_init, + stuart_setbrg, + stuart_getc, + stuart_tstc, + stuart_putc, + stuart_puts, +}; +#endif + + +#ifndef CONFIG_SERIAL_MULTI +inline int serial_init(void) { + return (pxa_init_dev(UART_INDEX)); +} +void serial_setbrg(void) { + pxa_setbrg_dev(UART_INDEX); +} +int serial_getc(void) { + return(pxa_getc_dev(UART_INDEX)); +} +int serial_tstc(void) { + return(pxa_tstc_dev(UART_INDEX)); +} +void serial_putc(const char c) { + pxa_putc_dev(UART_INDEX,c); +} +void serial_puts(const char *s) { + pxa_puts_dev(UART_INDEX,s); +} +#endif /* CONFIG_SERIAL_MULTI */ diff --git a/doc/README.m5253evbe b/doc/README.m5253evbe new file mode 100644 index 0000000..0426cb1 --- /dev/null +++ b/doc/README.m5253evbe @@ -0,0 +1,103 @@ +Freescale Amadeus Plus M5253EVBE board +====================================== + +Hayden Fraser(Hayden.Fraser@freescale.com) +Created 06/05/2007 +=========================================== + + +1. SWITCH SETTINGS +================== +1.1 N/A + + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + SDR: 0x00000000-0x00ffffff + SRAM0: 0x20010000-0x20017fff + SRAM1: 0x20000000-0x2000ffff + MBAR1: 0x10000000-0x4fffffff + MBAR2: 0x80000000-0xCfffffff + Flash: 0xffe00000-0xffffffff + +3. DEFINITIONS AND COMPILATION +============================== +3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h + CONFIG_MCF52x2 Processor family + CONFIG_MCF5253 MCF5253 specific + CONFIG_M5253EVBE Amadeus Plus board specific + CFG_CLK Define Amadeus Plus CPU Clock + CFG_MBAR MBAR base address + CFG_MBAR2 MBAR2 base address + +3.2 Compilation + export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf- + cd u-boot-1-2-x + make distclean + make M5253EVBE_config + make + + +4. SCREEN DUMP +============== +4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00) + +CPU: Freescale Coldfire MCF5253 at 62 MHz +Board: Freescale MCF5253 EVBE +DRAM: 16 MB +FLASH: 2 MB +In: serial +Out: serial +Err: serial +=> flinfo + +Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors + AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49 + Erase timeout: 16384 ms, write timeout: 1 ms + + Sector Start Addresses: + FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO + FFE20000 FFE30000 FFE40000 FFE50000 FFE60000 + FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000 + FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000 + FFF10000 FFF20000 FFF30000 FFF40000 FFF50000 + FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000 + FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000 + +=> bdinfo +boot_params = 0x00F62F90 +memstart = 0x00000000 +memsize = 0x01000000 +flashstart = 0xFFE00000 +flashsize = 0x00200000 +flashoffset = 0x00000000 +baudrate = 19200 bps + +=> printenv +bootdelay=5 +baudrate=19200 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 134/8188 bytes +=> saveenv +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... +. done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + +5. COMPILER +----------- +To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture +compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used. +You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M +codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M diff --git a/doc/README.m54455evb b/doc/README.m54455evb new file mode 100644 index 0000000..119a19d --- /dev/null +++ b/doc/README.m54455evb @@ -0,0 +1,416 @@ +Freescale MCF54455EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 4/08/07 +=========================================== + + +Changed files: +============== + +- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init +- board/freescale/m54455evb/flash.c Atmel and INTEL flash support +- board/freescale/m54455evb/Makefile Makefile +- board/freescale/m54455evb/config.mk config make +- board/freescale/m54455evb/u-boot.lds Linker description + +- common/cmd_bdinfo.c Clock frequencies output +- common/cmd_mii.c mii support + +- cpu/mcf5445x/cpu.c cpu specific code +- cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- cpu/mcf5445x/interrupts.c cpu specific interrupt support +- cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock +- cpu/mcf5445x/Makefile Makefile +- cpu/mcf5445x/config.mk config make +- cpu/mcf5445x/start.S start up assembly code + +- doc/README.m54455evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5445x.h mcf5445x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m5445x.h mcf5445x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M54455EVB.h Board specific configuration file + +- lib_m68k/board.c board init function +- lib_m68k/cache.c +- lib_m68k/interrupts Coldfire common interrupt functions +- lib_m68k/m68k_linux.c +- lib_m68k/time.c Timer functions (Dma timer and PIT) +- lib_m68k/traps.c Exception init code + +- rtc/mcfrtc.c Realtime clock Driver + +1 MCF5445x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M54455EVB Development Board +CONFIG_MCF5445x -- define for all MCF5445x CPUs +CONFIG_M54455 -- define for all Freescale MCF54455 CPUs +CONFIG_M54455EVB -- define for M54455EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CFG_MCFRTC_BASE -- provide base address for RTC in immap.h +CFG_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_NET_MULTI -- define to use multi FEC in u-boot +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CFG_DISCOVER_PHY -- enable PHY discovery +CFG_RX_ETH_BUFFER -- Set FEC Receive buffer +CFG_FAULT_ECHO_LINK_DOWN-- +CFG_FEC0_PINMUX -- Set FEC0 Pin configuration +CFG_FEC1_PINMUX -- Set FEC1 Pin configuration +CFG_FEC0_MIIBASE -- Set FEC0 MII base register +CFG_FEC1_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop +CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot + +CONFIG_ISO_PARTITION -- enable ISO read/write +CONFIG_DOS_PARTITION -- enable DOS read/write +CONFIG_IDE_RESET -- define ide_reset() +CONFIG_IDE_PREINIT -- define ide_preinit() +CONFIG_ATAPI -- define ATAPI support +CONFIG_LBA48 -- define LBA48 (larger than 120GB) support +CFG_IDE_MAXBUS -- define max channel +CFG_IDE_MAXDEVICE -- define max devices per channel +CFG_ATA_BASE_ADDR -- define ATA base address +CFG_ATA_IDE0_OFFSET -- define ATA IDE0 offset +CFG_ATA_DATA_OFFSET -- define ATA data IO +CFG_ATA_REG_OFFSET -- define for normal register accesses +CFG_ATA_ALT_OFFSET -- define for alternate registers +CFG_ATA_STRIDE -- define for Interval between registers +_IO_BASE -- define for IO base address + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CFG_I2C_SPEED -- define for I2C speed +CFG_I2C_SLAVE -- define for I2C slave address +CFG_I2C_OFFSET -- define for I2C base address offset +CFG_IMMR -- define for MBAR offset + +CONFIG_PCI -- define for PCI support +CONFIG_PCI_PNP -- define for Plug n play support +CFG_PCI_MEM_BUS -- PCI memory logical offset +CFG_PCI_MEM_PHYS -- PCI memory physical offset +CFG_PCI_MEM_SIZE -- PCI memory size +CFG_PCI_IO_BUS -- PCI IO logical offset +CFG_PCI_IO_PHYS -- PCI IO physical offset +CFG_PCI_IO_SIZE -- PCI IO size +CFG_PCI_CFG_BUS -- PCI Configuration logical offset +CFG_PCI_CFG_PHYS -- PCI Configuration physical offset +CFG_PCI_CFG_SIZE -- PCI Configuration size + +CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc + +CFG_MBAR -- define MBAR offset + +CFG_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CFG_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM + +CFG_CSn_BASE -- defines the Chip Select Base register +CFG_CSn_MASK -- defines the Chip Select Mask register +CFG_CSn_CTRL -- defines the Chip Select Control register + +CFG_ATMEL_BASE -- defines the Atmel Flash base +CFG_INTEL_BASE -- defines the Intel Flash base + +CFG_SDRAM_BASE -- defines the DRAM Base +CFG_SDRAM_BASE1 -- defines the DRAM Base 1 + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + ATA: 0x90000000-0x9FFFFFFF (256MB) + PCI: 0xA0000000-0xBFFFFFFF (512MB) + FlexBus: 0xC0000000-0xDFFFFFFF (512MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Atmel boot: + Flash0: 0x00000000-0x0007FFFF (512KB) + Flash1: 0x04000000-0x05FFFFFF (32MB) + Intel boot: + Flash0: 0x00000000-0x01FFFFFF (32MB) + Flash1: 0x04000000-0x0407FFFF (512KB) + + CPLD: 0x08000000-0x08FFFFFF (16MB) + FPGA: 0x09000000-0x09FFFFFF (16MB) + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. SWITCH SETTINGS +================== +3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL + SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state + SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down + 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active + SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down + SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL + +4. COMPILATION +============== +4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version) +from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +4.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M54455EVB_config, or - default to atmel 33Mhz input clock + make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock + make M54455EVB_a33_config, or - default to atmel 33Mhz input clock + make M54455EVB_a66_config, or - default to atmel 66Mhz input clock + make M54455EVB_intel_config, or - default to intel 33Mhz input clock + make M54455EVB_i33_config, or - default to intel 33Mhz input clock + make M54455EVB_i66_config, or - default to intel 66Mhz input clock + make + +5. SCREEN DUMP +============== +5.1 M54455EVB Development board + Boot from Atmel (NOTE: May not show exactly the same) + +U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08) + +CPU: Freescale MCF54455 (Mask:48 Version:1) + CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz + PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz +Board: Freescale M54455 EVB +I2C: ready +DRAM: 256 MB +FLASH: 16.5 MB +In: serial +Out: serial +Err: serial +Net: FEC0, FEC1 +IDE: Bus 0: not available +-> print +bootargs=root=/dev/ram rw +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +eth1addr=00:e0:0c:bc:e5:61 +hostname=M54455EVB +netdev=eth0 +inpclk=33333333 +loadaddr=40010000 +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save +ethact=FEC0 +mtdids=nor0=M54455EVB-1 +mtdparts=M54455EVB-1:16m(user) +u-boot=u-boot54455.bin +filesize=292b4 +fileaddr=40010000 +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=261632k + +Environment size: 563/8188 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x10000000 +flashstart = 0x00000000 +flashsize = 0x01080000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 133.333 MHz +pcifreq = 33.333 MHz +flbfreq = 66.666 MHz +inpfreq = 33.333 MHz +vcofreq = 533.333 MHz +ethaddr = 00:E0:0C:BC:E5:60 +eth1addr = 00:E0:0C:BC:E5:61 +ip_addr = 192.168.1.3 +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +diskboot- boot from IDE device +echo - echo args to console +erase - erase FLASH memory +ext2load- load binary file from a Ext2 filesystem +ext2ls - list files in a directory (default /) +fatinfo - print information about filesystem +fatload - load binary file from a dos filesystem +fatls - list files in a directory (default /) +flinfo - print FLASH memory information +fsinfo - print information about filesystems +fsload - load binary file from a filesystem image +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +icrc32 - checksum calculation +ide - IDE sub-system +iloop - infinite loop on address range +imd - i2c memory display +iminfo - print header information for application image +imls - list all images found in flash +imm - i2c memory modify (auto-incrementing) +imw - memory write (fill) +inm - memory modify (constant address) +iprobe - probe to discover valid I2C chip addresses +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +pci - list and access PCI Configuration Space +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +tftpboot- boot image via network using TFTP protocol +version - print monitor version +->bootm 4000000 + +## Booting image at 04000000 ... + Image Name: Linux Kernel Image + Created: 2007-08-14 15:13:00 UTC + Image Type: M68K Linux Kernel Image (uncompressed) + Data Size: 2301952 Bytes = 2.2 MB + Load Address: 40020000 + Entry Point: 40020000 + Verifying Checksum ... OK +OK +Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr +erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007 +starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB +Built 1 zonelists. Total pages: 32624 +Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph +ysmap-flash.0:5M(kernel)ro,-(jffs2) +PID hash table entries: 1024 (order: 10, 4096 bytes) +Console: colour dummy device 80x25 +Dentry cache hash table entries: 32768 (order: 4, 131072 bytes) +Inode-cache hash table entries: 16384 (order: 3, 65536 bytes) +Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init) +Mount-cache hash table entries: 1024 +NET: Registered protocol family 16 +SCSI subsystem initialized +NET: Registered protocol family 2 +IP route cache hash table entries: 2048 (order: 0, 8192 bytes) +TCP established hash table entries: 8192 (order: 2, 32768 bytes) +TCP bind hash table entries: 4096 (order: 1, 16384 bytes) +TCP: Hash tables configured (established 8192 bind 4096) +TCP reno registered +JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. +io scheduler noop registered +io scheduler anticipatory registered +io scheduler deadline registered +io scheduler cfq registered (default) +ColdFire internal UART serial driver version 1.00 +ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART +ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART +ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART +RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize +loop: loaded (max 8 devices) +FEC ENET Version 0.2 +fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849 +eth0: ethernet 00:08:ee:00:e4:19 +physmap platform flash device: 01000000 at 04000000 +physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank + Intel/Sharp Extended Query Table at 0x0031 +Using buffer write method +cfi_cmdset_0001: Erase suspend on write enabled +2 cmdlinepart partitions found on MTD device physmap-flash.0 +Creating 2 MTD partitions on "physmap-flash.0": +0x00000000-0x00500000 : "kernel" +mtd: Giving out device 0 to kernel +0x00500000-0x01000000 : "jffs2" +mtd: Giving out device 1 to jffs2 +mice: PS/2 mouse device common for all mice +i2c /dev entries driver +TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 17 +NET: Registered protocol family 15 +VFS: Mounted root (jffs2 filesystem). +Setting the hostname to freescale +Mounting filesystems +mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory +Starting syslogd and klogd +Setting up networking on loopback device: +Setting up networking on eth0: +eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. +Adding static route for default gateway to 172.27.255.254: +Setting nameserver to 172.27.0.1 in /etc/resolv.conf: +Starting inetd: +/ # diff --git a/drivers/Makefile b/drivers/Makefile index 3ee6312..6bf05cc 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -43,7 +43,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ - sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ + sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 586e83b..90c64da 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -2,9 +2,11 @@ include $(TOPDIR)/config.mk LIB := $(obj)libatibiosemu.a -X86DIR = ./x86emu +X86DIR = x86emu -OBJS = atibios.o biosemu.o besys.o bios.o \ +$(shell mkdir -p $(obj)$(X86DIR)) + +COBJS = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/decode.o \ $(X86DIR)/ops2.o \ $(X86DIR)/ops.o \ @@ -12,19 +14,24 @@ OBJS = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -CFLAGS += -I. -I./include -I$(X86DIR) -I$(TOPDIR)/include \ +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ -D__PPC__ -D__BIG_ENDIAN__ +CFLAGS += $(EXTRA_CFLAGS) +HOST_CFLAGS += $(EXTRA_CFLAGS) + all: $(LIB) -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index 78acb09..6131b5c 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -99,7 +99,7 @@ void eth_halt(void); static int dm9000_probe(void); static u16 phy_read(int); static void phy_write(int, u16); -static u16 read_srom_word(int); +u16 read_srom_word(int); static u8 DM9000_ior(int); static void DM9000_iow(int reg, u8 value); @@ -303,8 +303,8 @@ eth_init(bd_t * bd) for (i = 0; i < 6; i++) ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); - if (!is_zero_ether_addr(bd->bi_enetaddr) && - !is_mutlicast_ether_addr(bd->bi_enetaddr)) { + if (is_zero_ether_addr(bd->bi_enetaddr) || + is_multicast_ether_addr(bd->bi_enetaddr)) { /* try reading from environment */ u8 i; char *s, *e; @@ -537,16 +537,28 @@ eth_rx(void) /* Read a word data from SROM */ -static u16 +u16 read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); DM9000_iow(DM9000_EPCR, 0x4); - udelay(200); + udelay(8000); DM9000_iow(DM9000_EPCR, 0x0); return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); } +void +write_srom_word(int offset, u16 val) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + DM9000_iow(DM9000_EPDRL, (val & 0xff)); + DM9000_iow(DM9000_EPCR, 0x12); + udelay(8000); + DM9000_iow(DM9000_EPCR, 0); +} + + /* Read a byte from I/O port */ diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6..3a13eea 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -130,9 +130,14 @@ fsl_pci_init(struct pci_controller *hose) } - /* Call setup to allocate PCSRBAR window */ - pciauto_setup_device(hose, dev, 1, hose->pci_mem, + /* Use generic setup_device to initialize standard pci regs, + * but do not allocate any windows since any BAR found (such + * as PCSRBAR) is not in this cpu's memory space. + */ + + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c index 075cae6..6d7e347 100644 --- a/drivers/nand/nand_ids.c +++ b/drivers/nand/nand_ids.c @@ -123,6 +123,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, + {NAND_MFR_MICRON, "Micron"}, {0x0, "Unknown"} }; #endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 7342dc8..0639859 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -23,9 +23,8 @@ include $(TOPDIR)/config.mk -LIB := $(obj)libnetdrv.a - -COBJS := xilinx_emaclite.o xilinx_emac.o +LIB := $(obj)libnet.a +COBJS := mcffec.o xilinx_emac.o xilinx_emaclite.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c new file mode 100644 index 0000000..3b81258 --- /dev/null +++ b/drivers/net/mcffec.c @@ -0,0 +1,597 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> + +#ifdef CONFIG_MCFFEC + +#include <asm/fec.h> +#include <asm/immap.h> + +#include <command.h> +#include <net.h> +#include <miiphy.h> + +#undef ET_DEBUG +#undef MII_DEBUG + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 +#define TX_BUF_CNT 2 +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 +#define LAST_PKTBUFSRX PKTBUFSRX - 1 +#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) +#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) + +struct fec_info_s fec_info[] = { +#ifdef CFG_FEC0_IOBASE + { + 0, /* index */ + CFG_FEC0_IOBASE, /* io base */ + CFG_FEC0_PINMUX, /* gpio pin muxing */ + CFG_FEC0_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phyname init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + }, +#endif +#ifdef CFG_FEC1_IOBASE + { + 1, /* index */ + CFG_FEC1_IOBASE, /* io base */ + CFG_FEC1_PINMUX, /* gpio pin muxing */ + CFG_FEC1_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phy name init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + } +#endif +}; + +int fec_send(struct eth_device *dev, volatile void *packet, int length); +int fec_recv(struct eth_device *dev); +int fec_init(struct eth_device *dev, bd_t * bd); +void fec_halt(struct eth_device *dev); +void fec_reset(struct eth_device *dev); + +extern int fecpin_setclear(struct eth_device *dev, int setclear); + +#ifdef CFG_DISCOVER_PHY +extern void __mii_init(void); +extern uint mii_send(uint mii_cmd); +extern int mii_discover_phy(struct eth_device *dev); +extern int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +extern int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +#endif + +void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) +{ + if ((dup_spd >> 16) == FULL) { + /* Set maximum frame length */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | + FEC_RCR_PROM | 0x100; + fecp->tcr = FEC_TCR_FDEN; + } else { + /* Half duplex mode */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | + FEC_RCR_MII_MODE | FEC_RCR_DRT; + fecp->tcr &= ~FEC_TCR_FDEN; + } + + if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef MII_DEBUG + printf("100Mbps\n"); +#endif + bd->bi_ethspeed = 100; + } else { +#ifdef MII_DEBUG + printf("10Mbps\n"); +#endif + bd->bi_ethspeed = 10; + } +} + +int fec_send(struct eth_device *dev, volatile void *packet, int length) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int j, rc; + u16 phyStatus; + + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && + (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("TX not ready\n"); + } + + info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; + info->txbd[info->txIdx].cbd_datlen = length; + info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; + + /* Activate transmit Buffer Descriptor polling */ + fecp->tdar = 0x01000000; /* Descriptor polling active */ + +#ifdef CFG_UNIFY_CACHE + icache_invalid(); +#endif + j = 0; + while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && + (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("TX timeout\n"); + } + +#ifdef ET_DEBUG + printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", + __FILE__, __LINE__, __FUNCTION__, j, + info->txbd[info->txIdx].cbd_sc, + (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); +#endif + + /* return only status bits */ + rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); + info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; + + return rc; +} + +int fec_recv(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int length; + + for (;;) { +#ifdef CFG_UNIFY_CACHE + icache_invalid(); +#endif + /* section 16.9.23.2 */ + if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = info->rxbd[info->rxIdx].cbd_datlen; + + if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { + printf("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + info->rxbd[info->rxIdx].cbd_sc); +#ifdef ET_DEBUG + printf("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + info->rxbd[info->rxIdx].cbd_sc); +#endif + } else { + + length -= 4; + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[info->rxIdx], length); + + fecp->eir |= FEC_EIR_RXF; + } + + /* Give the buffer back to the FEC. */ + info->rxbd[info->rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if (info->rxIdx == LAST_PKTBUFSRX) { + info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; + info->rxIdx = 0; + } else { + info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + info->rxIdx++; + } + + /* Try to fill Buffer Descriptors */ + fecp->rdar = 0x01000000; /* Descriptor polling active */ + } + + return length; +} + +#ifdef ET_DEBUG +void dbgFecRegs(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + + printf("=====\n"); + printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); + printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); + printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); + printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); + printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); + printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); + printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); + printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); + printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); + printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); + printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); + printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); + printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); + printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); + printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); + printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); + printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); + printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); + printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); + printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); + printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); + printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); + printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); + + printf("\n"); + printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, + fecp->rmon_t_drop); + printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, + fecp->rmon_t_packets); + printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, + fecp->rmon_t_bc_pkt); + printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, + fecp->rmon_t_mc_pkt); + printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, + fecp->rmon_t_crc_align); + printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, + fecp->rmon_t_undersize); + printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, + fecp->rmon_t_oversize); + printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, + fecp->rmon_t_frag); + printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, + fecp->rmon_t_jab); + printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, + fecp->rmon_t_col); + printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, + fecp->rmon_t_p64); + printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, + fecp->rmon_t_p65to127); + printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, + fecp->rmon_t_p128to255); + printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, + fecp->rmon_t_p256to511); + printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, + fecp->rmon_t_p512to1023); + printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, + fecp->rmon_t_p1024to2047); + printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, + fecp->rmon_t_p_gte2048); + printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, + fecp->rmon_t_octets); + + printf("\n"); + printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, + fecp->ieee_t_drop); + printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, + fecp->ieee_t_frame_ok); + printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, + fecp->ieee_t_1col); + printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, + fecp->ieee_t_mcol); + printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, + fecp->ieee_t_def); + printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, + fecp->ieee_t_lcol); + printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, + fecp->ieee_t_excol); + printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, + fecp->ieee_t_macerr); + printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, + fecp->ieee_t_cserr); + printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, + fecp->ieee_t_sqe); + printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, + fecp->ieee_t_fdxfc); + printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, + fecp->ieee_t_octets_ok); + + printf("\n"); + printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, + fecp->rmon_r_drop); + printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, + fecp->rmon_r_packets); + printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, + fecp->rmon_r_bc_pkt); + printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, + fecp->rmon_r_mc_pkt); + printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, + fecp->rmon_r_crc_align); + printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, + fecp->rmon_r_undersize); + printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, + fecp->rmon_r_oversize); + printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, + fecp->rmon_r_frag); + printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, + fecp->rmon_r_jab); + printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, + fecp->rmon_r_p64); + printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, + fecp->rmon_r_p65to127); + printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, + fecp->rmon_r_p128to255); + printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, + fecp->rmon_r_p256to511); + printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, + fecp->rmon_r_p512to1023); + printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, + fecp->rmon_r_p1024to2047); + printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, + fecp->rmon_r_p_gte2048); + printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, + fecp->rmon_r_octets); + + printf("\n"); + printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, + fecp->ieee_r_drop); + printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, + fecp->ieee_r_frame_ok); + printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, + fecp->ieee_r_crc); + printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, + fecp->ieee_r_align); + printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, + fecp->ieee_r_macerr); + printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, + fecp->ieee_r_fdxfc); + printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, + fecp->ieee_r_octets_ok); + + printf("\n\n\n"); +} +#endif + +int fec_init(struct eth_device *dev, bd_t * bd) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int i; + u8 *ea = NULL; + + fecpin_setclear(dev, 1); + + fec_reset(dev); + +#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ + defined (CFG_DISCOVER_PHY) + + mii_init(); + + setFecDuplexSpeed(fecp, bd, info->dup_spd); +#else +#ifndef CFG_DISCOVER_PHY + setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); +#endif /* ifndef CFG_DISCOVER_PHY */ +#endif /* CONFIG_CMD_MII || CONFIG_MII */ + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set station address */ + if ((u32) fecp == CFG_FEC0_IOBASE) { +#ifdef CFG_FEC1_IOBASE + volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); + ea = &bd->bi_enet1addr[0]; + fecp1->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp1->paur = (ea[4] << 24) | (ea[5] << 16); +#endif + ea = &bd->bi_enetaddr[0]; + fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); + } else { +#ifdef CFG_FEC0_IOBASE + volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); + ea = &bd->bi_enetaddr[0]; + fecp0->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp0->paur = (ea[4] << 24) | (ea[5] << 16); +#endif +#ifdef CFG_FEC1_IOBASE + ea = &bd->bi_enet1addr[0]; + fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); +#endif + } + + /* Clear unicast address hash table */ + fecp->iaur = 0; + fecp->ialr = 0; + + /* Clear multicast address hash table */ + fecp->gaur = 0; + fecp->galr = 0; + + /* Set maximum receive buffer size. */ + fecp->emrbr = PKT_MAXBLR_SIZE; + + /* + * Setup Buffers and Buffer Desriptors + */ + info->rxIdx = 0; + info->txIdx = 0; + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + for (i = 0; i < PKTBUFSRX; i++) { + info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + info->rxbd[i].cbd_datlen = 0; /* Reset */ + info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Last, Tx CRC + */ + for (i = 0; i < TX_BUF_CNT; i++) { + info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; + info->txbd[i].cbd_datlen = 0; /* Reset */ + info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); + } + info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* Set receive and transmit descriptor base */ + fecp->erdsr = (unsigned int)(&info->rxbd[0]); + fecp->etdsr = (unsigned int)(&info->txbd[0]); + + /* Now enable the transmit and receive processing */ + fecp->ecr |= FEC_ECR_ETHER_EN; + + /* And last, try to fill Rx Buffer Descriptors */ + fecp->rdar = 0x01000000; /* Descriptor polling active */ + + return 1; +} + +void fec_reset(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +void fec_halt(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + + fec_reset(dev); + + fecpin_setclear(dev, 0); + + info->rxIdx = info->txIdx = 0; + memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); + memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); + memset(info->txbuf, 0, DBUF_LENGTH); +} + +int mcffec_initialize(bd_t * bis) +{ + struct eth_device *dev; + int i; + + for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { + + dev = + (struct eth_device *)memalign(CFG_CACHELINE_SIZE, + sizeof *dev); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "FEC%d", fec_info[i].index); + + dev->priv = &fec_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + /* setup Receive and Transmit buffer descriptor */ + fec_info[i].rxbd = + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); + fec_info[i].txbd = + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (TX_BUF_CNT * sizeof(cbd_t))); + fec_info[i].txbuf = + (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", + (int)fec_info[i].rxbd, (int)fec_info[i].txbd); +#endif + + fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, + mcffec_miiphy_read, mcffec_miiphy_write); +#endif + } + + /* default speed */ + bis->bi_ethspeed = 10; + + return 1; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ +#endif /* CONFIG_MCFFEC */ diff --git a/drivers/pci.c b/drivers/pci.c index 4158919..50ca6b0 100644 --- a/drivers/pci.c +++ b/drivers/pci.c @@ -82,8 +82,10 @@ int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ { \ u32 val32; \ \ - if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ + *val = -1; \ return -1; \ + } \ \ *val = (val32 >> ((offset & (int)off_mask) * 8)); \ \ diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 2378553..acfda83 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -28,6 +28,11 @@ #define PCIAUTO_IDE_MODE_MASK 0x05 +/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CFG_PCI_CACHE_LINE_SIZE +#define CFG_PCI_CACHE_LINE_SIZE 8 +#endif + /* * */ @@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose, } pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, + CFG_PCI_CACHE_LINE_SIZE); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 89a7279..dc2765b 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1110,7 +1110,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __FUNCTION__); - return -EINVAL; + return 0; } uec_set_mac_address(uec, dev->enetaddr); uec->the_first_run = 1; @@ -1119,10 +1119,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd) err = uec_open(uec, COMM_DIR_RX_AND_TX); if (err) { printf("%s: cannot enable UEC device\n", dev->name); - return err; + return 0; } - return 0; + return uec->mii_info->link; } static void uec_halt(struct eth_device* dev) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile new file mode 100644 index 0000000..93c68dd --- /dev/null +++ b/drivers/serial/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libserial.a + +COBJS := mcfuart.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c new file mode 100644 index 0000000..88f3eb1 --- /dev/null +++ b/drivers/serial/mcfuart.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Minimal serial functions needed to use one of the uart ports + * as serial console interface. + */ + +#include <common.h> + +#ifdef CONFIG_MCFUART + +#include <asm/immap.h> +#include <asm/uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void uart_port_conf(void); + +int serial_init(void) +{ + volatile uart_t *uart; + u32 counter; + + uart = (volatile uart_t *)(CFG_UART_BASE); + + uart_port_conf(); + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + uart->ucr = UART_UCR_RESET_ERROR; + uart->ucr = UART_UCR_RESET_MR; + __asm__("nop"); + + uart->uimr = 0; + + /* write to CSR: RX/TX baud rate from timers */ + uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK); + + uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE); + uart->umr = UART_UMR_SB_STOP_BITS_1; + + /* Setting up BaudRate */ + counter = (u32) (gd->bus_clk / (gd->baudrate)); + counter >>= 5; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = (u8) ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (u8) (counter & 0x00ff); + + uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED); + + return (0); +} + +void serial_putc(const char c) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + if (c == '\n') + serial_putc('\r'); + + /* Wait for last character to go. */ + while (!(uart->usr & UART_USR_TXRDY)) ; + + uart->utb = c; +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + /* Wait for a character to arrive. */ + while (!(uart->usr & UART_USR_RXRDY)) ; + return uart->urb; +} + +int serial_tstc(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + return (uart->usr & UART_USR_RXRDY); +} + +void serial_setbrg(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + u32 counter; + + counter = ((gd->bus_clk / gd->baudrate)) >> 5; + counter++; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (counter & 0x00ff); + + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + + uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED; +} +#endif /* CONFIG_MCFUART */ diff --git a/drivers/sil680.c b/drivers/sil680.c new file mode 100644 index 0000000..a6143df --- /dev/null +++ b/drivers/sil680.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2007 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* sil680.c - ide support functions for the Sil0680A controller */ + +/* + * The following parameters must be defined in the configuration file + * of the target board: + * + * #define CFG_IDE_SIL680 + * + * #define CONFIG_PCI_PNP + * NOTE it may also be necessary to define this if the default of 8 is + * incorrect for the target board (e.g. the sequoia board requires 0). + * #define CFG_PCI_CACHE_LINE_SIZE 0 + * + * #define CONFIG_CMD_IDE + * #undef CONFIG_IDE_8xx_DIRECT + * #undef CONFIG_IDE_LED + * #undef CONFIG_IDE_RESET + * #define CONFIG_IDE_PREINIT + * #define CFG_IDE_MAXBUS 2 - modify to suit + * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit + * #define CFG_ATA_BASE_ADDR 0 + * #define CFG_ATA_IDE0_OFFSET 0 + * #define CFG_ATA_IDE1_OFFSET 0 + * #define CFG_ATA_DATA_OFFSET 0 + * #define CFG_ATA_REG_OFFSET 0 + * #define CFG_ATA_ALT_OFFSET 0x0004 + * + * The mapping for PCI IO-space. + * NOTE this is the value for the sequoia board. Modify to suit. + * #define CFG_PCI0_IO_SPACE 0xE8000000 + */ + +#include <common.h> +#if defined(CFG_IDE_SIL680) +#include <ata.h> +#include <ide.h> +#include <pci.h> + +extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; + +int ide_preinit (void) +{ + int status; + pci_dev_t devbusfn; + int l; + + status = 1; + for (l = 0; l < CFG_IDE_MAXBUS; l++) { + ide_bus_offset[l] = -ATA_STATUS; + } + devbusfn = pci_find_device (0x1095, 0x0680, 0); + if (devbusfn != -1) { + status = 0; + + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (u32 *) &ide_bus_offset[0]); + ide_bus_offset[0] &= 0xfffffff8; + ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) &ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffff8; + ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + /* init various things - taken from the Linux driver */ + /* set PIO mode */ + pci_write_config_byte(devbusfn, 0x80, 0x00); + pci_write_config_byte(devbusfn, 0x84, 0x00); + /* IDE0 */ + pci_write_config_byte(devbusfn, 0xA1, 0x02); + pci_write_config_word(devbusfn, 0xA2, 0x328A); + pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xA8, 0x43924392); + pci_write_config_dword(devbusfn, 0xAC, 0x40094009); + /* IDE1 */ + pci_write_config_byte(devbusfn, 0xB1, 0x02); + pci_write_config_word(devbusfn, 0xB2, 0x328A); + pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xB8, 0x43924392); + pci_write_config_dword(devbusfn, 0xBC, 0x40094009); + } + return (status); +} + +void ide_set_reset (int flag) { + return; +} + +#endif /* CFG_IDE_SIL680 */ diff --git a/drivers/tsec.c b/drivers/tsec.c index fd21ed4..6bca4dc 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -65,38 +65,30 @@ struct tsec_info_struct { * FEC_PHYIDX */ static struct tsec_info_struct tsec_info[] = { -#if defined(CONFIG_TSEC1) -#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN) - {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, -#else - {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, -#endif +#ifdef CONFIG_TSEC1 + {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, #else {0, 0, 0}, #endif -#if defined(CONFIG_TSEC2) -#if defined(CONFIG_MPC8641HPCN) - {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, -#else - {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, -#endif +#ifdef CONFIG_TSEC2 + {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, #else {0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC - {FEC_PHY_ADDR, 0, FEC_PHYIDX}, + {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, #else -#if defined(CONFIG_TSEC3) - {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, +#ifdef CONFIG_TSEC3 + {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, #else {0, 0, 0}, #endif -#if defined(CONFIG_TSEC4) - {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, +#ifdef CONFIG_TSEC4 + {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, #else {0, 0, 0}, -#endif -#endif +#endif /* CONFIG_TSEC4 */ +#endif /* CONFIG_MPC85XX_FEC */ }; #define MAXCONTROLLERS (4) @@ -355,17 +347,16 @@ uint mii_cr_init(uint mii_reg, struct tsec_private * priv) uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) { /* - * Wait if PHY is capable of autonegotiation and autonegotiation - * is not complete. + * Wait if the link is up, and autonegotiation is in progress + * (ie - we're capable and it's not done) */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & PHY_BMSR_AUTN_ABLE) + if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); - while (!((mii_reg & PHY_BMSR_AUTN_COMP) - && (mii_reg & MIIM_STATUS_LINK))) { + while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { /* * Timeout reached ? */ @@ -385,7 +376,10 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) priv->link = 1; udelay(500000); /* another 500 ms (results in faster booting) */ } else { - priv->link = 1; + if (mii_reg & MIIM_STATUS_LINK) + priv->link = 1; + else + priv->link = 0; } return 0; @@ -525,16 +519,13 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); - if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && - (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { + if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && + !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { int i = 0; puts("Waiting for PHY realtime link"); - while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && - (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { - /* - * Timeout reached ? - */ + while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + /* Timeout reached ? */ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts(" TIMEOUT !\n"); priv->link = 0; @@ -549,6 +540,11 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) } puts(" done\n"); udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) + priv->link = 1; + else + priv->link = 0; } if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index f0a37b2..14984a5 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -669,7 +669,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi) ed_p = &(((ed_t *)ed_p)->hwNextED)) inter = ep_rev (6, ((ed_t *)ed_p)->int_interval); ed->hwNextED = *ed_p; - *ed_p = m32_swap(ed); + *ed_p = m32_swap((unsigned long)ed); } break; } @@ -687,11 +687,11 @@ static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed, /* ED might have been unlinked through another path */ while (*ed_p != 0) { - if (((struct ed *)m32_swap (ed_p)) == ed) { + if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) { *ed_p = ed->hwNextED; break; } - ed_p = & (((struct ed *)m32_swap (ed_p))->hwNextED); + ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED); } } } diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e8cb299..9b4da3a 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1288,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3) -#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3) -#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3) -#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3) -#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3) -#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3) -#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3) -#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)) +#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \ + ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3) #else #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h index 3283714..0f9e8ab 100644 --- a/include/asm-m68k/bitops.h +++ b/include/asm-m68k/bitops.h @@ -15,4 +15,43 @@ extern int test_and_set_bit(int nr, volatile void *addr); extern int test_and_clear_bit(int nr, volatile void *addr); extern int test_and_change_bit(int nr, volatile void *addr); +#ifdef __KERNEL__ + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +extern __inline__ int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} +#define __ffs(x) (ffs(x) - 1) + +#endif /* __KERNEL__ */ + #endif /* _M68K_BITOPS_H */ diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h index ce613ac..0e2a0ed 100644 --- a/include/asm-m68k/byteorder.h +++ b/include/asm-m68k/byteorder.h @@ -1,7 +1,107 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef _M68K_BYTEORDER_H #define _M68K_BYTEORDER_H #include <asm/types.h> + +#ifdef __GNUC__ +#define __sw16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define __sw32(x) \ + ((__u32)( \ + (((__u32)(x)) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x)) >> 24) )) + +extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) +{ + unsigned result = *addr; + return __sw16(result); +} + +extern __inline__ void st_le16(volatile unsigned short *addr, + const unsigned val) +{ + *addr = __sw16(val); +} + +extern __inline__ unsigned ld_le32(const volatile unsigned *addr) +{ + unsigned result = *addr; + return __sw32(result); +} + +extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) +{ + *addr = __sw32(val); +} + +#if 0 +/* alas, egcs sounds like it has a bug in this code that doesn't use the + inline asm correctly, and can cause file corruption. Until I hear that + it's fixed, I can live without the extra speed. I hope. */ +#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) +#if 0 +# define __arch_swab16(x) ld_le16(&x) +# define __arch_swab32(x) ld_le32(&x) +#else +static __inline__ __attribute__ ((const)) +__u16 ___arch__swab16(__u16 value) +{ + return __sw16(value); +} + +static __inline__ __attribute__ ((const)) +__u32 ___arch__swab32(__u32 value) +{ + return __sw32(value); +} + +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) +#endif /* 0 */ + +#endif + +/* The same, but returns converted value from the location pointer by addr. */ +#define __arch__swab16p(addr) ld_le16(addr) +#define __arch__swab32p(addr) ld_le32(addr) + +/* The same, but do the conversion in situ, ie. put the value back to addr. */ +#define __arch__swab16s(addr) st_le16(addr,*addr) +#define __arch__swab32s(addr) st_le32(addr,*addr) +#endif + +#endif /* __GNUC__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#define __BYTEORDER_HAS_U64__ +#endif #include <linux/byteorder/big_endian.h> -#endif /* _M68K_BYTEORDER_H */ +#endif /* _M68K_BYTEORDER_H */ diff --git a/include/asm-m68k/errno.h b/include/asm-m68k/errno.h new file mode 100644 index 0000000..ff364b8 --- /dev/null +++ b/include/asm-m68k/errno.h @@ -0,0 +1,138 @@ +#ifndef _PPC_ERRNO_H +#define _PPC_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ +#define EDEADLOCK 58 /* File locking deadlock error */ +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +/* Should never be seen by user programs */ +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ + +#define _LAST_ERRNO 515 + +#endif diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h index 5bbbfb2..344c5e1 100644 --- a/include/asm-m68k/fec.h +++ b/include/asm-m68k/fec.h @@ -5,6 +5,10 @@ * MPC8xx Communication Processor Module. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * + * Add FEC Structure and definitions + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -30,9 +34,9 @@ /* Buffer descriptors used FEC. */ typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ @@ -53,28 +57,36 @@ typedef struct cpm_buf_desc { /* Buffer descriptor control/status used by Ethernet receive. */ #define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_RO1 ((ushort)0x4000) #define BD_ENET_RX_WRAP ((ushort)0x2000) #define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_RO2 BD_ENET_RX_INTR #define BD_ENET_RX_LAST ((ushort)0x0800) #define BD_ENET_RX_FIRST ((ushort)0x0400) #define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) +#define BD_ENET_RX_MC ((ushort)0x0040) #define BD_ENET_RX_LG ((ushort)0x0020) #define BD_ENET_RX_NO ((ushort)0x0010) #define BD_ENET_RX_SH ((ushort)0x0008) #define BD_ENET_RX_CR ((ushort)0x0004) #define BD_ENET_RX_OV ((ushort)0x0002) #define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_TR BD_ENET_RX_CL #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ /* Buffer descriptor control/status used by Ethernet transmit. */ #define BD_ENET_TX_READY ((ushort)0x8000) #define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_TO1 BD_ENET_TX_PAD #define BD_ENET_TX_WRAP ((ushort)0x2000) #define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_ #define BD_ENET_TX_LAST ((ushort)0x0800) #define BD_ENET_TX_TC ((ushort)0x0400) #define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_ABC BD_ENET_TX_DEF #define BD_ENET_TX_HB ((ushort)0x0100) #define BD_ENET_TX_LC ((ushort)0x0080) #define BD_ENET_TX_RL ((ushort)0x0040) @@ -83,4 +95,261 @@ typedef struct cpm_buf_desc { #define BD_ENET_TX_CSL ((ushort)0x0001) #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ -#endif /* fec_h */ +#ifdef CONFIG_MCFFEC +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ +/* FEC private information */ +struct fec_info_s { + int index; + u32 iobase; + u32 pinmux; + u32 miibase; + int phy_addr; + int dup_spd; + char *phy_name; + int phyname_init; + cbd_t *rxbd; /* Rx BD */ + cbd_t *txbd; /* Tx BD */ + uint rxIdx; + uint txIdx; + char *txbuf; + int initialized; +}; + +/* Register read/write struct */ +typedef struct fec { +#ifdef CONFIG_M5272 + u32 ecr; /* 0x00 */ + u32 eir; /* 0x04 */ + u32 eimr; /* 0x08 */ + u32 ivsr; /* 0x0C */ + u32 rdar; /* 0x10 */ + u32 tdar; /* 0x14 */ + u8 resv1[0x28]; /* 0x18 */ + u32 mmfr; /* 0x40 */ + u32 mscr; /* 0x44 */ + u8 resv2[0x44]; /* 0x48 */ + u32 frbr; /* 0x8C */ + u32 frsr; /* 0x90 */ + u8 resv3[0x10]; /* 0x94 */ + u32 tfwr; /* 0xA4 */ + u32 res4; /* 0xA8 */ + u32 tfsr; /* 0xAC */ + u8 resv4[0x50]; /* 0xB0 */ + u32 opd; /* 0x100 - dummy */ + u32 rcr; /* 0x104 */ + u32 mibc; /* 0x108 */ + u8 resv5[0x38]; /* 0x10C */ + u32 tcr; /* 0x144 */ + u8 resv6[0x270]; /* 0x148 */ + u32 iaur; /* 0x3B8 - dummy */ + u32 ialr; /* 0x3BC - dummy */ + u32 palr; /* 0x3C0 */ + u32 paur; /* 0x3C4 */ + u32 gaur; /* 0x3C8 */ + u32 galr; /* 0x3CC */ + u32 erdsr; /* 0x3D0 */ + u32 etdsr; /* 0x3D4 */ + u32 emrbr; /* 0x3D8 */ + u8 resv12[0x74]; /* 0x18C */ +#else + u8 resv0[0x4]; + u32 eir; + u32 eimr; + u8 resv1[0x4]; + u32 rdar; + u32 tdar; + u8 resv2[0xC]; + u32 ecr; + u8 resv3[0x18]; + u32 mmfr; + u32 mscr; + u8 resv4[0x1C]; + u32 mibc; + u8 resv5[0x1C]; + u32 rcr; + u8 resv6[0x3C]; + u32 tcr; + u8 resv7[0x1C]; + u32 palr; + u32 paur; + u32 opd; + u8 resv8[0x28]; + u32 iaur; + u32 ialr; + u32 gaur; + u32 galr; + u8 resv9[0x1C]; + u32 tfwr; + u8 resv10[0x4]; + u32 frbr; + u32 frsr; + u8 resv11[0x2C]; + u32 erdsr; + u32 etdsr; + u32 emrbr; + u8 resv12[0x74]; +#endif + + u32 rmon_t_drop; + u32 rmon_t_packets; + u32 rmon_t_bc_pkt; + u32 rmon_t_mc_pkt; + u32 rmon_t_crc_align; + u32 rmon_t_undersize; + u32 rmon_t_oversize; + u32 rmon_t_frag; + u32 rmon_t_jab; + u32 rmon_t_col; + u32 rmon_t_p64; + u32 rmon_t_p65to127; + u32 rmon_t_p128to255; + u32 rmon_t_p256to511; + u32 rmon_t_p512to1023; + u32 rmon_t_p1024to2047; + u32 rmon_t_p_gte2048; + u32 rmon_t_octets; + + u32 ieee_t_drop; + u32 ieee_t_frame_ok; + u32 ieee_t_1col; + u32 ieee_t_mcol; + u32 ieee_t_def; + u32 ieee_t_lcol; + u32 ieee_t_excol; + u32 ieee_t_macerr; + u32 ieee_t_cserr; + u32 ieee_t_sqe; + u32 ieee_t_fdxfc; + u32 ieee_t_octets_ok; + u8 resv13[0x8]; + + u32 rmon_r_drop; + u32 rmon_r_packets; + u32 rmon_r_bc_pkt; + u32 rmon_r_mc_pkt; + u32 rmon_r_crc_align; + u32 rmon_r_undersize; + u32 rmon_r_oversize; + u32 rmon_r_frag; + u32 rmon_r_jab; + u32 rmon_r_resvd_0; + u32 rmon_r_p64; + u32 rmon_r_p65to127; + u32 rmon_r_p128to255; + u32 rmon_r_p256to511; + u32 rmon_r_p512to1023; + u32 rmon_r_p1024to2047; + u32 rmon_r_p_gte2048; + u32 rmon_r_octets; + + u32 ieee_r_drop; + u32 ieee_r_frame_ok; + u32 ieee_r_crc; + u32 ieee_r_align; + u32 ieee_r_macerr; + u32 ieee_r_fdxfc; + u32 ieee_r_octets_ok; +} fec_t; + +/********************************************************************* +* Fast Ethernet Controller (FEC) +*********************************************************************/ +/* Bit definitions and macros for FEC_EIR */ +#define FEC_EIR_CLEAR_ALL (0xFFF80000) +#define FEC_EIR_HBERR (0x80000000) +#define FEC_EIR_BABR (0x40000000) +#define FEC_EIR_BABT (0x20000000) +#define FEC_EIR_GRA (0x10000000) +#define FEC_EIR_TXF (0x08000000) +#define FEC_EIR_TXB (0x04000000) +#define FEC_EIR_RXF (0x02000000) +#define FEC_EIR_RXB (0x01000000) +#define FEC_EIR_MII (0x00800000) +#define FEC_EIR_EBERR (0x00400000) +#define FEC_EIR_LC (0x00200000) +#define FEC_EIR_RL (0x00100000) +#define FEC_EIR_UN (0x00080000) + +/* Bit definitions and macros for FEC_RDAR */ +#define FEC_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for FEC_TDAR */ +#define FEC_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for FEC_ECR */ +#define FEC_ECR_ETHER_EN (0x00000002) +#define FEC_ECR_RESET (0x00000001) + +/* Bit definitions and macros for FEC_MMFR */ +#define FEC_MMFR_DATA(x) (((x)&0xFFFF)) +#define FEC_MMFR_ST(x) (((x)&0x03)<<30) +#define FEC_MMFR_ST_01 (0x40000000) +#define FEC_MMFR_OP_RD (0x20000000) +#define FEC_MMFR_OP_WR (0x10000000) +#define FEC_MMFR_PA(x) (((x)&0x1F)<<23) +#define FEC_MMFR_RA(x) (((x)&0x1F)<<18) +#define FEC_MMFR_TA(x) (((x)&0x03)<<16) +#define FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for FEC_MSCR */ +#define FEC_MSCR_DIS_PREAMBLE (0x00000080) +#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1) + +/* Bit definitions and macros for FEC_MIBC */ +#define FEC_MIBC_MIB_DISABLE (0x80000000) +#define FEC_MIBC_MIB_IDLE (0x40000000) + +/* Bit definitions and macros for FEC_RCR */ +#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16) +#define FEC_RCR_FCE (0x00000020) +#define FEC_RCR_BC_REJ (0x00000010) +#define FEC_RCR_PROM (0x00000008) +#define FEC_RCR_MII_MODE (0x00000004) +#define FEC_RCR_DRT (0x00000002) +#define FEC_RCR_LOOP (0x00000001) + +/* Bit definitions and macros for FEC_TCR */ +#define FEC_TCR_RFC_PAUSE (0x00000010) +#define FEC_TCR_TFC_PAUSE (0x00000008) +#define FEC_TCR_FDEN (0x00000004) +#define FEC_TCR_HBC (0x00000002) +#define FEC_TCR_GTS (0x00000001) + +/* Bit definitions and macros for FEC_PAUR */ +#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16) +#define FEC_PAUR_TYPE(x) ((x)&0xFFFF) + +/* Bit definitions and macros for FEC_OPD */ +#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for FEC_TFWR */ +#define FEC_TFWR_X_WMRK(x) ((x)&0x03) +#define FEC_TFWR_X_WMRK_64 (0x01) +#define FEC_TFWR_X_WMRK_128 (0x02) +#define FEC_TFWR_X_WMRK_192 (0x03) + +/* Bit definitions and macros for FEC_FRBR */ +#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2) + +/* Bit definitions and macros for FEC_FRSR */ +#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2) + +/* Bit definitions and macros for FEC_ERDSR */ +#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for FEC_ETDSR */ +#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for FEC_EMRBR */ +#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) + +#define FEC_RESET_DELAY 100 +#define FEC_RX_TOUT 100 + +#endif /* CONFIG_MCFFEC */ +#endif /* fec_h */ diff --git a/include/asm-m68k/fsl_i2c.h b/include/asm-m68k/fsl_i2c.h new file mode 100644 index 0000000..4f71341 --- /dev/null +++ b/include/asm-m68k/fsl_i2c.h @@ -0,0 +1,86 @@ +/* + * Freescale I2C Controller + * + * Copyright 2006 Freescale Semiconductor, Inc. + * + * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, + * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), + * and Jeff Brown. + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_FSL_I2C_H_ +#define _ASM_FSL_I2C_H_ + +#include <asm/types.h> + +typedef struct fsl_i2c { + + u8 adr; /* I2C slave address */ + u8 res0[3]; +#define I2C_ADR 0xFE +#define I2C_ADR_SHIFT 1 +#define I2C_ADR_RES ~(I2C_ADR) + + u8 fdr; /* I2C frequency divider register */ + u8 res1[3]; +#define IC2_FDR 0x3F +#define IC2_FDR_SHIFT 0 +#define IC2_FDR_RES ~(IC2_FDR) + + u8 cr; /* I2C control redister */ + u8 res2[3]; +#define I2C_CR_MEN 0x80 +#define I2C_CR_MIEN 0x40 +#define I2C_CR_MSTA 0x20 +#define I2C_CR_MTX 0x10 +#define I2C_CR_TXAK 0x08 +#define I2C_CR_RSTA 0x04 +#define I2C_CR_BCST 0x01 + + u8 sr; /* I2C status register */ + u8 res3[3]; +#define I2C_SR_MCF 0x80 +#define I2C_SR_MAAS 0x40 +#define I2C_SR_MBB 0x20 +#define I2C_SR_MAL 0x10 +#define I2C_SR_BCSTM 0x08 +#define I2C_SR_SRW 0x04 +#define I2C_SR_MIF 0x02 +#define I2C_SR_RXAK 0x01 + + u8 dr; /* I2C data register */ + u8 res4[3]; +#define I2C_DR 0xFF +#define I2C_DR_SHIFT 0 +#define I2C_DR_RES ~(I2C_DR) + + u8 dfsrr; /* I2C digital filter sampling rate register */ + u8 res5[3]; +#define I2C_DFSRR 0x3F +#define I2C_DFSRR_SHIFT 0 +#define I2C_DFSRR_RES ~(I2C_DR) + + /* Fill out the reserved block */ + u8 res6[0xE8]; +} fsl_i2c_t; + +#endif /* _ASM_I2C_H_ */ diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index f68352f..9d9894b 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -39,6 +39,14 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; +#ifdef CONFIG_PCI + unsigned long pci_clk; +#endif +#ifdef CONFIG_EXTRA_CLOCK + unsigned long inp_clk; + unsigned long vco_clk; + unsigned long flb_clk; +#endif unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h new file mode 100644 index 0000000..ffb9a37 --- /dev/null +++ b/include/asm-m68k/immap.h @@ -0,0 +1,242 @@ +/* + * ColdFire Internal Memory Map and Defines + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_H +#define __IMMAP_H + +#ifdef CONFIG_M5235 +#include <asm/immap_5235.h> +#include <asm/m5235.h> + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR3) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) +#define CFG_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_TMRINTR_MASK (INTC_IPRL_INT22) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CFG_UDELAY_BASE (MMAP_PIT0) +#define CFG_PIT_BASE (MMAP_PIT1) +#define CFG_PIT_PRESCALE (6) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) +#endif /* CONFIG_M5235 */ + +#ifdef CONFIG_M5249 +#include <asm/immap_5249.h> +#include <asm/m5249.h> + +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +#define CFG_INTR_BASE (MMAP_INTC) +#define CFG_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CFG_TMRINTR_NO (31) +#define CFG_TMRINTR_MASK (0x00000400) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) +#endif +#endif /* CONFIG_M5249 */ + +#ifdef CONFIG_M5253 +#include <asm/immap_5253.h> +#include <asm/m5249.h> +#include <asm/m5253.h> + +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +#define CFG_INTR_BASE (MMAP_INTC) +#define CFG_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CFG_TMRINTR_NO (27) +#define CFG_TMRINTR_MASK (0x00000400) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) +#endif +#endif /* CONFIG_M5253 */ + +#ifdef CONFIG_M5271 +#include <asm/immap_5271.h> +#include <asm/m5271.h> + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR3) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) +#define CFG_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_TMRINTR_MASK (INTC_IPRL_INT22) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */ +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) +#endif /* CONFIG_M5271 */ + +#ifdef CONFIG_M5272 +#include <asm/immap_5272.h> +#include <asm/m5272.h> + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +#define CFG_INTR_BASE (MMAP_INTC) +#define CFG_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_TMR0) +#define CFG_TMR_BASE (MMAP_TMR3) +#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr) +#define CFG_TMRINTR_NO (INT_TMR3) +#define CFG_TMRINTR_MASK (INT_ISR_INT24) +#define CFG_TMRINTR_PEND (0) +#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif +#endif /* CONFIG_M5272 */ + +#ifdef CONFIG_M5282 +#include <asm/immap_5282.h> +#include <asm/m5282.h> + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR3) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) +#define CFG_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif +#endif /* CONFIG_M5282 */ + +#ifdef CONFIG_M5329 +#include <asm/immap_5329.h> +#include <asm/m5329.h> + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) +#define CFG_MCFRTC_BASE (MMAP_RTC) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) +#define CFG_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (6) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CFG_UDELAY_BASE (MMAP_PIT0) +#define CFG_PIT_BASE (MMAP_PIT1) +#define CFG_PIT_PRESCALE (6) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) +#endif /* CONFIG_M5329 */ + +#ifdef CONFIG_M54455 +#include <asm/immap_5445x.h> +#include <asm/m5445x.h> + +#define CFG_FEC0_IOBASE (MMAP_FEC0) +#define CFG_FEC1_IOBASE (MMAP_FEC1) + +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) + +#define CFG_MCFRTC_BASE (MMAP_RTC) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) +#define CFG_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (6) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CFG_UDELAY_BASE (MMAP_PIT0) +#define CFG_PIT_BASE (MMAP_PIT1) +#define CFG_PIT_PRESCALE (6) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) + +#ifdef CONFIG_PCI +#define CFG_PCI_BAR0 CFG_SDRAM_BASE +#define CFG_PCI_BAR4 CFG_SDRAM_BASE +#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE) +#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE) +#endif +#endif /* CONFIG_M54455 */ + +#endif /* __IMMAP_H */ diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h new file mode 100644 index 0000000..4a03450 --- /dev/null +++ b/include/asm-m68k/immap_5235.h @@ -0,0 +1,378 @@ +/* + * MCF5329 Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5235__ +#define __IMMAP_5235__ + +#define MMAP_SCM (CFG_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_MBAR + 0x00000280) +#define MMAP_I2C (CFG_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_MBAR + 0x00100000) +#define MMAP_CCM (CFG_MBAR + 0x00110000) +#define MMAP_PLL (CFG_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_MBAR + 0x00190000) +#define MMAP_RNG (CFG_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_MBAR + 0x001F0000) + +/* System Control Module register */ +typedef struct scm_ctrl { + u32 ipsbar; /* 0x00 - MBAR */ + u32 res1; /* 0x04 */ + u32 rambar; /* 0x08 - RAMBAR */ + u32 res2; /* 0x0C */ + u8 crsr; /* 0x10 Core Reset Status Register */ + u8 cwcr; /* 0x11 Core Watchdog Control Register */ + u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */ + u8 cwsr; /* 0x13 Core Watchdog Service Register */ + u32 dmareqc; /* 0x14 */ + u32 res3; /* 0x18 */ + u32 mpark; /* 0x1C */ + u8 mpr; /* 0x20 */ + u8 res4[3]; /* 0x21 - 0x23 */ + u8 pacr0; /* 0x24 */ + u8 pacr1; /* 0x25 */ + u8 pacr2; /* 0x26 */ + u8 pacr3; /* 0x27 */ + u8 pacr4; /* 0x28 */ + u32 res5; /* 0x29 */ + u8 pacr5; /* 0x2a */ + u8 pacr6; /* 0x2b */ + u8 pacr7; /* 0x2c */ + u32 res6; /* 0x2d */ + u8 pacr8; /* 0x2e */ + u32 res7; /* 0x2f */ + u8 gpacr; /* 0x30 */ + u8 res8[3]; /* 0x31 - 0x33 */ +} scm_t; + +/* SDRAM controller registers */ +typedef struct sdram_ctrl { + u16 dcr; /* 0x00 Control register */ + u16 res1[3]; /* 0x02 - 0x07 */ + u32 dacr0; /* 0x08 address and control register 0 */ + u32 dmr0; /* 0x0C mask register block 0 */ + u32 dacr1; /* 0x10 address and control register 1 */ + u32 dmr1; /* 0x14 mask register block 1 */ +} sdram_t; + +/* Flexbus module Chip select registers */ +typedef struct fbcs_ctrl { + u16 csar0; /* 0x00 Chip-Select Address Register 0 */ + u16 res0; + u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ + u16 res1; /* 0x08 */ + u16 cscr0; /* 0x0A Chip-Select Control Register 0 */ + + u16 csar1; /* 0x0C Chip-Select Address Register 1 */ + u16 res2; + u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ + u16 res3; /* 0x14 */ + u16 cscr1; /* 0x16 Chip-Select Control Register 1 */ + + u16 csar2; /* 0x18 Chip-Select Address Register 2 */ + u16 res4; + u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ + u16 res5; /* 0x20 */ + u16 cscr2; /* 0x22 Chip-Select Control Register 2 */ + + u16 csar3; /* 0x24 Chip-Select Address Register 3 */ + u16 res6; + u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ + u16 res7; /* 0x2C */ + u16 cscr3; /* 0x2E Chip-Select Control Register 3 */ + + u16 csar4; /* 0x30 Chip-Select Address Register 4 */ + u16 res8; + u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ + u16 res9; /* 0x38 */ + u16 cscr4; /* 0x3A Chip-Select Control Register 4 */ + + u16 csar5; /* 0x3C Chip-Select Address Register 5 */ + u16 res10; + u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ + u16 res11; /* 0x44 */ + u16 cscr5; /* 0x46 Chip-Select Control Register 5 */ + + u16 csar6; /* 0x48 Chip-Select Address Register 5 */ + u16 res12; + u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */ + u16 res13; /* 0x50 */ + u16 cscr6; /* 0x52 Chip-Select Control Register 5 */ + + u16 csar7; /* 0x54 Chip-Select Address Register 5 */ + u16 res14; + u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */ + u16 res15; /* 0x5C */ + u16 cscr7; /* 0x5E Chip-Select Control Register 5 */ +} fbcs_t; + +/* QSPI module registers */ +typedef struct qspi_ctrl { + u16 qmr; /* Mode register */ + u16 res1; + u16 qdlyr; /* Delay register */ + u16 res2; + u16 qwr; /* Wrap register */ + u16 res3; + u16 qir; /* Interrupt register */ + u16 res4; + u16 qar; /* Address register */ + u16 res5; + u16 qdr; /* Data register */ + u16 res6; +} qspi_t; + +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u8 irlr; /* 0x18 */ + u8 iacklpr; /* 0x19 */ + u16 res1[19]; /* 0x1a - 0x3c */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u8 irlr; /* 0x18 */ + u8 iacklpr; /* 0x19 */ + u16 res1[19]; /* 0x1a - 0x3c */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +typedef struct intgack_ctrl1 { + /* Global IACK Registers */ + u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */ + u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */ +} intgack_t; + +/* GPIO port registers */ +typedef struct gpio_ctrl { + /* Port Output Data Registers */ + u8 podr_addr; /* 0x00 */ + u8 podr_datah; /* 0x01 */ + u8 podr_datal; /* 0x02 */ + u8 podr_busctl; /* 0x03 */ + u8 podr_bs; /* 0x04 */ + u8 podr_cs; /* 0x05 */ + u8 podr_sdram; /* 0x06 */ + u8 podr_feci2c; /* 0x07 */ + u8 podr_uarth; /* 0x08 */ + u8 podr_uartl; /* 0x09 */ + u8 podr_qspi; /* 0x0A */ + u8 podr_timer; /* 0x0B */ + u8 podr_etpu; /* 0x0C */ + u8 res1[3]; /* 0x0D - 0x0F */ + + /* Port Data Direction Registers */ + u8 pddr_addr; /* 0x10 */ + u8 pddr_datah; /* 0x11 */ + u8 pddr_datal; /* 0x12 */ + u8 pddr_busctl; /* 0x13 */ + u8 pddr_bs; /* 0x14 */ + u8 pddr_cs; /* 0x15 */ + u8 pddr_sdram; /* 0x16 */ + u8 pddr_feci2c; /* 0x17 */ + u8 pddr_uarth; /* 0x18 */ + u8 pddr_uartl; /* 0x19 */ + u8 pddr_qspi; /* 0x1A */ + u8 pddr_timer; /* 0x1B */ + u8 pddr_etpu; /* 0x1C */ + u8 res2[3]; /* 0x1D - 0x1F */ + + /* Port Data Direction Registers */ + u8 ppdsdr_addr; /* 0x20 */ + u8 ppdsdr_datah; /* 0x21 */ + u8 ppdsdr_datal; /* 0x22 */ + u8 ppdsdr_busctl; /* 0x23 */ + u8 ppdsdr_bs; /* 0x24 */ + u8 ppdsdr_cs; /* 0x25 */ + u8 ppdsdr_sdram; /* 0x26 */ + u8 ppdsdr_feci2c; /* 0x27 */ + u8 ppdsdr_uarth; /* 0x28 */ + u8 ppdsdr_uartl; /* 0x29 */ + u8 ppdsdr_qspi; /* 0x2A */ + u8 ppdsdr_timer; /* 0x2B */ + u8 ppdsdr_etpu; /* 0x2C */ + u8 res3[3]; /* 0x2D - 0x2F */ + + /* Port Clear Output Data Registers */ + u8 pclrr_addr; /* 0x30 */ + u8 pclrr_datah; /* 0x31 */ + u8 pclrr_datal; /* 0x32 */ + u8 pclrr_busctl; /* 0x33 */ + u8 pclrr_bs; /* 0x34 */ + u8 pclrr_cs; /* 0x35 */ + u8 pclrr_sdram; /* 0x36 */ + u8 pclrr_feci2c; /* 0x37 */ + u8 pclrr_uarth; /* 0x38 */ + u8 pclrr_uartl; /* 0x39 */ + u8 pclrr_qspi; /* 0x3A */ + u8 pclrr_timer; /* 0x3B */ + u8 pclrr_etpu; /* 0x3C */ + u8 res4[3]; /* 0x3D - 0x3F */ + + /* Pin Assignment Registers */ + u8 par_ad; /* 0x40 */ + u8 res5; /* 0x41 */ + u16 par_busctl; /* 0x42 */ + u8 par_bs; /* 0x44 */ + u8 par_cs; /* 0x45 */ + u8 par_sdram; /* 0x46 */ + u8 par_feci2c; /* 0x47 */ + u16 par_uart; /* 0x48 */ + u8 par_qspi; /* 0x4A */ + u8 res6; /* 0x4B */ + u16 par_timer; /* 0x4C */ + u8 par_etpu; /* 0x4E */ + u8 res7; /* 0x4F */ + + /* Drive Strength Control Registers */ + u8 dscr_eim; /* 0x50 */ + u8 dscr_etpu; /* 0x51 */ + u8 dscr_feci2c; /* 0x52 */ + u8 dscr_uart; /* 0x53 */ + u8 dscr_qspi; /* 0x54 */ + u8 dscr_timer; /* 0x55 */ + u16 res8; /* 0x56 */ +} gpio_t; + +/*Chip configuration module registers */ +typedef struct ccm_ctrl { + u8 rcr; /* 0x01 */ + u8 rsr; /* 0x02 */ + u16 res1; /* 0x03 */ + u16 ccr; /* 0x04 Chip configuration register */ + u16 lpcr; /* 0x06 Low-power Control register */ + u16 rcon; /* 0x08 Rreset configuration register */ + u16 cir; /* 0x0a Chip identification register */ +} ccm_t; + +/* Clock Module registers */ +typedef struct pll_ctrl { + u32 syncr; /* 0x00 synthesizer control register */ + u32 synsr; /* 0x04 synthesizer status register */ +} pll_t; + +/* Watchdog registers */ +typedef struct wdog_ctrl { + u16 cr; /* 0x00 Control register */ + u16 mr; /* 0x02 Modulus register */ + u16 cntr; /* 0x04 Count register */ + u16 sr; /* 0x06 Service register */ +} wdog_t; + +/* FlexCan module registers */ +typedef struct can_ctrl { + u32 mcr; /* 0x00 Module Configuration register */ + u32 ctrl; /* 0x04 Control register */ + u32 timer; /* 0x08 Free Running Timer */ + u32 res1; /* 0x0C */ + u32 rxgmask; /* 0x10 Rx Global Mask */ + u32 rx14mask; /* 0x14 RxBuffer 14 Mask */ + u32 rx15mask; /* 0x18 RxBuffer 15 Mask */ + u32 errcnt; /* 0x1C Error Counter Register */ + u32 errstat; /* 0x20 Error and status Register */ + u32 res2; /* 0x24 */ + u32 imask; /* 0x28 Interrupt Mask Register */ + u32 res3; /* 0x2C */ + u32 iflag; /* 0x30 Interrupt Flag Register */ + u32 res4[19]; /* 0x34 - 0x7F */ + u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */ +} can_t; + +#endif /* __IMMAP_5235__ */ diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h index a2c1271..6c6fbcc 100644 --- a/include/asm-m68k/immap_5249.h +++ b/include/asm-m68k/immap_5249.h @@ -25,19 +25,11 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__ -/* Timer module registers - */ -typedef struct timer_ctrl { - ushort timer_tmr; - ushort res1; - ushort timer_trr; - ushort res2; - ushort timer_tcap; - ushort res3; - ushort timer_tcn; - ushort res4; - ushort timer_ter; - uchar res5[14]; -} timer_t; +#define MMAP_INTC (CFG_MBAR + 0x00000040) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_MBAR + 0x00000200) +#define MMAP_QSPI (CFG_MBAR + 0x00000400) -#endif /* __IMMAP_5249__ */ +#endif /* __IMMAP_5249__ */ diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h new file mode 100644 index 0000000..aafbdd0 --- /dev/null +++ b/include/asm-m68k/immap_5253.h @@ -0,0 +1,95 @@ +/* + * MCF5253 Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5249__ +#define __IMMAP_5249__ + +#define MMAP_INTC (CFG_MBAR + 0x00000040) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_MBAR + 0x00000200) +#define MMAP_I2C0 (CFG_MBAR + 0x00000280) +#define MMAP_QSPI (CFG_MBAR + 0x00000400) +#define MMAP_CAN0 (CFG_MBAR + 0x00010000) +#define MMAP_CAN1 (CFG_MBAR + 0x00011000) + +#define MMAP_I2C1 (CFG_MBAR2 + 0x00000440) +#define MMAP_UART2 (CFG_MBAR2 + 0x00000C00) + +/********************************************************************* +* ATA Module (ATAC) +*********************************************************************/ + +/* Register read/write struct */ +typedef struct atac { + /* PIO */ + u8 toff; /* 0x00 */ + u8 ton; /* 0x01 */ + u8 t1; /* 0x02 */ + u8 t2w; /* 0x03 */ + u8 t2r; /* 0x04 */ + u8 ta; /* 0x05 */ + u8 trd; /* 0x06 */ + u8 t4; /* 0x07 */ + u8 t9; /* 0x08 */ + + /* DMA */ + u8 tm; /* 0x09 */ + u8 tn; /* 0x0A */ + u8 td; /* 0x0B */ + u8 tk; /* 0x0C */ + u8 tack; /* 0x0D */ + u8 tenv; /* 0x0E */ + u8 trp; /* 0x0F */ + u8 tzah; /* 0x10 */ + u8 tmli; /* 0x11 */ + u8 tdvh; /* 0x12 */ + u8 tdzfs; /* 0x13 */ + u8 tdvs; /* 0x14 */ + u8 tcvh; /* 0x15 */ + u8 tss; /* 0x16 */ + u8 tcyc; /* 0x17 */ + + /* FIFO */ + u32 fifo32; /* 0x18 */ + u16 fifo16; /* 0x1C */ + u8 rsvd0[2]; + u8 ffill; /* 0x20 */ + u8 rsvd1[3]; + + /* ATA */ + u8 cr; /* 0x24 */ + u8 rsvd2[3]; + u8 isr; /* 0x28 */ + u8 rsvd3[3]; + u8 ier; /* 0x2C */ + u8 rsvd4[3]; + u8 icr; /* 0x30 */ + u8 rsvd5[3]; + u8 falarm; /* 0x34 */ +} atac_t; + +#endif /* __IMMAP_5249__ */ diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h index 424dc1d..d9dc015 100644 --- a/include/asm-m68k/immap_5271.h +++ b/include/asm-m68k/immap_5271.h @@ -26,73 +26,73 @@ #ifndef __IMMAP_5271__ #define __IMMAP_5271__ -/* Interrupt module registers -*/ -typedef struct int_ctrl { - uint int_icr1; - uint int_icr2; - uint int_icr3; - uint int_icr4; - uint int_isr; - uint int_pitr; - uint int_piwr; - uchar res1[3]; - uchar int_pivr; -} intctrl_t; +#define MMAP_SCM (CFG_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_MBAR + 0x00000280) +#define MMAP_I2C (CFG_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_MBAR + 0x00100000) +#define MMAP_CCM (CFG_MBAR + 0x00110000) +#define MMAP_PLL (CFG_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_MBAR + 0x00190000) +#define MMAP_RNG (CFG_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_MBAR + 0x001F0000) -/* Timer module registers - */ -typedef struct timer_ctrl { - ushort timer_tmr; - ushort res1; - ushort timer_trr; - ushort res2; - ushort timer_tcap; - ushort res3; - ushort timer_tcn; - ushort res4; - ushort timer_ter; - uchar res5[14]; -} timer_t; - - /* Fast ethernet controller registers - */ -typedef struct fec { - uint res1; - uint fec_ievent; - uint fec_imask; - uint res2; - uint fec_r_des_active; - uint fec_x_des_active; - uint res3[3]; - uint fec_ecntrl; - uint res4[6]; - uint fec_mii_data; - uint fec_mii_speed; - uint res5[7]; - uint fec_mibc; - uint res6[7]; - uint fec_r_cntrl; - uint res7[15]; - uint fec_x_cntrl; - uint res8[7]; - uint fec_addr_low; - uint fec_addr_high; - uint fec_opd; - uint res9[10]; - uint fec_ihash_table_high; - uint fec_ihash_table_low; - uint fec_ghash_table_high; - uint fec_ghash_table_low; - uint res10[7]; - uint fec_tfwr; - uint res11; - uint fec_r_bound; - uint fec_r_fstart; - uint res12[11]; - uint fec_r_des_start; - uint fec_x_des_start; - uint fec_r_buff_size; -} fec_t; +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u8 irlr; /* 0x18 */ + u8 iacklpr; /* 0x19 */ + u16 res1[19]; /* 0x1a - 0x3c */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; -#endif /* __IMMAP_5271__ */ +#endif /* __IMMAP_5271__ */ diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h index ecb4906..2ebb140 100644 --- a/include/asm-m68k/immap_5272.h +++ b/include/asm-m68k/immap_5272.h @@ -25,423 +25,326 @@ #ifndef __IMMAP_5272__ #define __IMMAP_5272__ -/* System configuration registers -*/ -typedef struct sys_ctrl { - uint sc_mbar; - ushort sc_scr; - ushort sc_spr; - uint sc_pmr; - char res1[2]; - ushort sc_alpr; - uint sc_dir; - char res2[12]; +#define MMAP_CFG (CFG_MBAR + 0x00000000) +#define MMAP_INTC (CFG_MBAR + 0x00000020) +#define MMAP_FBCS (CFG_MBAR + 0x00000040) +#define MMAP_GPIO (CFG_MBAR + 0x00000080) +#define MMAP_QSPI (CFG_MBAR + 0x000000A0) +#define MMAP_PWM (CFG_MBAR + 0x000000C0) +#define MMAP_DMA0 (CFG_MBAR + 0x000000E0) +#define MMAP_UART0 (CFG_MBAR + 0x00000100) +#define MMAP_UART1 (CFG_MBAR + 0x00000140) +#define MMAP_SDRAM (CFG_MBAR + 0x00000180) +#define MMAP_TMR0 (CFG_MBAR + 0x00000200) +#define MMAP_TMR1 (CFG_MBAR + 0x00000220) +#define MMAP_TMR2 (CFG_MBAR + 0x00000240) +#define MMAP_TMR3 (CFG_MBAR + 0x00000260) +#define MMAP_WDOG (CFG_MBAR + 0x00000280) +#define MMAP_PLIC (CFG_MBAR + 0x00000300) +#define MMAP_FEC (CFG_MBAR + 0x00000840) +#define MMAP_USB (CFG_MBAR + 0x00001000) + +/* System configuration registers */ +typedef struct sys_ctrl { + uint sc_mbar; + ushort sc_scr; + ushort sc_spr; + uint sc_pmr; + char res1[2]; + ushort sc_alpr; + uint sc_dir; + char res2[12]; } sysctrl_t; -/* Interrupt module registers -*/ +/* Interrupt module registers */ typedef struct int_ctrl { - uint int_icr1; - uint int_icr2; - uint int_icr3; - uint int_icr4; - uint int_isr; - uint int_pitr; - uint int_piwr; - uchar res1[3]; - uchar int_pivr; + uint int_icr1; + uint int_icr2; + uint int_icr3; + uint int_icr4; + uint int_isr; + uint int_pitr; + uint int_piwr; + uchar res1[3]; + uchar int_pivr; } intctrl_t; -/* Chip select module registers. -*/ -typedef struct cs_ctlr { - uint cs_br0; - uint cs_or0; - uint cs_br1; - uint cs_or1; - uint cs_br2; - uint cs_or2; - uint cs_br3; - uint cs_or3; - uint cs_br4; - uint cs_or4; - uint cs_br5; - uint cs_or5; - uint cs_br6; - uint cs_or6; - uint cs_br7; - uint cs_or7; +/* Chip select module registers */ +typedef struct cs_ctlr { + uint cs_br0; + uint cs_or0; + uint cs_br1; + uint cs_or1; + uint cs_br2; + uint cs_or2; + uint cs_br3; + uint cs_or3; + uint cs_br4; + uint cs_or4; + uint cs_br5; + uint cs_or5; + uint cs_br6; + uint cs_or6; + uint cs_br7; + uint cs_or7; } csctrl_t; -/* GPIO port registers -*/ -typedef struct gpio_ctrl { - uint gpio_pacnt; - ushort gpio_paddr; - ushort gpio_padat; - uint gpio_pbcnt; - ushort gpio_pbddr; - ushort gpio_pbdat; - uchar res1[4]; - ushort gpio_pcddr; - ushort gpio_pcdat; - uint gpio_pdcnt; - uchar res2[4]; +/* GPIO port registers */ +typedef struct gpio_ctrl { + uint gpio_pacnt; + ushort gpio_paddr; + ushort gpio_padat; + uint gpio_pbcnt; + ushort gpio_pbddr; + ushort gpio_pbdat; + uchar res1[4]; + ushort gpio_pcddr; + ushort gpio_pcdat; + uint gpio_pdcnt; + uchar res2[4]; } gpio_t; -/* QSPI module registers - */ -typedef struct qspi_ctrl { - ushort qspi_qmr; - uchar res1[2]; - ushort qspi_qdlyr; - uchar res2[2]; - ushort qspi_qwr; - uchar res3[2]; - ushort qspi_qir; - uchar res4[2]; - ushort qspi_qar; - uchar res5[2]; - ushort qspi_qdr; - uchar res6[10]; +/* QSPI module registers */ +typedef struct qspi_ctrl { + ushort qspi_qmr; + uchar res1[2]; + ushort qspi_qdlyr; + uchar res2[2]; + ushort qspi_qwr; + uchar res3[2]; + ushort qspi_qir; + uchar res4[2]; + ushort qspi_qar; + uchar res5[2]; + ushort qspi_qdr; + uchar res6[10]; } qspi_t; -/* PWM module registers - */ -typedef struct pwm_ctrl { - uchar pwm_pwcr0; - uchar res1[3]; - uchar pwm_pwcr1; - uchar res2[3]; - uchar pwm_pwcr2; - uchar res3[7]; - uchar pwm_pwwd0; - uchar res4[3]; - uchar pwm_pwwd1; - uchar res5[3]; - uchar pwm_pwwd2; - uchar res6[7]; +/* PWM module registers */ +typedef struct pwm_ctrl { + uchar pwm_pwcr0; + uchar res1[3]; + uchar pwm_pwcr1; + uchar res2[3]; + uchar pwm_pwcr2; + uchar res3[7]; + uchar pwm_pwwd0; + uchar res4[3]; + uchar pwm_pwwd1; + uchar res5[3]; + uchar pwm_pwwd2; + uchar res6[7]; } pwm_t; -/* DMA module registers - */ -typedef struct dma_ctrl { - ulong dma_dmr; - uchar res1[2]; - ushort dma_dir; - ulong dma_dbcr; - ulong dma_dsar; - ulong dma_ddar; - uchar res2[12]; +/* DMA module registers */ +typedef struct dma_ctrl { + ulong dma_dmr; + uchar res1[2]; + ushort dma_dir; + ulong dma_dbcr; + ulong dma_dsar; + ulong dma_ddar; + uchar res2[12]; } dma_t; -/* UART module registers - */ -typedef struct uart_ctrl { - uchar uart_umr; - uchar res1[3]; - uchar uart_usr_ucsr; - uchar res2[3]; - uchar uart_ucr; - uchar res3[3]; - uchar uart_urb_utb; - uchar res4[3]; - uchar uart_uipcr_uacr; - uchar res5[3]; - uchar uart_uisr_uimr; - uchar res6[3]; - uchar uart_udu; - uchar res7[3]; - uchar uart_udl; - uchar res8[3]; - uchar uart_uabu; - uchar res9[3]; - uchar uart_uabl; - uchar res10[3]; - uchar uart_utf; - uchar res11[3]; - uchar uart_urf; - uchar res12[3]; - uchar uart_ufpd; - uchar res13[3]; - uchar uart_uip; - uchar res14[3]; - uchar uart_uop1; - uchar res15[3]; - uchar uart_uop0; - uchar res16[3]; -} uart_t; - -/* SDRAM controller registers, offset: 0x180 - */ +/* SDRAM controller registers, offset: 0x180 */ typedef struct sdram_ctrl { - uchar res1[2]; - ushort sdram_sdcr; - uchar res2[2]; - ushort sdram_sdtr; - uchar res3[120]; + uchar res1[2]; + ushort sdram_sdcr; + uchar res2[2]; + ushort sdram_sdtr; + uchar res3[120]; } sdramctrl_t; -/* Timer module registers - */ -typedef struct timer_ctrl { - ushort timer_tmr; - ushort res1; - ushort timer_trr; - ushort res2; - ushort timer_tcap; - ushort res3; - ushort timer_tcn; - ushort res4; - ushort timer_ter; - uchar res5[14]; -} timer_t; - -/* Watchdog registers - */ +/* Watchdog registers */ typedef struct wdog_ctrl { - ushort wdog_wrrr; - ushort res1; - ushort wdog_wirr; - ushort res2; - ushort wdog_wcr; - ushort res3; - ushort wdog_wer; - uchar res4[114]; + ushort wdog_wrrr; + ushort res1; + ushort wdog_wirr; + ushort res2; + ushort wdog_wcr; + ushort res3; + ushort wdog_wer; + uchar res4[114]; } wdog_t; -/* PLIC module registers - */ +/* PLIC module registers */ typedef struct plic_ctrl { - ulong plic_p0b1rr; - ulong plic_p1b1rr; - ulong plic_p2b1rr; - ulong plic_p3b1rr; - ulong plic_p0b2rr; - ulong plic_p1b2rr; - ulong plic_p2b2rr; - ulong plic_p3b2rr; - uchar plic_p0drr; - uchar plic_p1drr; - uchar plic_p2drr; - uchar plic_p3drr; - uchar res1[4]; - ulong plic_p0b1tr; - ulong plic_p1b1tr; - ulong plic_p2b1tr; - ulong plic_p3b1tr; - ulong plic_p0b2tr; - ulong plic_p1b2tr; - ulong plic_p2b2tr; - ulong plic_p3b2tr; - uchar plic_p0dtr; - uchar plic_p1dtr; - uchar plic_p2dtr; - uchar plic_p3dtr; - uchar res2[4]; - ushort plic_p0cr; - ushort plic_p1cr; - ushort plic_p2cr; - ushort plic_p3cr; - ushort plic_p0icr; - ushort plic_p1icr; - ushort plic_p2icr; - ushort plic_p3icr; - ushort plic_p0gmr; - ushort plic_p1gmr; - ushort plic_p2gmr; - ushort plic_p3gmr; - ushort plic_p0gmt; - ushort plic_p1gmt; - ushort plic_p2gmt; - ushort plic_p3gmt; - uchar res3; - uchar plic_pgmts; - uchar plic_pgmta; - uchar res4; - uchar plic_p0gcir; - uchar plic_p1gcir; - uchar plic_p2gcir; - uchar plic_p3gcir; - uchar plic_p0gcit; - uchar plic_p1gcit; - uchar plic_p2gcit; - uchar plic_p3gcit; - uchar res5[3]; - uchar plic_pgcitsr; - uchar res6[3]; - uchar plic_pdcsr; - ushort plic_p0psr; - ushort plic_p1psr; - ushort plic_p2psr; - ushort plic_p3psr; - ushort plic_pasr; - uchar res7; - uchar plic_plcr; - ushort res8; - ushort plic_pdrqr; - ushort plic_p0sdr; - ushort plic_p1sdr; - ushort plic_p2sdr; - ushort plic_p3sdr; - ushort res9; - ushort plic_pcsr; - uchar res10[1184]; + ulong plic_p0b1rr; + ulong plic_p1b1rr; + ulong plic_p2b1rr; + ulong plic_p3b1rr; + ulong plic_p0b2rr; + ulong plic_p1b2rr; + ulong plic_p2b2rr; + ulong plic_p3b2rr; + uchar plic_p0drr; + uchar plic_p1drr; + uchar plic_p2drr; + uchar plic_p3drr; + uchar res1[4]; + ulong plic_p0b1tr; + ulong plic_p1b1tr; + ulong plic_p2b1tr; + ulong plic_p3b1tr; + ulong plic_p0b2tr; + ulong plic_p1b2tr; + ulong plic_p2b2tr; + ulong plic_p3b2tr; + uchar plic_p0dtr; + uchar plic_p1dtr; + uchar plic_p2dtr; + uchar plic_p3dtr; + uchar res2[4]; + ushort plic_p0cr; + ushort plic_p1cr; + ushort plic_p2cr; + ushort plic_p3cr; + ushort plic_p0icr; + ushort plic_p1icr; + ushort plic_p2icr; + ushort plic_p3icr; + ushort plic_p0gmr; + ushort plic_p1gmr; + ushort plic_p2gmr; + ushort plic_p3gmr; + ushort plic_p0gmt; + ushort plic_p1gmt; + ushort plic_p2gmt; + ushort plic_p3gmt; + uchar res3; + uchar plic_pgmts; + uchar plic_pgmta; + uchar res4; + uchar plic_p0gcir; + uchar plic_p1gcir; + uchar plic_p2gcir; + uchar plic_p3gcir; + uchar plic_p0gcit; + uchar plic_p1gcit; + uchar plic_p2gcit; + uchar plic_p3gcit; + uchar res5[3]; + uchar plic_pgcitsr; + uchar res6[3]; + uchar plic_pdcsr; + ushort plic_p0psr; + ushort plic_p1psr; + ushort plic_p2psr; + ushort plic_p3psr; + ushort plic_pasr; + uchar res7; + uchar plic_plcr; + ushort res8; + ushort plic_pdrqr; + ushort plic_p0sdr; + ushort plic_p1sdr; + ushort plic_p2sdr; + ushort plic_p3sdr; + ushort res9; + ushort plic_pcsr; + uchar res10[1184]; } plic_t; -/* Fast ethernet controller registers - */ -typedef struct fec { - uint fec_ecntrl; /* ethernet control register */ - uint fec_ievent; /* interrupt event register */ - uint fec_imask; /* interrupt mask register */ - uint fec_ivec; /* interrupt level and vector status */ - uint fec_r_des_active; /* Rx ring updated flag */ - uint fec_x_des_active; /* Tx ring updated flag */ - uint res3[10]; /* reserved */ - uint fec_mii_data; /* MII data register */ - uint fec_mii_speed; /* MII speed control register */ - uint res4[17]; /* reserved */ - uint fec_r_bound; /* end of RAM (read-only) */ - uint fec_r_fstart; /* Rx FIFO start address */ - uint res5[6]; /* reserved */ - uint fec_x_fstart; /* Tx FIFO start address */ - uint res7[21]; /* reserved */ - uint fec_r_cntrl; /* Rx control register */ - uint fec_r_hash; /* Rx hash register */ - uint res8[14]; /* reserved */ - uint fec_x_cntrl; /* Tx control register */ - uint res9[0x9e]; /* reserved */ - uint fec_addr_low; /* lower 32 bits of station address */ - uint fec_addr_high; /* upper 16 bits of station address */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ - uint fec_r_des_start; /* beginning of Rx descriptor ring */ - uint fec_x_des_start; /* beginning of Tx descriptor ring */ - uint fec_r_buff_size; /* Rx buffer size */ - uint res2[9]; /* reserved */ - uchar fec_fifo[960]; /* fifo RAM */ -} fec_t; - -/* USB module registers -*/ +/* USB module registers */ typedef struct usb { - ushort res1; - ushort usb_fnr; - ushort res2; - ushort usb_fnmr; - ushort res3; - ushort usb_rfmr; - ushort res4; - ushort usb_rfmmr; - uchar res5[3]; - uchar usb_far; - ulong usb_asr; - ulong usb_drr1; - ulong usb_drr2; - ushort res6; - ushort usb_specr; - ushort res7; - ushort usb_ep0sr; - ulong usb_iep0cfg; - ulong usb_oep0cfg; - ulong usb_ep1cfg; - ulong usb_ep2cfg; - ulong usb_ep3cfg; - ulong usb_ep4cfg; - ulong usb_ep5cfg; - ulong usb_ep6cfg; - ulong usb_ep7cfg; - ulong usb_ep0ctl; - ushort res8; - ushort usb_ep1ctl; - ushort res9; - ushort usb_ep2ctl; - ushort res10; - ushort usb_ep3ctl; - ushort res11; - ushort usb_ep4ctl; - ushort res12; - ushort usb_ep5ctl; - ushort res13; - ushort usb_ep6ctl; - ushort res14; - ushort usb_ep7ctl; - ulong usb_ep0isr; - ushort res15; - ushort usb_ep1isr; - ushort res16; - ushort usb_ep2isr; - ushort res17; - ushort usb_ep3isr; - ushort res18; - ushort usb_ep4isr; - ushort res19; - ushort usb_ep5isr; - ushort res20; - ushort usb_ep6isr; - ushort res21; - ushort usb_ep7isr; - ulong usb_ep0imr; - ushort res22; - ushort usb_ep1imr; - ushort res23; - ushort usb_ep2imr; - ushort res24; - ushort usb_ep3imr; - ushort res25; - ushort usb_ep4imr; - ushort res26; - ushort usb_ep5imr; - ushort res27; - ushort usb_ep6imr; - ushort res28; - ushort usb_ep7imr; - ulong usb_ep0dr; - ulong usb_ep1dr; - ulong usb_ep2dr; - ulong usb_ep3dr; - ulong usb_ep4dr; - ulong usb_ep5dr; - ulong usb_ep6dr; - ulong usb_ep7dr; - ushort res29; - ushort usb_ep0dpr; - ushort res30; - ushort usb_ep1dpr; - ushort res31; - ushort usb_ep2dpr; - ushort res32; - ushort usb_ep3dpr; - ushort res33; - ushort usb_ep4dpr; - ushort res34; - ushort usb_ep5dpr; - ushort res35; - ushort usb_ep6dpr; - ushort res36; - ushort usb_ep7dpr; - uchar res37[788]; - uchar usb_cfgram[1024]; + ushort res1; + ushort usb_fnr; + ushort res2; + ushort usb_fnmr; + ushort res3; + ushort usb_rfmr; + ushort res4; + ushort usb_rfmmr; + uchar res5[3]; + uchar usb_far; + ulong usb_asr; + ulong usb_drr1; + ulong usb_drr2; + ushort res6; + ushort usb_specr; + ushort res7; + ushort usb_ep0sr; + ulong usb_iep0cfg; + ulong usb_oep0cfg; + ulong usb_ep1cfg; + ulong usb_ep2cfg; + ulong usb_ep3cfg; + ulong usb_ep4cfg; + ulong usb_ep5cfg; + ulong usb_ep6cfg; + ulong usb_ep7cfg; + ulong usb_ep0ctl; + ushort res8; + ushort usb_ep1ctl; + ushort res9; + ushort usb_ep2ctl; + ushort res10; + ushort usb_ep3ctl; + ushort res11; + ushort usb_ep4ctl; + ushort res12; + ushort usb_ep5ctl; + ushort res13; + ushort usb_ep6ctl; + ushort res14; + ushort usb_ep7ctl; + ulong usb_ep0isr; + ushort res15; + ushort usb_ep1isr; + ushort res16; + ushort usb_ep2isr; + ushort res17; + ushort usb_ep3isr; + ushort res18; + ushort usb_ep4isr; + ushort res19; + ushort usb_ep5isr; + ushort res20; + ushort usb_ep6isr; + ushort res21; + ushort usb_ep7isr; + ulong usb_ep0imr; + ushort res22; + ushort usb_ep1imr; + ushort res23; + ushort usb_ep2imr; + ushort res24; + ushort usb_ep3imr; + ushort res25; + ushort usb_ep4imr; + ushort res26; + ushort usb_ep5imr; + ushort res27; + ushort usb_ep6imr; + ushort res28; + ushort usb_ep7imr; + ulong usb_ep0dr; + ulong usb_ep1dr; + ulong usb_ep2dr; + ulong usb_ep3dr; + ulong usb_ep4dr; + ulong usb_ep5dr; + ulong usb_ep6dr; + ulong usb_ep7dr; + ushort res29; + ushort usb_ep0dpr; + ushort res30; + ushort usb_ep1dpr; + ushort res31; + ushort usb_ep2dpr; + ushort res32; + ushort usb_ep3dpr; + ushort res33; + ushort usb_ep4dpr; + ushort res34; + ushort usb_ep5dpr; + ushort res35; + ushort usb_ep6dpr; + ushort res36; + ushort usb_ep7dpr; + uchar res37[788]; + uchar usb_cfgram[1024]; } usb_t; -/* Internal memory map. -*/ -typedef struct immap { - sysctrl_t sysctrl_reg; /* System configuration registers */ - intctrl_t intctrl_reg; /* Interrupt controller registers */ - csctrl_t csctrl_reg; /* Chip select controller registers */ - gpio_t gpio_reg; /* GPIO controller registers */ - qspi_t qspi_reg; /* QSPI controller registers */ - pwm_t pwm_reg; /* Pulse width modulation registers */ - dma_t dma_reg; /* DMA registers */ - uart_t uart_reg[2]; /* UART registers */ - sdramctrl_t sdram_reg; /* SDRAM controller registers */ - timer_t timer_reg[4]; /* Timer registers */ - wdog_t wdog_reg; /* Watchdog registers */ - plic_t plic_reg; /* Physical layer interface registers */ - fec_t fec_reg; /* Fast ethernet controller registers */ - usb_t usb_reg; /* USB controller registers */ -} immap_t; - -#endif /* __IMMAP_5272__ */ +#endif /* __IMMAP_5272__ */ diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h index 6553b08..e82960a 100644 --- a/include/asm-m68k/immap_5282.h +++ b/include/asm-m68k/immap_5282.h @@ -25,61 +25,168 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__ -struct sys_ctrl { - uint ipsbar; - char res1[4]; - uint rambar; - char res2[4]; - uchar crsr; - uchar cwcr; - uchar lpicr; - uchar cwsr; - uint dmareqc; - char res3[4]; - uint mpark; +#define MMAP_SCM (CFG_MBAR + 0x00000000) +#define MMAP_SDRAMC (CFG_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_MBAR + 0x00000140) +#define MMAP_DMA2 (CFG_MBAR + 0x00000180) +#define MMAP_DMA3 (CFG_MBAR + 0x000001C0) +#define MMAP_UART0 (CFG_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_MBAR + 0x00000280) +#define MMAP_I2C (CFG_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_MBAR + 0x00100000) +#define MMAP_CCM (CFG_MBAR + 0x00110000) +#define MMAP_PLL (CFG_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_MBAR + 0x00180000) +#define MMAP_QADC (CFG_MBAR + 0x00190000) +#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000) +#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000) +#define MMAP_CAN (CFG_MBAR + 0x001C0000) +#define MMAP_CFMC (CFG_MBAR + 0x001D0000) +#define MMAP_CFMMEM (CFG_MBAR + 0x04000000) - /* TODO: finish these */ -}; +/* System Control Module */ +typedef struct scm_ctrl { + u32 ipsbar; + u32 res1; + u32 rambar; + u32 res2; + u8 crsr; + u8 cwcr; + u8 lpicr; + u8 cwsr; + u32 res3; + u8 mpark; + u8 res4[3]; + u8 pacr0; + u8 pacr1; + u8 pacr2; + u8 pacr3; + u8 pacr4; + u8 res5; + u8 pacr5; + u8 pacr6; + u8 pacr7; + u8 res6; + u8 pacr8; + u8 res7; + u8 gpacr0; + u8 gpacr1; + u16 res8; +} scm_t; -/* Fast ethernet controller registers - */ -typedef struct fec { - uint res1; /* reserved 1000*/ - uint fec_ievent; /* interrupt event register 1004*/ /* EIR */ - uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */ - uint res2; /* reserved 100c*/ - uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */ - uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */ - uint res3[3]; /* reserved 1018*/ - uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */ - uint res4[6]; /* reserved 1028*/ - uint fec_mii_data; /* MII data register 1040*/ /* MDATA */ - uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */ - /*1044*/ - uint res5[7]; /* reserved 1048*/ - uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */ - uint res6[7]; /* reserved 1068*/ - uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */ - uint res7[15]; /* reserved 1088*/ - uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */ - uint res8[7]; /* reserved 10C8*/ - uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */ - uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */ - uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */ - uint res9[10]; /* reserved 10F0*/ - uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */ - uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */ - uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */ - uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */ - uint res10[7]; /* reserved 1128*/ - uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */ - uint res11; /* reserved 1148*/ - uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */ - uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */ - uint res12[11]; /* reserved 1154*/ - uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */ - uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */ - uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */ -} fec_t; +/* Flexbus module Chip select registers */ +typedef struct fbcs_ctrl { + u16 csar0; /* 0x00 Chip-Select Address Register 0 */ + u16 res0; + u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ + u16 res1; /* 0x08 */ + u16 cscr0; /* 0x0A Chip-Select Control Register 0 */ + + u16 csar1; /* 0x0C Chip-Select Address Register 1 */ + u16 res2; + u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ + u16 res3; /* 0x14 */ + u16 cscr1; /* 0x16 Chip-Select Control Register 1 */ + + u16 csar2; /* 0x18 Chip-Select Address Register 2 */ + u16 res4; + u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ + u16 res5; /* 0x20 */ + u16 cscr2; /* 0x22 Chip-Select Control Register 2 */ + + u16 csar3; /* 0x24 Chip-Select Address Register 3 */ + u16 res6; + u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ + u16 res7; /* 0x2C */ + u16 cscr3; /* 0x2E Chip-Select Control Register 3 */ + + u16 csar4; /* 0x30 Chip-Select Address Register 4 */ + u16 res8; + u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ + u16 res9; /* 0x38 */ + u16 cscr4; /* 0x3A Chip-Select Control Register 4 */ + + u16 csar5; /* 0x3C Chip-Select Address Register 5 */ + u16 res10; + u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ + u16 res11; /* 0x44 */ + u16 cscr5; /* 0x46 Chip-Select Control Register 5 */ + + u16 csar6; /* 0x48 Chip-Select Address Register 5 */ + u16 res12; + u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */ + u16 res13; /* 0x50 */ + u16 cscr6; /* 0x52 Chip-Select Control Register 5 */ + + u16 csar7; /* 0x54 Chip-Select Address Register 5 */ + u16 res14; + u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */ + u16 res15; /* 0x5C */ + u16 cscr7; /* 0x5E Chip-Select Control Register 5 */ +} fbcs_t; + +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u8 irlr; /* 0x18 */ + u8 iacklpr; /* 0x19 */ + u16 res1[19]; /* 0x1a - 0x3c */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +/* Clock Module registers */ +typedef struct pll_ctrl { + u16 syncr; /* 0x00 synthesizer control register */ + u16 synsr; /* 0x02 synthesizer status register */ +} pll_t; + +/* Watchdog registers */ +typedef struct wdog_ctrl { + ushort wcr; + ushort wmr; + ushort wcntr; + ushort wsr; +} wdog_t; -#endif /* __IMMAP_5282__ */ +#endif /* __IMMAP_5282__ */ diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h new file mode 100644 index 0000000..2a3980c --- /dev/null +++ b/include/asm-m68k/immap_5329.h @@ -0,0 +1,793 @@ +/* + * MCF5329 Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5329__ +#define __IMMAP_5329__ + +#define MMAP_SCM1 0xEC000000 +#define MMAP_MDHA 0xEC080000 +#define MMAP_SKHA 0xEC084000 +#define MMAP_RNG 0xEC088000 +#define MMAP_SCM2 0xFC000000 +#define MMAP_XBS 0xFC004000 +#define MMAP_FBCS 0xFC008000 +#define MMAP_CAN 0xFC020000 +#define MMAP_FEC 0xFC030000 +#define MMAP_SCM3 0xFC040000 +#define MMAP_EDMA 0xFC044000 +#define MMAP_TCD 0xFC045000 +#define MMAP_INTC0 0xFC048000 +#define MMAP_INTC1 0xFC04C000 +#define MMAP_INTCACK 0xFC054000 +#define MMAP_I2C 0xFC058000 +#define MMAP_QSPI 0xFC05C000 +#define MMAP_UART0 0xFC060000 +#define MMAP_UART1 0xFC064000 +#define MMAP_UART2 0xFC068000 +#define MMAP_DTMR0 0xFC070000 +#define MMAP_DTMR1 0xFC074000 +#define MMAP_DTMR2 0xFC078000 +#define MMAP_DTMR3 0xFC07C000 +#define MMAP_PIT0 0xFC080000 +#define MMAP_PIT1 0xFC084000 +#define MMAP_PIT2 0xFC088000 +#define MMAP_PIT3 0xFC08C000 +#define MMAP_PWM 0xFC090000 +#define MMAP_EPORT 0xFC094000 +#define MMAP_WDOG 0xFC098000 +#define MMAP_CCM 0xFC0A0000 +#define MMAP_GPIO 0xFC0A4000 +#define MMAP_RTC 0xFC0A8000 +#define MMAP_LCDC 0xFC0AC000 +#define MMAP_USBOTG 0xFC0B0000 +#define MMAP_USBH 0xFC0B4000 +#define MMAP_SDRAM 0xFC0B8000 +#define MMAP_SSI 0xFC0BC000 +#define MMAP_PLL 0xFC0C0000 + +/* System control module registers */ +typedef struct scm1_ctrl { + u32 mpr0; /* 0x00 Master Privilege Register 0 */ + u32 res1[15]; /* 0x04 - 0x3F */ + u32 pacrh; /* 0x40 Peripheral Access Control Register H */ + u32 res2[3]; /* 0x44 - 0x53 */ + u32 bmt0; /*0x54 Bus Monitor Timeout 0 */ +} scm1_t; + +/* Message Digest Hardware Accelerator */ +typedef struct mdha_ctrl { + u32 mdmr; /* 0x00 MDHA Mode Register */ + u32 mdcr; /* 0x04 Control register */ + u32 mdcmr; /* 0x08 Command Register */ + u32 mdsr; /* 0x0C Status Register */ + u32 mdisr; /* 0x10 Interrupt Status Register */ + u32 mdimr; /* 0x14 Interrupt Mask Register */ + u32 mddsr; /* 0x1C Data Size Register */ + u32 mdin; /* 0x20 Input FIFO */ + u32 res1[3]; /* 0x24 - 0x2F */ + u32 mdao; /* 0x30 Message Digest AO Register */ + u32 mdbo; /* 0x34 Message Digest BO Register */ + u32 mdco; /* 0x38 Message Digest CO Register */ + u32 mddo; /* 0x3C Message Digest DO Register */ + u32 mdeo; /* 0x40 Message Digest EO Register */ + u32 mdmds; /* 0x44 Message Data Size Register */ + u32 res[10]; /* 0x48 - 0x6F */ + u32 mda1; /* 0x70 Message Digest A1 Register */ + u32 mdb1; /* 0x74 Message Digest B1 Register */ + u32 mdc1; /* 0x78 Message Digest C1 Register */ + u32 mdd1; /* 0x7C Message Digest D1 Register */ + u32 mde1; /* 0x80 Message Digest E1 Register */ +} mdha_t; + +/* Symmetric Key Hardware Accelerator */ +typedef struct skha_ctrl { + u32 mr; /* 0x00 Mode Register */ + u32 cr; /* 0x04 Control Register */ + u32 cmr; /* 0x08 Command Register */ + u32 sr; /* 0x0C Status Register */ + u32 esr; /* 0x10 Error Status Register */ + u32 emr; /* 0x14 Error Status Mask Register) */ + u32 ksr; /* 0x18 Key Size Register */ + u32 dsr; /* 0x1C Data Size Register */ + u32 in; /* 0x20 Input FIFO */ + u32 out; /* 0x24 Output FIFO */ + u32 res1[2]; /* 0x28 - 0x2F */ + u32 kdr1; /* 0x30 Key Data Register 1 */ + u32 kdr2; /* 0x34 Key Data Register 2 */ + u32 kdr3; /* 0x38 Key Data Register 3 */ + u32 kdr4; /* 0x3C Key Data Register 4 */ + u32 kdr5; /* 0x40 Key Data Register 5 */ + u32 kdr6; /* 0x44 Key Data Register 6 */ + u32 res2[10]; /* 0x48 - 0x6F */ + u32 c1; /* 0x70 Context 1 */ + u32 c2; /* 0x74 Context 2 */ + u32 c3; /* 0x78 Context 3 */ + u32 c4; /* 0x7C Context 4 */ + u32 c5; /* 0x80 Context 5 */ + u32 c6; /* 0x84 Context 6 */ + u32 c7; /* 0x88 Context 7 */ + u32 c8; /* 0x8C Context 8 */ + u32 c9; /* 0x90 Context 9 */ + u32 c10; /* 0x94 Context 10 */ + u32 c11; /* 0x98 Context 11 */ +} skha_t; + +/* Random Number Generator */ +typedef struct rng_ctrl { + u32 rngcr; /* 0x00 RNG Control Register */ + u32 rngsr; /* 0x04 RNG Status Register */ + u32 rnger; /* 0x08 RNG Entropy Register */ + u32 rngout; /* 0x0C RNG Output FIFO */ +} rng_t; + +/* System control module registers 2 */ +typedef struct scm2_ctrl { + u32 mpr1; /* 0x00 Master Privilege Register */ + u32 res1[7]; /* 0x04 - 0x1F */ + u32 pacra; /* 0x20 Peripheral Access Control Register A */ + u32 pacrb; /* 0x24 Peripheral Access Control Register B */ + u32 pacrc; /* 0x28 Peripheral Access Control Register C */ + u32 pacrd; /* 0x2C Peripheral Access Control Register D */ + u32 res2[4]; /* 0x30 - 0x3F */ + u32 pacre; /* 0x40 Peripheral Access Control Register E */ + u32 pacrf; /* 0x44 Peripheral Access Control Register F */ + u32 pacrg; /* 0x48 Peripheral Access Control Register G */ + u32 res3[2]; /* 0x4C - 0x53 */ + u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */ +} scm2_t; + +/* Cross-Bar Switch Module */ +typedef struct xbs_ctrl { + u32 prs1; /* 0x100 Priority Register Slave 1 */ + u32 res1[3]; /* 0x104 - 0F */ + u32 crs1; /* 0x110 Control Register Slave 1 */ + u32 res2[187]; /* 0x114 - 0x3FF */ + + u32 prs4; /* 0x400 Priority Register Slave 4 */ + u32 res3[3]; /* 0x404 - 0F */ + u32 crs4; /* 0x410 Control Register Slave 4 */ + u32 res4[123]; /* 0x414 - 0x5FF */ + + u32 prs6; /* 0x600 Priority Register Slave 6 */ + u32 res5[3]; /* 0x604 - 0F */ + u32 crs6; /* 0x610 Control Register Slave 6 */ + u32 res6[59]; /* 0x614 - 0x6FF */ + + u32 prs7; /* 0x700 Priority Register Slave 7 */ + u32 res7[3]; /* 0x704 - 0F */ + u32 crs7; /* 0x710 Control Register Slave 7 */ +} xbs_t; + +/* Flexbus module Chip select registers */ +typedef struct fbcs_ctrl { + u16 csar0; /* 0x00 Chip-Select Address Register 0 */ + u16 res0; + u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ + u32 cscr0; /* 0x08 Chip-Select Control Register 0 */ + + u16 csar1; /* 0x0C Chip-Select Address Register 1 */ + u16 res1; + u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ + u32 cscr1; /* 0x14 Chip-Select Control Register 1 */ + + u16 csar2; /* 0x18 Chip-Select Address Register 2 */ + u16 res2; + u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ + u32 cscr2; /* 0x20 Chip-Select Control Register 2 */ + + u16 csar3; /* 0x24 Chip-Select Address Register 3 */ + u16 res3; + u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ + u32 cscr3; /* 0x2C Chip-Select Control Register 3 */ + + u16 csar4; /* 0x30 Chip-Select Address Register 4 */ + u16 res4; + u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ + u32 cscr4; /* 0x38 Chip-Select Control Register 4 */ + + u16 csar5; /* 0x3C Chip-Select Address Register 5 */ + u16 res5; + u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ + u32 cscr5; /* 0x44 Chip-Select Control Register 5 */ +} fbcs_t; + +/* FlexCan module registers */ +typedef struct can_ctrl { + u32 mcr; /* 0x00 Module Configuration register */ + u32 ctrl; /* 0x04 Control register */ + u32 timer; /* 0x08 Free Running Timer */ + u32 res1; /* 0x0C */ + u32 rxgmask; /* 0x10 Rx Global Mask */ + u32 rx14mask; /* 0x14 RxBuffer 14 Mask */ + u32 rx15mask; /* 0x18 RxBuffer 15 Mask */ + u32 errcnt; /* 0x1C Error Counter Register */ + u32 errstat; /* 0x20 Error and status Register */ + u32 res2; /* 0x24 */ + u32 imask; /* 0x28 Interrupt Mask Register */ + u32 res3; /* 0x2C */ + u32 iflag; /* 0x30 Interrupt Flag Register */ + u32 res4[19]; /* 0x34 - 0x7F */ + u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */ +} can_t; + +/* System Control Module register 3 */ +typedef struct scm3_ctrl { + u8 res1[19]; /* 0x00 - 0x12 */ + u8 wcr; /* 0x13 wakeup control register */ + u16 res2; /* 0x14 - 0x15 */ + u16 cwcr; /* 0x16 Core Watchdog Control Register */ + u8 res3[3]; /* 0x18 - 0x1A */ + u8 cwsr; /* 0x1B Core Watchdog Service Register */ + u8 res4[2]; /* 0x1C - 0x1D */ + u8 scmisr; /* 0x1F Interrupt Status Register */ + u32 res5; /* 0x20 */ + u32 bcr; /* 0x24 Burst Configuration Register */ + u32 res6[18]; /* 0x28 - 0x6F */ + u32 cfadr; /* 0x70 Core Fault Address Register */ + u8 res7[4]; /* 0x71 - 0x74 */ + u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */ + u8 cfloc; /* 0x76 Core Fault Location Register */ + u8 cfatr; /* 0x77 Core Fault Attributes Register */ + u32 res8; /* 0x78 */ + u32 cfdtr; /* 0x7C Core Fault Data Register */ +} scm3_t; + +/* eDMA module registers */ +typedef struct edma_ctrl { + u32 cr; /* 0x00 Control Register */ + u32 es; /* 0x04 Error Status Register */ + u16 res1[3]; /* 0x08 - 0x0D */ + u16 erq; /* 0x0E Enable Request Register */ + u16 res2[3]; /* 0x10 - 0x15 */ + u16 eei; /* 0x16 Enable Error Interrupt Request */ + u8 serq; /* 0x18 Set Enable Request */ + u8 cerq; /* 0x19 Clear Enable Request */ + u8 seei; /* 0x1A Set Enable Error Interrupt Request */ + u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */ + u8 cint; /* 0x1C Clear Interrupt Enable Register */ + u8 cerr; /* 0x1D Clear Error Register */ + u8 ssrt; /* 0x1E Set START Bit Register */ + u8 cdne; /* 0x1F Clear DONE Status Bit Register */ + u16 res3[3]; /* 0x20 - 0x25 */ + u16 intr; /* 0x26 Interrupt Request Register */ + u16 res4[3]; /* 0x28 - 0x2D */ + u16 err; /* 0x2E Error Register */ + u32 res5[52]; /* 0x30 - 0xFF */ + u8 dchpri0; /* 0x100 Channel 0 Priority Register */ + u8 dchpri1; /* 0x101 Channel 1 Priority Register */ + u8 dchpri2; /* 0x102 Channel 2 Priority Register */ + u8 dchpri3; /* 0x103 Channel 3 Priority Register */ + u8 dchpri4; /* 0x104 Channel 4 Priority Register */ + u8 dchpri5; /* 0x105 Channel 5 Priority Register */ + u8 dchpri6; /* 0x106 Channel 6 Priority Register */ + u8 dchpri7; /* 0x107 Channel 7 Priority Register */ + u8 dchpri8; /* 0x108 Channel 8 Priority Register */ + u8 dchpri9; /* 0x109 Channel 9 Priority Register */ + u8 dchpri10; /* 0x110 Channel 10 Priority Register */ + u8 dchpri11; /* 0x111 Channel 11 Priority Register */ + u8 dchpri12; /* 0x112 Channel 12 Priority Register */ + u8 dchpri13; /* 0x113 Channel 13 Priority Register */ + u8 dchpri14; /* 0x114 Channel 14 Priority Register */ + u8 dchpri15; /* 0x115 Channel 15 Priority Register */ +} edma_t; + +/* TCD - eDMA*/ +typedef struct tcd_ctrl { + u32 saddr; /* 0x00 Source Address */ + u16 attr; /* 0x04 Transfer Attributes */ + u16 soff; /* 0x06 Signed Source Address Offset */ + u32 nbytes; /* 0x08 Minor Byte Count */ + u32 slast; /* 0x0C Last Source Address Adjustment */ + u32 daddr; /* 0x10 Destination address */ + u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */ + u16 doff; /* 0x16 Signed Destination Address Offset */ + u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */ + u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */ + u16 csr; /* 0x1E Control and Status */ +} tcd_st; + +typedef struct tcd_multiple { + tcd_st tcd[16]; +} tcd_t; + +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 - 0x19 */ + u16 icfg0; /* 0x1A Configuration Register */ + u8 simr0; /* 0x1C Set Interrupt Mask */ + u8 cimr0; /* 0x1D Clear Interrupt Mask */ + u8 clmask0; /* 0x1E Current Level Mask */ + u8 slmask; /* 0x1F Saved Level Mask */ + u32 res2[8]; /* 0x20 - 0x3F */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 */ + u16 icfg1; /* 0x1A Configuration Register */ + u8 simr1; /* 0x1C Set Interrupt Mask */ + u8 cimr1; /* 0x1D Clear Interrupt Mask */ + u16 res2; /* 0x1E - 0x1F */ + u32 res3[8]; /* 0x20 - 0x3F */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +typedef struct intgack_ctrl1 { + /* Global IACK Registers */ + u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */ + u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */ +} intgack_t; + +/*I2C module registers */ +typedef struct i2c_ctrl { + u8 adr; /* 0x00 address register */ + u8 res1[3]; /* 0x01 - 0x03 */ + u8 fdr; /* 0x04 frequency divider register */ + u8 res2[3]; /* 0x05 - 0x07 */ + u8 cr; /* 0x08 control register */ + u8 res3[3]; /* 0x09 - 0x0B */ + u8 sr; /* 0x0C status register */ + u8 res4[3]; /* 0x0D - 0x0F */ + u8 dr; /* 0x10 data register */ + u8 res5[3]; /* 0x11 - 0x13 */ +} i2c_t; + +/* QSPI module registers */ +typedef struct qspi_ctrl { + u16 qmr; /* Mode register */ + u16 res1; + u16 qdlyr; /* Delay register */ + u16 res2; + u16 qwr; /* Wrap register */ + u16 res3; + u16 qir; /* Interrupt register */ + u16 res4; + u16 qar; /* Address register */ + u16 res5; + u16 qdr; /* Data register */ + u16 res6; +} qspi_t; + +/* PWM module registers */ +typedef struct pwm_ctrl { + u8 en; /* 0x00 PWM Enable Register */ + u8 pol; /* 0x01 Polarity Register */ + u8 clk; /* 0x02 Clock Select Register */ + u8 prclk; /* 0x03 Prescale Clock Select Register */ + u8 cae; /* 0x04 Center Align Enable Register */ + u8 ctl; /* 0x05 Control Register */ + u8 res1[2]; /* 0x06 - 0x07 */ + u8 scla; /* 0x08 Scale A register */ + u8 sclb; /* 0x09 Scale B register */ + u8 res2[2]; /* 0x0A - 0x0B */ + u8 cnt0; /* 0x0C Channel 0 Counter register */ + u8 cnt1; /* 0x0D Channel 1 Counter register */ + u8 cnt2; /* 0x0E Channel 2 Counter register */ + u8 cnt3; /* 0x0F Channel 3 Counter register */ + u8 cnt4; /* 0x10 Channel 4 Counter register */ + u8 cnt5; /* 0x11 Channel 5 Counter register */ + u8 cnt6; /* 0x12 Channel 6 Counter register */ + u8 cnt7; /* 0x13 Channel 7 Counter register */ + u8 per0; /* 0x14 Channel 0 Period register */ + u8 per1; /* 0x15 Channel 1 Period register */ + u8 per2; /* 0x16 Channel 2 Period register */ + u8 per3; /* 0x17 Channel 3 Period register */ + u8 per4; /* 0x18 Channel 4 Period register */ + u8 per5; /* 0x19 Channel 5 Period register */ + u8 per6; /* 0x1A Channel 6 Period register */ + u8 per7; /* 0x1B Channel 7 Period register */ + u8 dty0; /* 0x1C Channel 0 Duty register */ + u8 dty1; /* 0x1D Channel 1 Duty register */ + u8 dty2; /* 0x1E Channel 2 Duty register */ + u8 dty3; /* 0x1F Channel 3 Duty register */ + u8 dty4; /* 0x20 Channel 4 Duty register */ + u8 dty5; /* 0x21 Channel 5 Duty register */ + u8 dty6; /* 0x22 Channel 6 Duty register */ + u8 dty7; /* 0x23 Channel 7 Duty register */ + u8 sdn; /* 0x24 Shutdown register */ + u8 res3[3]; /* 0x25 - 0x27 */ +} pwm_t; + +/* Edge Port module registers */ +typedef struct eport_ctrl { + u16 par; /* 0x00 Pin Assignment Register */ + u8 ddar; /* 0x02 Data Direction Register */ + u8 ier; /* 0x03 Interrupt Enable Register */ + u8 dr; /* 0x04 Data Register */ + u8 pdr; /* 0x05 Pin Data Register */ + u8 fr; /* 0x06 Flag_Register */ + u8 res1; +} eport_t; + +/* Watchdog registers */ +typedef struct wdog_ctrl { + u16 cr; /* 0x00 Control register */ + u16 mr; /* 0x02 Modulus register */ + u16 cntr; /* 0x04 Count register */ + u16 sr; /* 0x06 Service register */ +} wdog_t; + +/*Chip configuration module registers */ +typedef struct ccm_ctrl { + u8 rstctrl; /* 0x00 Reset Controller register */ + u8 rststat; /* 0x01 Reset Status register */ + u16 res1; /* 0x02 - 0x03 */ + u16 ccr; /* 0x04 Chip configuration register */ + u16 res2; /* 0x06 */ + u16 rcon; /* 0x08 Rreset configuration register */ + u16 cir; /* 0x0A Chip identification register */ + u32 res3; /* 0x0C */ + u16 misccr; /* 0x10 Miscellaneous control register */ + u16 cdr; /* 0x12 Clock divider register */ + u16 uhcsr; /* 0x14 USB Host controller status register */ + u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */ +} ccm_t; + +/* GPIO port registers */ +typedef struct gpio_ctrl { + /* Port Output Data Registers */ + u8 podr_fech; /* 0x00 */ + u8 podr_fecl; /* 0x01 */ + u8 podr_ssi; /* 0x02 */ + u8 podr_busctl; /* 0x03 */ + u8 podr_be; /* 0x04 */ + u8 podr_cs; /* 0x05 */ + u8 podr_pwm; /* 0x06 */ + u8 podr_feci2c; /* 0x07 */ + u8 res1; /* 0x08 */ + u8 podr_uart; /* 0x09 */ + u8 podr_qspi; /* 0x0A */ + u8 podr_timer; /* 0x0B */ + u8 res2; /* 0x0C */ + u8 podr_lcddatah; /* 0x0D */ + u8 podr_lcddatam; /* 0x0E */ + u8 podr_lcddatal; /* 0x0F */ + u8 podr_lcdctlh; /* 0x10 */ + u8 podr_lcdctll; /* 0x11 */ + + /* Port Data Direction Registers */ + u16 res3; /* 0x12 - 0x13 */ + u8 pddr_fech; /* 0x14 */ + u8 pddr_fecl; /* 0x15 */ + u8 pddr_ssi; /* 0x16 */ + u8 pddr_busctl; /* 0x17 */ + u8 pddr_be; /* 0x18 */ + u8 pddr_cs; /* 0x19 */ + u8 pddr_pwm; /* 0x1A */ + u8 pddr_feci2c; /* 0x1B */ + u8 res4; /* 0x1C */ + u8 pddr_uart; /* 0x1D */ + u8 pddr_qspi; /* 0x1E */ + u8 pddr_timer; /* 0x1F */ + u8 res5; /* 0x20 */ + u8 pddr_lcddatah; /* 0x21 */ + u8 pddr_lcddatam; /* 0x22 */ + u8 pddr_lcddatal; /* 0x23 */ + u8 pddr_lcdctlh; /* 0x24 */ + u8 pddr_lcdctll; /* 0x25 */ + u16 res6; /* 0x26 - 0x27 */ + + /* Port Data Direction Registers */ + u8 ppd_fech; /* 0x28 */ + u8 ppd_fecl; /* 0x29 */ + u8 ppd_ssi; /* 0x2A */ + u8 ppd_busctl; /* 0x2B */ + u8 ppd_be; /* 0x2C */ + u8 ppd_cs; /* 0x2D */ + u8 ppd_pwm; /* 0x2E */ + u8 ppd_feci2c; /* 0x2F */ + u8 res7; /* 0x30 */ + u8 ppd_uart; /* 0x31 */ + u8 ppd_qspi; /* 0x32 */ + u8 ppd_timer; /* 0x33 */ + u8 res8; /* 0x34 */ + u8 ppd_lcddatah; /* 0x35 */ + u8 ppd_lcddatam; /* 0x36 */ + u8 ppd_lcddatal; /* 0x37 */ + u8 ppd_lcdctlh; /* 0x38 */ + u8 ppd_lcdctll; /* 0x39 */ + u16 res9; /* 0x3A - 0x3B */ + + /* Port Clear Output Data Registers */ + u8 pclrr_fech; /* 0x3C */ + u8 pclrr_fecl; /* 0x3D */ + u8 pclrr_ssi; /* 0x3E */ + u8 pclrr_busctl; /* 0x3F */ + u8 pclrr_be; /* 0x40 */ + u8 pclrr_cs; /* 0x41 */ + u8 pclrr_pwm; /* 0x42 */ + u8 pclrr_feci2c; /* 0x43 */ + u8 res10; /* 0x44 */ + u8 pclrr_uart; /* 0x45 */ + u8 pclrr_qspi; /* 0x46 */ + u8 pclrr_timer; /* 0x47 */ + u8 res11; /* 0x48 */ + u8 pclrr_lcddatah; /* 0x49 */ + u8 pclrr_lcddatam; /* 0x4A */ + u8 pclrr_lcddatal; /* 0x4B */ + u8 pclrr_lcdctlh; /* 0x4C */ + u8 pclrr_lcdctll; /* 0x4D */ + u16 res12; /* 0x4E - 0x4F */ + + /* Pin Assignment Registers */ + u8 par_fec; /* 0x50 */ + u8 par_pwm; /* 0x51 */ + u8 par_busctl; /* 0x52 */ + u8 par_feci2c; /* 0x53 */ + u8 par_be; /* 0x54 */ + u8 par_cs; /* 0x55 */ + u16 par_ssi; /* 0x56 */ + u16 par_uart; /* 0x58 */ + u16 par_qspi; /* 0x5A */ + u8 par_timer; /* 0x5C */ + u8 par_lcddata; /* 0x5D */ + u16 par_lcdctl; /* 0x5E */ + u16 par_irq; /* 0x60 */ + u16 res16; /* 0x62 - 0x63 */ + + /* Mode Select Control Registers */ + u8 mscr_flexbus; /* 0x64 */ + u8 mscr_sdram; /* 0x65 */ + u16 res17; /* 0x66 - 0x67 */ + + /* Drive Strength Control Registers */ + u8 dscr_i2c; /* 0x68 */ + u8 dscr_pwm; /* 0x69 */ + u8 dscr_fec; /* 0x6A */ + u8 dscr_uart; /* 0x6B */ + u8 dscr_qspi; /* 0x6C */ + u8 dscr_timer; /* 0x6D */ + u8 dscr_ssi; /* 0x6E */ + u8 dscr_lcd; /* 0x6F */ + u8 dscr_debug; /* 0x70 */ + u8 dscr_clkrst; /* 0x71 */ + u8 dscr_irq; /* 0x72 */ +} gpio_t; + +/* LCD module registers */ +typedef struct lcd_ctrl { + u32 ssar; /* 0x00 Screen Start Address Register */ + u32 sr; /* 0x04 LCD Size Register */ + u32 vpw; /* 0x08 Virtual Page Width Register */ + u32 cpr; /* 0x0C Cursor Position Register */ + u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */ + u32 ccmr; /* 0x14 Color Cursor Mapping Register */ + u32 pcr; /* 0x18 Panel Configuration Register */ + u32 hcr; /* 0x1C Horizontal Configuration Register */ + u32 vcr; /* 0x20 Vertical Configuration Register */ + u32 por; /* 0x24 Panning Offset Register */ + u32 scr; /* 0x28 Sharp Configuration Register */ + u32 pccr; /* 0x2C PWM Contrast Control Register */ + u32 dcr; /* 0x30 DMA Control Register */ + u32 rmcr; /* 0x34 Refresh Mode Control Register */ + u32 icr; /* 0x38 Refresh Mode Control Register */ + u32 ier; /* 0x3C Interrupt Enable Register */ + u32 isr; /* 0x40 Interrupt Status Register */ + u32 res[4]; + u32 gwsar; /* 0x50 Graphic Window Start Address Register */ + u32 gwsr; /* 0x54 Graphic Window Size Register */ + u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */ + u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */ + u32 gwpr; /* 0x60 Graphic Window Position Register */ + u32 gwcr; /* 0x64 Graphic Window Control Register */ + u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */ +} lcd_t; + +typedef struct lcdbg_ctrl { + u32 bglut[255]; +} lcdbg_t; + +typedef struct lcdgw_ctrl { + u32 gwlut[255]; +} lcdgw_t; + +/* USB OTG module registers */ +typedef struct usb_otg { + u32 id; /* 0x000 Identification Register */ + u32 hwgeneral; /* 0x004 General HW Parameters */ + u32 hwhost; /* 0x008 Host HW Parameters */ + u32 hwdev; /* 0x00C Device HW parameters */ + u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ + u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ + u32 res1[58]; /* 0x18 - 0xFF */ + u8 caplength; /* 0x100 Capability Register Length */ + u8 res2; /* 0x101 */ + u16 hciver; /* 0x102 Host Interface Version Number */ + u32 hcsparams; /* 0x104 Host Structural Parameters */ + u32 hccparams; /* 0x108 Host Capability Parameters */ + u32 res3[5]; /* 0x10C - 0x11F */ + u16 dciver; /* 0x120 Device Interface Version Number */ + u16 res4; /* 0x122 */ + u32 dccparams; /* 0x124 Device Capability Parameters */ + u32 res5[6]; /* 0x128 - 0x13F */ + u32 cmd; /* 0x140 USB Command */ + u32 sts; /* 0x144 USB Status */ + u32 intr; /* 0x148 USB Interrupt Enable */ + u32 frindex; /* 0x14C USB Frame Index */ + u32 res6; /* 0x150 */ + u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */ + u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */ + u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */ + u32 burstsize; /* 0x160 Master Interface Data Burst Size */ + u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */ + u32 res7[6]; /* 0x168 - 0x17F */ + u32 cfgflag; /* 0x180 Configure Flag Register */ + u32 portsc1; /* 0x184 Port Status/Control */ + u32 res8[7]; /* 0x188 - 0x1A3 */ + u32 otgsc; /* 0x1A4 On The Go Status and Control */ + u32 mode; /* 0x1A8 USB mode register */ + u32 eptsetstat; /* 0x1AC Endpoint Setup status */ + u32 eptprime; /* 0x1B0 Endpoint initialization */ + u32 eptflush; /* 0x1B4 Endpoint de-initialize */ + u32 eptstat; /* 0x1B8 Endpoint status */ + u32 eptcomplete; /* 0x1BC Endpoint Complete */ + u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ + u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ + u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ + u32 eptctrl3; /* 0x1CC Endpoint control 3 */ +} usbotg_t; + +/* USB Host module registers */ +typedef struct usb_host { + u32 id; /* 0x000 Identification Register */ + u32 hwgeneral; /* 0x004 General HW Parameters */ + u32 hwhost; /* 0x008 Host HW Parameters */ + u32 res1; /* 0x0C */ + u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ + u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ + u32 res2[58]; /* 0x18 - 0xFF */ + + /* Host Controller Capability Register */ + u8 caplength; /* 0x100 Capability Register Length */ + u8 res3; /* 0x101 */ + u16 hciver; /* 0x102 Host Interface Version Number */ + u32 hcsparams; /* 0x104 Host Structural Parameters */ + u32 hccparams; /* 0x108 Host Capability Parameters */ + u32 res4[13]; /* 0x10C - 0x13F */ + + /* Host Controller Operational Register */ + u32 cmd; /* 0x140 USB Command */ + u32 sts; /* 0x144 USB Status */ + u32 intr; /* 0x148 USB Interrupt Enable */ + u32 frindex; /* 0x14C USB Frame Index */ + u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */ + u32 prdlst; /* 0x154 Periodic Frame List Base Address */ + u32 aynclst; /* 0x158 Current Asynchronous List Address */ + u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */ + u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */ + u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */ + u32 res6[6]; /* 0x168 - 0x17F */ + u32 cfgflag; /* 0x180 Configure Flag Register */ + u32 portsc1; /* 0x184 Port Status/Control */ + u32 res7[8]; /* 0x188 - 0x1A7 */ + + /* non-ehci registers */ + u32 mode; /* 0x1A8 USB mode register */ + u32 eptsetstat; /* 0x1AC Endpoint Setup status */ + u32 eptprime; /* 0x1B0 Endpoint initialization */ + u32 eptflush; /* 0x1B4 Endpoint de-initialize */ + u32 eptstat; /* 0x1B8 Endpoint status */ + u32 eptcomplete; /* 0x1BC Endpoint Complete */ + u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ + u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ + u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ + u32 eptctrl3; /* 0x1CC Endpoint control 3 */ +} usbhost_t; + +/* SDRAM controller registers */ +typedef struct sdram_ctrl { + u32 mode; /* 0x00 Mode/Extended Mode register */ + u32 ctrl; /* 0x04 Control register */ + u32 cfg1; /* 0x08 Configuration register 1 */ + u32 cfg2; /* 0x0C Configuration register 2 */ + u32 res1[64]; /* 0x10 - 0x10F */ + u32 cs0; /* 0x110 Chip Select 0 Configuration */ + u32 cs1; /* 0x114 Chip Select 1 Configuration */ +} sdram_t; + +/* Synchronous serial interface */ +typedef struct ssi_ctrl { + u32 tx0; /* 0x00 Transmit Data Register 0 */ + u32 tx1; /* 0x04 Transmit Data Register 1 */ + u32 rx0; /* 0x08 Receive Data Register 0 */ + u32 rx1; /* 0x0C Receive Data Register 1 */ + u32 cr; /* 0x10 Control Register */ + u32 isr; /* 0x14 Interrupt Status Register */ + u32 ier; /* 0x18 Interrupt Enable Register */ + u32 tcr; /* 0x1C Transmit Configuration Register */ + u32 rcr; /* 0x20 Receive Configuration Register */ + u32 ccr; /* 0x24 Clock Control Register */ + u32 res1; /* 0x28 */ + u32 fcsr; /* 0x2C FIFO Control/Status Register */ + u32 res2[2]; /* 0x30 - 0x37 */ + u32 acr; /* 0x38 AC97 Control Register */ + u32 acadd; /* 0x3C AC97 Command Address Register */ + u32 acdat; /* 0x40 AC97 Command Data Register */ + u32 atag; /* 0x44 AC97 Tag Register */ + u32 tmask; /* 0x48 Transmit Time Slot Mask Register */ + u32 rmask; /* 0x4C Receive Time Slot Mask Register */ +} ssi_t; + +/* Clock Module registers */ +typedef struct pll_ctrl { + u8 podr; /* 0x00 Output Divider Register */ + u8 res1[3]; + u8 pcr; /* 0x04 Control Register */ + u8 res2[3]; + u8 pmdr; /* 0x08 Modulation Divider Register */ + u8 res3[3]; + u8 pfdr; /* 0x0C Feedback Divider Register */ + u8 res4[3]; +} pll_t; + +#endif /* __IMMAP_5329__ */ diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h new file mode 100644 index 0000000..d091d7b --- /dev/null +++ b/include/asm-m68k/immap_5445x.h @@ -0,0 +1,937 @@ +/* + * MCF5445x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5445X__ +#define __IMMAP_5445X__ + +/* Module Base Addresses */ +#define MMAP_SCM1 0xFC000000 +#define MMAP_XBS 0xFC004000 +#define MMAP_FBCS 0xFC008000 +#define MMAP_FEC0 0xFC030000 +#define MMAP_FEC1 0xFC034000 +#define MMAP_RTC 0xFC03C000 +#define MMAP_EDMA 0xFC044000 +#define MMAP_INTC0 0xFC048000 +#define MMAP_INTC1 0xFC04C000 +#define MMAP_IACK 0xFC054000 +#define MMAP_I2C 0xFC058000 +#define MMAP_DSPI 0xFC05C000 +#define MMAP_UART0 0xFC060000 +#define MMAP_UART1 0xFC064000 +#define MMAP_UART2 0xFC068000 +#define MMAP_DTMR0 0xFC070000 +#define MMAP_DTMR1 0xFC074000 +#define MMAP_DTMR2 0xFC078000 +#define MMAP_DTMR3 0xFC07C000 +#define MMAP_PIT0 0xFC080000 +#define MMAP_PIT1 0xFC084000 +#define MMAP_PIT2 0xFC088000 +#define MMAP_PIT3 0xFC08C000 +#define MMAP_EPORT 0xFC094000 +#define MMAP_WTM 0xFC098000 +#define MMAP_SBF 0xFC0A0000 +#define MMAP_RCM 0xFC0A0000 +#define MMAP_CCM 0xFC0A0000 +#define MMAP_GPIO 0xFC0A4000 +#define MMAP_PCI 0xFC0A8000 +#define MMAP_PCIARB 0xFC0AC000 +#define MMAP_RNG 0xFC0B4000 +#define MMAP_SDRAM 0xFC0B8000 +#define MMAP_SSI 0xFC0BC000 +#define MMAP_PLL 0xFC0C4000 +#define MMAP_ATA 0x90000000 + +/********************************************************************* +* ATA +*********************************************************************/ + +typedef struct atac { + /* PIO */ + u8 toff; /* 0x00 */ + u8 ton; /* 0x01 */ + u8 t1; /* 0x02 */ + u8 t2w; /* 0x03 */ + u8 t2r; /* 0x04 */ + u8 ta; /* 0x05 */ + u8 trd; /* 0x06 */ + u8 t4; /* 0x07 */ + u8 t9; /* 0x08 */ + + /* DMA */ + u8 tm; /* 0x09 */ + u8 tn; /* 0x0A */ + u8 td; /* 0x0B */ + u8 tk; /* 0x0C */ + u8 tack; /* 0x0D */ + u8 tenv; /* 0x0E */ + u8 trp; /* 0x0F */ + u8 tzah; /* 0x10 */ + u8 tmli; /* 0x11 */ + u8 tdvh; /* 0x12 */ + u8 tdzfs; /* 0x13 */ + u8 tdvs; /* 0x14 */ + u8 tcvh; /* 0x15 */ + u8 tss; /* 0x16 */ + u8 tcyc; /* 0x17 */ + + /* FIFO */ + u32 fifo32; /* 0x18 */ + u16 fifo16; /* 0x1C */ + u8 rsvd0[2]; + u8 ffill; /* 0x20 */ + u8 rsvd1[3]; + + /* ATA */ + u8 cr; /* 0x24 */ + u8 rsvd2[3]; + u8 isr; /* 0x28 */ + u8 rsvd3[3]; + u8 ier; /* 0x2C */ + u8 rsvd4[3]; + u8 icr; /* 0x30 */ + u8 rsvd5[3]; + u8 falarm; /* 0x34 */ + u8 rsvd6[106]; +} atac_t; + +/********************************************************************* +* Cross-bar switch (XBS) +*********************************************************************/ + +typedef struct xbs { + u8 resv0[0x100]; + u32 prs1; /* XBS Priority Register */ + u8 resv1[0xC]; + u32 crs1; /* XBS Control Register */ + u8 resv2[0xEC]; + u32 prs2; /* XBS Priority Register */ + u8 resv3[0xC]; + u32 crs2; /* XBS Control Register */ + u8 resv4[0xEC]; + u32 prs3; /* XBS Priority Register */ + u8 resv5[0xC]; + u32 crs3; /* XBS Control Register */ + u8 resv6[0xEC]; + u32 prs4; /* XBS Priority Register */ + u8 resv7[0xC]; + u32 crs4; /* XBS Control Register */ + u8 resv8[0xEC]; + u32 prs5; /* XBS Priority Register */ + u8 resv9[0xC]; + u32 crs5; /* XBS Control Register */ + u8 resv10[0xEC]; + u32 prs6; /* XBS Priority Register */ + u8 resv11[0xC]; + u32 crs6; /* XBS Control Register */ + u8 resv12[0xEC]; + u32 prs7; /* XBS Priority Register */ + u8 resv13[0xC]; + u32 crs7; /* XBS Control Register */ +} xbs_t; + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ + +typedef struct fbcs { + u32 csar0; /* Chip-select Address Register */ + u32 csmr0; /* Chip-select Mask Register */ + u32 cscr0; /* Chip-select Control Register */ + u32 csar1; /* Chip-select Address Register */ + u32 csmr1; /* Chip-select Mask Register */ + u32 cscr1; /* Chip-select Control Register */ + u32 csar2; /* Chip-select Address Register */ + u32 csmr2; /* Chip-select Mask Register */ + u32 cscr2; /* Chip-select Control Register */ + u32 csar3; /* Chip-select Address Register */ + u32 csmr3; /* Chip-select Mask Register */ + u32 cscr3; /* Chip-select Control Register */ +} fbcs_t; + +/********************************************************************* +* Enhanced DMA (EDMA) +*********************************************************************/ + +typedef struct edma { + u32 cr; + u32 es; + u8 resv0[0x6]; + u16 erq; + u8 resv1[0x6]; + u16 eei; + u8 serq; + u8 cerq; + u8 seei; + u8 ceei; + u8 cint; + u8 cerr; + u8 ssrt; + u8 cdne; + u8 resv2[0x6]; + u16 intr; + u8 resv3[0x6]; + u16 err; + u8 resv4[0xD0]; + u8 dchpri0; + u8 dchpri1; + u8 dchpri2; + u8 dchpri3; + u8 dchpri4; + u8 dchpri5; + u8 dchpri6; + u8 dchpri7; + u8 dchpri8; + u8 dchpri9; + u8 dchpri10; + u8 dchpri11; + u8 dchpri12; + u8 dchpri13; + u8 dchpri14; + u8 dchpri15; + u8 resv5[0xEF0]; + u32 tcd0_saddr; + u16 tcd0_attr; + u16 tcd0_soff; + u32 tcd0_nbytes; + u32 tcd0_slast; + u32 tcd0_daddr; + union { + u16 tcd0_citer_elink; + u16 tcd0_citer; + }; + u16 tcd0_doff; + u32 tcd0_dlast_sga; + union { + u16 tcd0_biter_elink; + u16 tcd0_biter; + }; + u16 tcd0_csr; + u32 tcd1_saddr; + u16 tcd1_attr; + u16 tcd1_soff; + u32 tcd1_nbytes; + u32 tcd1_slast; + u32 tcd1_daddr; + union { + u16 tcd1_citer_elink; + u16 tcd1_citer; + }; + u16 tcd1_doff; + u32 tcd1_dlast_sga; + union { + u16 tcd1_biter; + u16 tcd1_biter_elink; + }; + u16 tcd1_csr; + u32 tcd2_saddr; + u16 tcd2_attr; + u16 tcd2_soff; + u32 tcd2_nbytes; + u32 tcd2_slast; + u32 tcd2_daddr; + union { + u16 tcd2_citer; + u16 tcd2_citer_elink; + }; + u16 tcd2_doff; + u32 tcd2_dlast_sga; + union { + u16 tcd2_biter_elink; + u16 tcd2_biter; + }; + u16 tcd2_csr; + u32 tcd3_saddr; + u16 tcd3_attr; + u16 tcd3_soff; + u32 tcd3_nbytes; + u32 tcd3_slast; + u32 tcd3_daddr; + union { + u16 tcd3_citer; + u16 tcd3_citer_elink; + }; + u16 tcd3_doff; + u32 tcd3_dlast_sga; + union { + u16 tcd3_biter_elink; + u16 tcd3_biter; + }; + u16 tcd3_csr; + u32 tcd4_saddr; + u16 tcd4_attr; + u16 tcd4_soff; + u32 tcd4_nbytes; + u32 tcd4_slast; + u32 tcd4_daddr; + union { + u16 tcd4_citer; + u16 tcd4_citer_elink; + }; + u16 tcd4_doff; + u32 tcd4_dlast_sga; + union { + u16 tcd4_biter; + u16 tcd4_biter_elink; + }; + u16 tcd4_csr; + u32 tcd5_saddr; + u16 tcd5_attr; + u16 tcd5_soff; + u32 tcd5_nbytes; + u32 tcd5_slast; + u32 tcd5_daddr; + union { + u16 tcd5_citer; + u16 tcd5_citer_elink; + }; + u16 tcd5_doff; + u32 tcd5_dlast_sga; + union { + u16 tcd5_biter_elink; + u16 tcd5_biter; + }; + u16 tcd5_csr; + u32 tcd6_saddr; + u16 tcd6_attr; + u16 tcd6_soff; + u32 tcd6_nbytes; + u32 tcd6_slast; + u32 tcd6_daddr; + union { + u16 tcd6_citer; + u16 tcd6_citer_elink; + }; + u16 tcd6_doff; + u32 tcd6_dlast_sga; + union { + u16 tcd6_biter_elink; + u16 tcd6_biter; + }; + u16 tcd6_csr; + u32 tcd7_saddr; + u16 tcd7_attr; + u16 tcd7_soff; + u32 tcd7_nbytes; + u32 tcd7_slast; + u32 tcd7_daddr; + union { + u16 tcd7_citer; + u16 tcd7_citer_elink; + }; + u16 tcd7_doff; + u32 tcd7_dlast_sga; + union { + u16 tcd7_biter_elink; + u16 tcd7_biter; + }; + u16 tcd7_csr; + u32 tcd8_saddr; + u16 tcd8_attr; + u16 tcd8_soff; + u32 tcd8_nbytes; + u32 tcd8_slast; + u32 tcd8_daddr; + union { + u16 tcd8_citer; + u16 tcd8_citer_elink; + }; + u16 tcd8_doff; + u32 tcd8_dlast_sga; + union { + u16 tcd8_biter_elink; + u16 tcd8_biter; + }; + u16 tcd8_csr; + u32 tcd9_saddr; + u16 tcd9_attr; + u16 tcd9_soff; + u32 tcd9_nbytes; + u32 tcd9_slast; + u32 tcd9_daddr; + union { + u16 tcd9_citer_elink; + u16 tcd9_citer; + }; + u16 tcd9_doff; + u32 tcd9_dlast_sga; + union { + u16 tcd9_biter_elink; + u16 tcd9_biter; + }; + u16 tcd9_csr; + u32 tcd10_saddr; + u16 tcd10_attr; + u16 tcd10_soff; + u32 tcd10_nbytes; + u32 tcd10_slast; + u32 tcd10_daddr; + union { + u16 tcd10_citer_elink; + u16 tcd10_citer; + }; + u16 tcd10_doff; + u32 tcd10_dlast_sga; + union { + u16 tcd10_biter; + u16 tcd10_biter_elink; + }; + u16 tcd10_csr; + u32 tcd11_saddr; + u16 tcd11_attr; + u16 tcd11_soff; + u32 tcd11_nbytes; + u32 tcd11_slast; + u32 tcd11_daddr; + union { + u16 tcd11_citer; + u16 tcd11_citer_elink; + }; + u16 tcd11_doff; + u32 tcd11_dlast_sga; + union { + u16 tcd11_biter; + u16 tcd11_biter_elink; + }; + u16 tcd11_csr; + u32 tcd12_saddr; + u16 tcd12_attr; + u16 tcd12_soff; + u32 tcd12_nbytes; + u32 tcd12_slast; + u32 tcd12_daddr; + union { + u16 tcd12_citer; + u16 tcd12_citer_elink; + }; + u16 tcd12_doff; + u32 tcd12_dlast_sga; + union { + u16 tcd12_biter; + u16 tcd12_biter_elink; + }; + u16 tcd12_csr; + u32 tcd13_saddr; + u16 tcd13_attr; + u16 tcd13_soff; + u32 tcd13_nbytes; + u32 tcd13_slast; + u32 tcd13_daddr; + union { + u16 tcd13_citer_elink; + u16 tcd13_citer; + }; + u16 tcd13_doff; + u32 tcd13_dlast_sga; + union { + u16 tcd13_biter_elink; + u16 tcd13_biter; + }; + u16 tcd13_csr; + u32 tcd14_saddr; + u16 tcd14_attr; + u16 tcd14_soff; + u32 tcd14_nbytes; + u32 tcd14_slast; + u32 tcd14_daddr; + union { + u16 tcd14_citer; + u16 tcd14_citer_elink; + }; + u16 tcd14_doff; + u32 tcd14_dlast_sga; + union { + u16 tcd14_biter_elink; + u16 tcd14_biter; + }; + u16 tcd14_csr; + u32 tcd15_saddr; + u16 tcd15_attr; + u16 tcd15_soff; + u32 tcd15_nbytes; + u32 tcd15_slast; + u32 tcd15_daddr; + union { + u16 tcd15_citer_elink; + u16 tcd15_citer; + }; + u16 tcd15_doff; + u32 tcd15_dlast_sga; + union { + u16 tcd15_biter; + u16 tcd15_biter_elink; + }; + u16 tcd15_csr; +} edma_t; + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ + +typedef struct int0_ctrl { + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 - 0x19 */ + u16 icfg0; /* 0x1A Configuration Register */ + u8 simr0; /* 0x1C Set Interrupt Mask */ + u8 cimr0; /* 0x1D Clear Interrupt Mask */ + u8 clmask0; /* 0x1E Current Level Mask */ + u8 slmask; /* 0x1F Saved Level Mask */ + u32 res2[8]; /* 0x20 - 0x3F */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 */ + u16 icfg1; /* 0x1A Configuration Register */ + u8 simr1; /* 0x1C Set Interrupt Mask */ + u8 cimr1; /* 0x1D Clear Interrupt Mask */ + u16 res2; /* 0x1E - 0x1F */ + u32 res3[8]; /* 0x20 - 0x3F */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +/********************************************************************* +* Global Interrupt Acknowledge (IACK) +*********************************************************************/ + +typedef struct iack { + u8 resv0[0xE0]; + u8 gswiack; + u8 resv1[0x3]; + u8 gl1iack; + u8 resv2[0x3]; + u8 gl2iack; + u8 resv3[0x3]; + u8 gl3iack; + u8 resv4[0x3]; + u8 gl4iack; + u8 resv5[0x3]; + u8 gl5iack; + u8 resv6[0x3]; + u8 gl6iack; + u8 resv7[0x3]; + u8 gl7iack; +} iack_t; + +/********************************************************************* +* DMA Serial Peripheral Interface (DSPI) +*********************************************************************/ + +typedef struct dspi { + u32 dmcr; + u8 resv0[0x4]; + u32 dtcr; + u32 dctar0; + u32 dctar1; + u32 dctar2; + u32 dctar3; + u32 dctar4; + u32 dctar5; + u32 dctar6; + u32 dctar7; + u32 dsr; + u32 dirsr; + u32 dtfr; + u32 drfr; + u32 dtfdr0; + u32 dtfdr1; + u32 dtfdr2; + u32 dtfdr3; + u8 resv1[0x30]; + u32 drfdr0; + u32 drfdr1; + u32 drfdr2; + u32 drfdr3; +} dspi_t; + +/********************************************************************* +* Edge Port Module (EPORT) +*********************************************************************/ + +typedef struct eport { + u16 eppar; + u8 epddr; + u8 epier; + u8 epdr; + u8 eppdr; + u8 epfr; +} eport_t; + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ + +typedef struct wtm { + u16 wcr; + u16 wmr; + u16 wcntr; + u16 wsr; +} wtm_t; + +/********************************************************************* +* Serial Boot Facility (SBF) +*********************************************************************/ + +typedef struct sbf { + u8 resv0[0x18]; + u16 sbfsr; /* Serial Boot Facility Status Register */ + u8 resv1[0x6]; + u16 sbfcr; /* Serial Boot Facility Control Register */ +} sbf_t; + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +typedef struct ccm { + u8 ccm_resv0[0x4]; + u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */ + u8 resv1[0x2]; + u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */ + u16 cir; /* Chip Identification Register (Read-only) */ + u8 resv2[0x4]; + u16 misccr; /* Miscellaneous Control Register */ + u16 cdr; /* Clock Divider Register */ + u16 uocsr; /* USB On-the-Go Controller Status Register */ +} ccm_t; + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ + +typedef struct gpio { + u8 podr_fec0h; /* FEC0 High Port Output Data Register */ + u8 podr_fec0l; /* FEC0 Low Port Output Data Register */ + u8 podr_ssi; /* SSI Port Output Data Register */ + u8 podr_fbctl; /* Flexbus Control Port Output Data Register */ + u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */ + u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */ + u8 podr_dma; /* DMA Port Output Data Register */ + u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */ + u8 resv0[0x1]; + u8 podr_uart; /* UART Port Output Data Register */ + u8 podr_dspi; /* DSPI Port Output Data Register */ + u8 podr_timer; /* Timer Port Output Data Register */ + u8 podr_pci; /* PCI Port Output Data Register */ + u8 podr_usb; /* USB Port Output Data Register */ + u8 podr_atah; /* ATA High Port Output Data Register */ + u8 podr_atal; /* ATA Low Port Output Data Register */ + u8 podr_fec1h; /* FEC1 High Port Output Data Register */ + u8 podr_fec1l; /* FEC1 Low Port Output Data Register */ + u8 resv1[0x2]; + u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */ + u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */ + u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */ + u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */ + u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */ + u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */ + u8 pddr_ssi; /* SSI Port Data Direction Register */ + u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */ + u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */ + u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */ + u8 pddr_dma; /* DMA Port Data Direction Register */ + u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */ + u8 resv2[0x1]; + u8 pddr_uart; /* UART Port Data Direction Register */ + u8 pddr_dspi; /* DSPI Port Data Direction Register */ + u8 pddr_timer; /* Timer Port Data Direction Register */ + u8 pddr_pci; /* PCI Port Data Direction Register */ + u8 pddr_usb; /* USB Port Data Direction Register */ + u8 pddr_atah; /* ATA High Port Data Direction Register */ + u8 pddr_atal; /* ATA Low Port Data Direction Register */ + u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */ + u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */ + u8 resv3[0x2]; + u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */ + u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */ + u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */ + u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */ + u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */ + u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */ + u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */ + u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */ + u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */ + u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */ + u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */ + u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */ + u8 resv4[0x1]; + u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */ + u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */ + u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */ + u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */ + u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */ + u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */ + u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */ + u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */ + u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */ + u8 resv5[0x2]; + u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */ + u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */ + u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */ + u8 pclrr_ssi; /* SSI Port Clear Output Data Register */ + u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */ + u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */ + u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */ + u8 pclrr_dma; /* DMA Port Clear Output Data Register */ + u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */ + u8 resv6[0x1]; + u8 pclrr_uart; /* UART Port Clear Output Data Register */ + u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */ + u8 pclrr_timer; /* Timer Port Clear Output Data Register */ + u8 pclrr_pci; /* PCI Port Clear Output Data Register */ + u8 pclrr_usb; /* USB Port Clear Output Data Register */ + u8 pclrr_atah; /* ATA High Port Clear Output Data Register */ + u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */ + u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */ + u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */ + u8 resv7[0x2]; + u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */ + u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */ + u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */ + u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */ + u8 par_fec; /* FEC Pin Assignment Register */ + u8 par_dma; /* DMA Pin Assignment Register */ + u8 par_fbctl; /* Flexbus Control Pin Assignment Register */ + u8 par_dspi; /* DSPI Pin Assignment Register */ + u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */ + u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */ + u8 par_timer; /* Time Pin Assignment Register */ + u8 par_usb; /* USB Pin Assignment Register */ + u8 resv8[0x1]; + u8 par_uart; /* UART Pin Assignment Register */ + u16 par_feci2c; /* FEC / I2C Pin Assignment Register */ + u16 par_ssi; /* SSI Pin Assignment Register */ + u16 par_ata; /* ATA Pin Assignment Register */ + u8 par_irq; /* IRQ Pin Assignment Register */ + u8 resv9[0x1]; + u16 par_pci; /* PCI Pin Assignment Register */ + u8 mscr_sdram; /* SDRAM Mode Select Control Register */ + u8 mscr_pci; /* PCI Mode Select Control Register */ + u8 resv10[0x2]; + u8 dscr_i2c; /* I2C Drive Strength Control Register */ + u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */ + u8 dscr_fec; /* FEC Drive Strength Control Register */ + u8 dscr_uart; /* UART Drive Strength Control Register */ + u8 dscr_dspi; /* DSPI Drive Strength Control Register */ + u8 dscr_timer; /* TIMER Drive Strength Control Register */ + u8 dscr_ssi; /* SSI Drive Strength Control Register */ + u8 dscr_dma; /* DMA Drive Strength Control Register */ + u8 dscr_debug; /* DEBUG Drive Strength Control Register */ + u8 dscr_reset; /* RESET Drive Strength Control Register */ + u8 dscr_irq; /* IRQ Drive Strength Control Register */ + u8 dscr_usb; /* USB Drive Strength Control Register */ + u8 dscr_ata; /* ATA Drive Strength Control Register */ +} gpio_t; + +/********************************************************************* +* Random Number Generator (RNG) +*********************************************************************/ + +typedef struct rng { + u32 rngcr; + u32 rngsr; + u32 rnger; + u32 rngout; +} rng_t; + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +typedef struct sdramc { + u32 sdmr; /* SDRAM Mode/Extended Mode Register */ + u32 sdcr; /* SDRAM Control Register */ + u32 sdcfg1; /* SDRAM Configuration Register 1 */ + u32 sdcfg2; /* SDRAM Chip Select Register */ + u8 resv0[0x100]; + u32 sdcs0; /* SDRAM Mode/Extended Mode Register */ + u32 sdcs1; /* SDRAM Mode/Extended Mode Register */ +} sdramc_t; + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ + +typedef struct ssi { + u32 tx0; + u32 tx1; + u32 rx0; + u32 rx1; + u32 cr; + u32 isr; + u32 ier; + u32 tcr; + u32 rcr; + u32 ccr; + u8 resv0[0x4]; + u32 fcsr; + u8 resv1[0x8]; + u32 acr; + u32 acadd; + u32 acdat; + u32 atag; + u32 tmask; + u32 rmask; +} ssi_t; + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +typedef struct pll { + u32 pcr; /* PLL Control Register */ + u32 psr; /* PLL Status Register */ +} pll_t; + +typedef struct pci { + u32 idr; /* 0x00 Device Id / Vendor Id Register */ + u32 scr; /* 0x04 Status / command Register */ + u32 ccrir; /* 0x08 Class Code / Revision Id Register */ + u32 cr1; /* 0x0c Configuration 1 Register */ + u32 bar0; /* 0x10 Base address register 0 Register */ + u32 bar1; /* 0x14 Base address register 1 Register */ + u32 bar2; /* 0x18 Base address register 2 Register */ + u32 bar3; /* 0x1c Base address register 3 Register */ + u32 bar4; /* 0x20 Base address register 4 Register */ + u32 bar5; /* 0x24 Base address register 5 Register */ + u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */ + u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */ + u32 erbar; /* 0x30 Expansion ROM Base Address Register */ + u32 cpr; /* 0x34 Capabilities Pointer Register */ + u32 rsvd1; /* 0x38 */ + u32 cr2; /* 0x3c Configuration Register 2 */ + u32 rsvd2[8]; /* 0x40 - 0x5f */ + + /* General control / status registers */ + u32 gscr; /* 0x60 Global Status / Control Register */ + u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */ + u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */ + u32 tcr1; /* 0x6c Target Control 1 Register */ + u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */ + u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */ + u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */ + u32 rsvd3; /* 0x7c */ + u32 iwcr; /* 0x80 Initiator Window Configuration Register */ + u32 icr; /* 0x84 Initiator Control Register */ + u32 isr; /* 0x88 Initiator Status Register */ + u32 tcr2; /* 0x8c Target Control 2 Register */ + u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */ + u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */ + u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */ + u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */ + u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */ + u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */ + u32 intr; /* 0xa8 Interrupt Register */ + u32 rsvd4[19]; /* 0xac - 0xf7 */ + u32 car; /* 0xf8 Configuration Address Register */ +} pci_t; + +typedef struct pci_arbiter { + /* Pci Arbiter Registers */ + union { + u32 acr; /* Arbiter Control Register */ + u32 asr; /* Arbiter Status Register */ + }; +} pciarb_t; + +/* Register read/write struct */ +typedef struct scm1 { + u32 mpr; /* 0x00 Master Privilege Register */ + u32 rsvd1[7]; + u32 pacra; /* 0x20 Peripheral Access Control Register A */ + u32 pacrb; /* 0x24 Peripheral Access Control Register B */ + u32 pacrc; /* 0x28 Peripheral Access Control Register C */ + u32 pacrd; /* 0x2C Peripheral Access Control Register D */ + u32 rsvd2[4]; + u32 pacre; /* 0x40 Peripheral Access Control Register E */ + u32 pacrf; /* 0x44 Peripheral Access Control Register F */ + u32 pacrg; /* 0x48 Peripheral Access Control Register G */ +} scm1_t; +/********************************************************************/ + +typedef struct rtcex { + u32 rsvd1[3]; + u32 gocu; + u32 gocl; +} rtcex_t; +#endif /* __IMMAP_5445X__ */ diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 7bbdefb..e14a581 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -1,8 +1,221 @@ -#ifndef __ASM_M68K_IO_H_ -#define __ASM_M68K_IO_H_ +/* + * IO header file + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ -static inline void sync(void) +#ifndef __ASM_M68K_IO_H__ +#define __ASM_M68K_IO_H__ + +#include <asm/byteorder.h> + +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +#if !defined(__BIG_ENDIAN) +#define readw(addr) (*(volatile u16 *) (addr)) +#define readl(addr) (*(volatile u32 *) (addr)) +#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#else +#define readw(addr) in_le16((volatile u16 *)(addr)) +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#endif + +/* + * The insw/outsw/insl/outsl macros don't do byte-swapping. + * They are only used in practice for transferring buffers which + * are arrays of bytes, and byte-swapping is not appropriate in + * that case. - paulus + */ +#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#if !defined(__BIG_ENDIAN) +#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) +#else +#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#endif + +extern inline void _insb(volatile u8 * port, void *buf, int ns) +{ + u8 *data = (u8 *) buf; + while (ns--) + *data++ = *port; +} + +extern inline void _outsb(volatile u8 * port, const void *buf, int ns) +{ + u8 *data = (u8 *) buf; + while (ns--) + *port = *data++; +} + +extern inline void _insw(volatile u16 * port, void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) + *data++ = __sw16(*port); +} + +extern inline void _outsw(volatile u16 * port, const void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) { + *port = __sw16(*data); + data++; + } +} + +extern inline void _insl(volatile u32 * port, void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) + *data++ = __sw32(*port); +} + +extern inline void _outsl(volatile u32 * port, const void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) { + *port = __sw32(*data); + data++; + } +} + +extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) + *data++ = *port; +} + +extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) { + *port = *data++; + } +} + +extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) + *data++ = *port; +} + +extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) { + *port = *data; + data++; + } +} + +/* + * The *_ns versions below don't do byte-swapping. + * Neither do the standard versions now, these are just here + * for older code. + */ +#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define IO_SPACE_LIMIT ~0 + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +extern inline int in_8(volatile u8 * addr) +{ + return (int)*addr; +} + +extern inline void out_8(volatile u8 * addr, int val) +{ + *addr = (u8) val; +} + +extern inline int in_le16(volatile u16 * addr) +{ + return __sw16(*addr); +} + +extern inline int in_be16(volatile u16 * addr) +{ + return (*addr & 0xFFFF); +} + +extern inline void out_le16(volatile u16 * addr, int val) +{ + *addr = __sw16(val); +} + +extern inline void out_be16(volatile u16 * addr, int val) +{ + *addr = (u16) val; +} + +extern inline unsigned in_le32(volatile u32 * addr) { + return __sw32(*addr); } -#endif /* __ASM_M68K_IO_H_ */ +extern inline unsigned in_be32(volatile u32 * addr) +{ + return (*addr); +} + +extern inline void out_le32(volatile unsigned *addr, int val) +{ + *addr = __sw32(val); +} + +extern inline void out_be32(volatile unsigned *addr, int val) +{ + *addr = val; +} + +static inline void sync(void) +{ + /* This sync function is for PowerPC or other architecture instruction + * ColdFire does not have this instruction. Dummy function, added for + * compatibility (CFI driver) + */ +} +#endif /* __ASM_M68K_IO_H__ */ diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h new file mode 100644 index 0000000..b98b452 --- /dev/null +++ b/include/asm-m68k/m5235.h @@ -0,0 +1,905 @@ +/* + * mcf5329.h -- Definitions for Freescale Coldfire 5329 + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef mcf5235_h +#define mcf5235_h +/****************************************************************************/ + +/********************************************************************* +* System Control Module (SCM) +*********************************************************************/ + +/* Bit definition and macros for SCM_IPSBAR */ +#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) +#define SCM_IPSBAR_V (0x00000001) + +/* Bit definition and macros for SCM_RAMBAR */ +#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) +#define SCM_RAMBAR_BDE (0x00000200) + +/* Bit definition and macros for SCM_CRSR */ +#define SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for SCM_CWCR */ +#define SCM_CWCR_CWE (0x80) +#define SCM_CWCR_CWRI (0x40) +#define SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define SCM_CWCR_CWTA (0x04) +#define SCM_CWCR_CWTAVAL (0x02) +#define SCM_CWCR_CWTIC (0x01) + +/* Bit definitions and macros for SCM_LPICR */ +#define SCM_LPICR_ENBSTOP (0x80) +#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) +#define SCM_LPICR_XLPM_IPL_ANY (0x00) +#define SCM_LPICR_XLPM_IPL_L2_7 (0x10) +#define SCM_LPICR_XLPM_IPL_L3_7 (0x20) +#define SCM_LPICR_XLPM_IPL_L4_7 (0x30) +#define SCM_LPICR_XLPM_IPL_L5_7 (0x40) +#define SCM_LPICR_XLPM_IPL_L6_7 (0x50) +#define SCM_LPICR_XLPM_IPL_L7 (0x70) + +/* Bit definitions and macros for SCM_DMAREQC */ +#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) +#define SCM_DMAREQC_EXT_ETPU (0x00080000) +#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000) +#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000) +#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000) +#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) +#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) +#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) +#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) +#define SCM_DMAREQC_DMACn_DTMR0 (0x04) +#define SCM_DMAREQC_DMACn_DTMR1 (0x05) +#define SCM_DMAREQC_DMACn_DTMR2 (0x06) +#define SCM_DMAREQC_DMACn_DTMR3 (0x07) +#define SCM_DMAREQC_DMACn_UART0RX (0x08) +#define SCM_DMAREQC_DMACn_UART1RX (0x09) +#define SCM_DMAREQC_DMACn_UART2RX (0x0A) +#define SCM_DMAREQC_DMACn_UART0TX (0x0C) +#define SCM_DMAREQC_DMACn_UART1TX (0x0D) +#define SCM_DMAREQC_DMACn_UART3TX (0x0E) + +/* Bit definitions and macros for SCM_MPARK */ +#define SCM_MPARK_M2_P_EN (0x02000000) +#define SCM_MPARK_M3_PRTY_MSK (0x00C00000) +#define SCM_MPARK_M3_PRTY_4TH (0x00000000) +#define SCM_MPARK_M3_PRTY_3RD (0x00400000) +#define SCM_MPARK_M3_PRTY_2ND (0x00800000) +#define SCM_MPARK_M3_PRTY_1ST (0x00C00000) +#define SCM_MPARK_M2_PRTY_MSK (0x00300000) +#define SCM_MPARK_M2_PRTY_4TH (0x00000000) +#define SCM_MPARK_M2_PRTY_3RD (0x00100000) +#define SCM_MPARK_M2_PRTY_2ND (0x00200000) +#define SCM_MPARK_M2_PRTY_1ST (0x00300000) +#define SCM_MPARK_M0_PRTY_MSK (0x000C0000) +#define SCM_MPARK_M0_PRTY_4TH (0x00000000) +#define SCM_MPARK_M0_PRTY_3RD (0x00040000) +#define SCM_MPARK_M0_PRTY_2ND (0x00080000) +#define SCM_MPARK_M0_PRTY_1ST (0x000C0000) +#define SCM_MPARK_FIXED (0x00004000) +#define SCM_MPARK_TIMEOUT (0x00002000) +#define SCM_MPARK_PRKLAST (0x00001000) +#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) + +/* Bit definitions and macros for SCM_MPR */ +#define SCM_MPR_MPR3 (0x08) +#define SCM_MPR_MPR2 (0x04) +#define SCM_MPR_MPR1 (0x02) +#define SCM_MPR_MPR0 (0x01) + +/* Bit definitions and macros for SCM_PACRn */ +#define SCM_PACRn_LOCK1 (0x80) +#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4) +#define SCM_PACRn_LOCK0 (0x08) +#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) + +/* Bit definitions and macros for SCM_GPACR */ +#define SCM_PACRn_LOCK (0x80) +#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ +/* Bit definitions and macros for SDRAMC_DCR */ +#define SDRAMC_DCR_NAM (0x2000) +#define SDRAMC_DCR_COC (0x1000) +#define SDRAMC_DCR_IS (0x0800) +#define SDRAMC_DCR_RTIM_MASK (0x0C00) +#define SDRAMC_DCR_RTIM_3CLKS (0x0000) +#define SDRAMC_DCR_RTIM_6CLKS (0x0200) +#define SDRAMC_DCR_RTIM_9CLKS (0x0400) +#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8) + +/* Bit definitions and macros for SDRAMC_DARCn */ +#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18) +#define SDRAMC_DARCn_RE (0x00008000) +#define SDRAMC_DARCn_CASL_MASK (0x00003000) +#define SDRAMC_DARCn_CASL_C0 (0x00000000) +#define SDRAMC_DARCn_CASL_C1 (0x00001000) +#define SDRAMC_DARCn_CASL_C2 (0x00002000) +#define SDRAMC_DARCn_CASL_C3 (0x00003000) +#define SDRAMC_DARCn_CBM_MASK (0x00000700) +#define SDRAMC_DARCn_CBM_CMD17 (0x00000000) +#define SDRAMC_DARCn_CBM_CMD18 (0x00000100) +#define SDRAMC_DARCn_CBM_CMD19 (0x00000200) +#define SDRAMC_DARCn_CBM_CMD20 (0x00000300) +#define SDRAMC_DARCn_CBM_CMD21 (0x00000400) +#define SDRAMC_DARCn_CBM_CMD22 (0x00000500) +#define SDRAMC_DARCn_CBM_CMD23 (0x00000600) +#define SDRAMC_DARCn_CBM_CMD24 (0x00000700) +#define SDRAMC_DARCn_IMRS (0x00000040) +#define SDRAMC_DARCn_PS_MASK (0x00000030) +#define SDRAMC_DARCn_PS_32 (0x00000000) +#define SDRAMC_DARCn_PS_16 (0x00000010) +#define SDRAMC_DARCn_PS_8 (0x00000020) +#define SDRAMC_DARCn_IP (0x00000008) + +/* Bit definitions and macros for SDRAMC_DMRn */ +#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18) +#define SDRAMC_DMRn_WP (0x00000100) +#define SDRAMC_DMRn_V (0x00000001) + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ +/* Bit definitions and macros for FBCS_CSMR */ +#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16) +#define FBCS_CSMR_BAM_4G (0xFFFF0000) +#define FBCS_CSMR_BAM_2G (0x7FFF0000) +#define FBCS_CSMR_BAM_1G (0x3FFF0000) +#define FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define FBCS_CSMR_BAM_512M (0x1FFF0000) +#define FBCS_CSMR_BAM_256M (0x0FFF0000) +#define FBCS_CSMR_BAM_128M (0x07FF0000) +#define FBCS_CSMR_BAM_64M (0x03FF0000) +#define FBCS_CSMR_BAM_32M (0x01FF0000) +#define FBCS_CSMR_BAM_16M (0x00FF0000) +#define FBCS_CSMR_BAM_8M (0x007F0000) +#define FBCS_CSMR_BAM_4M (0x003F0000) +#define FBCS_CSMR_BAM_2M (0x001F0000) +#define FBCS_CSMR_BAM_1M (0x000F0000) +#define FBCS_CSMR_BAM_1024K (0x000F0000) +#define FBCS_CSMR_BAM_512K (0x00070000) +#define FBCS_CSMR_BAM_256K (0x00030000) +#define FBCS_CSMR_BAM_128K (0x00010000) +#define FBCS_CSMR_BAM_64K (0x00000000) +#define FBCS_CSMR_WP (0x00000100) +#define FBCS_CSMR_V (0x00000001) + +/* Bit definitions and macros for FBCS_CSCR */ +#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14) +#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10) +#define FBCS_CSCR_AA (0x0100) +#define FBCS_CSCR_PS_MASK (0x00C0) +#define FBCS_CSCR_PS_32 (0x0000) +#define FBCS_CSCR_PS_16 (0x0080) +#define FBCS_CSCR_PS_8 (0x0040) +#define FBCS_CSCR_BEM (0x0020) +#define FBCS_CSCR_BSTR (0x0010) +#define FBCS_CSCR_BSTW (0x0008) +#define FBCS_CSCR_SWWS(x) ((x)&0x07) + +/********************************************************************* +* Queued Serial Peripheral Interface (QSPI) +*********************************************************************/ +/* Bit definitions and macros for QSPI_QMR */ +#define QSPI_QMR_MSTR (0x8000) +#define QSPI_QMR_DOHIE (0x4000) +#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define QSPI_QMR_CPOL (0x0200) +#define QSPI_QMR_CPHA (0x0100) +#define QSPI_QMR_BAUD(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QDLYR */ +#define QSPI_QDLYR_SPE (0x8000) +#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QWR */ +#define QSPI_QWR_HALT (0x8000) +#define QSPI_QWR_WREN (0x4000) +#define QSPI_QWR_WRTO (0x2000) +#define QSPI_QWR_CSIV (0x1000) +#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define QSPI_QWR_NEWQP(x) ((x)&0x000F) + +/* Bit definitions and macros for QSPI_QIR */ +#define QSPI_QIR_WCEFB (0x8000) +#define QSPI_QIR_ABRTB (0x4000) +#define QSPI_QIR_ABRTL (0x1000) +#define QSPI_QIR_WCEFE (0x0800) +#define QSPI_QIR_ABRTE (0x0400) +#define QSPI_QIR_SPIFE (0x0100) +#define QSPI_QIR_WCEF (0x0008) +#define QSPI_QIR_ABRT (0x0004) +#define QSPI_QIR_SPIF (0x0001) + +/* Bit definitions and macros for QSPI_QAR */ +#define QSPI_QAR_ADDR(x) ((x)&0x003F) + +/* Bit definitions and macros for QSPI_QDR */ +#define QSPI_QDR_CONT (0x8000) +#define QSPI_QDR_BITSE (0x4000) +#define QSPI_QDR_DT (0x2000) +#define QSPI_QDR_DSCK (0x1000) +#define QSPI_QDR_QSPI_CS3 (0x0800) +#define QSPI_QDR_QSPI_CS2 (0x0400) +#define QSPI_QDR_QSPI_CS1 (0x0200) +#define QSPI_QDR_QSPI_CS0 (0x0100) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_SCM (8) +#define INT0_LO_DMA0 (9) +#define INT0_LO_DMA1 (10) +#define INT0_LO_DMA2 (11) +#define INT0_LO_DMA3 (12) +#define INT0_LO_UART0 (13) +#define INT0_LO_UART1 (14) +#define INT0_LO_UART2 (15) +#define INT0_LO_RSVD1 (16) +#define INT0_LO_I2C (17) +#define INT0_LO_QSPI (18) +#define INT0_LO_DTMR0 (19) +#define INT0_LO_DTMR1 (20) +#define INT0_LO_DTMR2 (21) +#define INT0_LO_DTMR3 (22) +#define INT0_LO_FEC_TXF (23) +#define INT0_LO_FEC_TXB (24) +#define INT0_LO_FEC_UN (25) +#define INT0_LO_FEC_RL (26) +#define INT0_LO_FEC_RXF (27) +#define INT0_LO_FEC_RXB (28) +#define INT0_LO_FEC_MII (29) +#define INT0_LO_FEC_LC (30) +#define INT0_LO_FEC_HBERR (31) +#define INT0_HI_FEC_GRA (32) +#define INT0_HI_FEC_EBERR (33) +#define INT0_HI_FEC_BABT (34) +#define INT0_HI_FEC_BABR (35) +#define INT0_HI_PIT0 (36) +#define INT0_HI_PIT1 (37) +#define INT0_HI_PIT2 (38) +#define INT0_HI_PIT3 (39) +#define INT0_HI_RNG (40) +#define INT0_HI_SKHA (41) +#define INT0_HI_MDHA (42) +#define INT0_HI_CAN1_BUF0I (43) +#define INT0_HI_CAN1_BUF1I (44) +#define INT0_HI_CAN1_BUF2I (45) +#define INT0_HI_CAN1_BUF3I (46) +#define INT0_HI_CAN1_BUF4I (47) +#define INT0_HI_CAN1_BUF5I (48) +#define INT0_HI_CAN1_BUF6I (49) +#define INT0_HI_CAN1_BUF7I (50) +#define INT0_HI_CAN1_BUF8I (51) +#define INT0_HI_CAN1_BUF9I (52) +#define INT0_HI_CAN1_BUF10I (53) +#define INT0_HI_CAN1_BUF11I (54) +#define INT0_HI_CAN1_BUF12I (55) +#define INT0_HI_CAN1_BUF13I (56) +#define INT0_HI_CAN1_BUF14I (57) +#define INT0_HI_CAN1_BUF15I (58) +#define INT0_HI_CAN1_ERRINT (59) +#define INT0_HI_CAN1_BOFFINT (60) +/* 60-63 Reserved */ + +/* 0 - 7 Reserved */ +#define INT1_LO_CAN1_BUF0I (8) +#define INT1_LO_CAN1_BUF1I (9) +#define INT1_LO_CAN1_BUF2I (10) +#define INT1_LO_CAN1_BUF3I (11) +#define INT1_LO_CAN1_BUF4I (12) +#define INT1_LO_CAN1_BUF5I (13) +#define INT1_LO_CAN1_BUF6I (14) +#define INT1_LO_CAN1_BUF7I (15) +#define INT1_LO_CAN1_BUF8I (16) +#define INT1_LO_CAN1_BUF9I (17) +#define INT1_LO_CAN1_BUF10I (18) +#define INT1_LO_CAN1_BUF11I (19) +#define INT1_LO_CAN1_BUF12I (20) +#define INT1_LO_CAN1_BUF13I (21) +#define INT1_LO_CAN1_BUF14I (22) +#define INT1_LO_CAN1_BUF15I (23) +#define INT1_LO_CAN1_ERRINT (24) +#define INT1_LO_CAN1_BOFFINT (25) +/* 26 Reserved */ +#define INT1_LO_ETPU_TC0F (27) +#define INT1_LO_ETPU_TC1F (28) +#define INT1_LO_ETPU_TC2F (29) +#define INT1_LO_ETPU_TC3F (30) +#define INT1_LO_ETPU_TC4F (31) +#define INT1_HI_ETPU_TC5F (32) +#define INT1_HI_ETPU_TC6F (33) +#define INT1_HI_ETPU_TC7F (34) +#define INT1_HI_ETPU_TC8F (35) +#define INT1_HI_ETPU_TC9F (36) +#define INT1_HI_ETPU_TC10F (37) +#define INT1_HI_ETPU_TC11F (38) +#define INT1_HI_ETPU_TC12F (39) +#define INT1_HI_ETPU_TC13F (40) +#define INT1_HI_ETPU_TC14F (41) +#define INT1_HI_ETPU_TC15F (42) +#define INT1_HI_ETPU_TC16F (43) +#define INT1_HI_ETPU_TC17F (44) +#define INT1_HI_ETPU_TC18F (45) +#define INT1_HI_ETPU_TC19F (46) +#define INT1_HI_ETPU_TC20F (47) +#define INT1_HI_ETPU_TC21F (48) +#define INT1_HI_ETPU_TC22F (49) +#define INT1_HI_ETPU_TC23F (50) +#define INT1_HI_ETPU_TC24F (51) +#define INT1_HI_ETPU_TC25F (52) +#define INT1_HI_ETPU_TC26F (53) +#define INT1_HI_ETPU_TC27F (54) +#define INT1_HI_ETPU_TC28F (55) +#define INT1_HI_ETPU_TC29F (56) +#define INT1_HI_ETPU_TC30F (57) +#define INT1_HI_ETPU_TC31F (58) +#define INT1_HI_ETPU_TGIF (59) + +/* Bit definitions and macros for INTC_IPRH */ +#define INTC_IPRH_INT63 (0x80000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT32 (0x00000001) + +/* Bit definitions and macros for INTC_IPRL */ +#define INTC_IPRL_INT31 (0x80000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT0 (0x00000001) + +/* Bit definitions and macros for INTC_IRLR */ +#define INTC_IRLRn(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for INTC_IACKLPRn */ +#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4) +#define INTC_IACKLPRn_PRI(x) ((x)&0x0F) + +/* Bit definitions and macros for INTC_ICRnx */ +#define INTC_ICRnx_IL(x) (((x)&0x07)<<3) +#define INTC_ICRnx_IP(x) ((x)&0x07) + +/********************************************************************* +* General Purpose I/O (GPIO) +*********************************************************************/ +/* Bit definitions and macros for GPIO_PODR */ +#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5) +#define GPIO_PODR_ADDR_MASK (0xE0) +#define GPIO_PODR_BS(x) ((x)&0x0F) +#define GPIO_PODR_BS_MASK (0x0F) +#define GPIO_PODR_CS(x) (((x)&0x7F)<<1) +#define GPIO_PODR_CS_MASK (0xFE) +#define GPIO_PODR_SDRAM(X) ((x)&0x3F) +#define GPIO_PODR_SDRAM_MASK (0x3F) +#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x) +#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK +#define GPIO_PODR_UARTH(x) ((x)&0x03) +#define GPIO_PODR_UARTH_MASK (0x03) +#define GPIO_PODR_QSPI(x) ((x)&0x1F) +#define GPIO_PODR_QSPI_MASK (0x1F) +#define GPIO_PODR_ETPU(x) ((x)&0x07) +#define GPIO_PODR_ETPU_MASK (0x07) + +/* Bit definitions and macros for GPIO_PDDR */ +#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x) +#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK +#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PPDSDR */ +#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x) +#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK +#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PCLRR */ +#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x) +#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK +#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PAR */ +#define GPIO_PAR_AD_ADDR23 (0x80) +#define GPIO_PAR_AD_ADDR22 (0x40) +#define GPIO_PAR_AD_ADDR21 (0x20) +#define GPIO_PAR_AD_DATAL (0x01) +#define GPIO_PAR_BUSCTL_OE (0x4000) +#define GPIO_PAR_BUSCTL_TA (0x1000) +#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10) +#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00) +#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400) +#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800) +#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00) +#define GPIO_PAR_BUSCTL_RWB (0x0100) +#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040) +#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010) +#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2) +#define GPIO_PAR_BUSCTL_TS_MASK (0x0C) +#define GPIO_PAR_BUSCTL_TS_GPIO (0x04) +#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08) +#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C) +#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03) +#define GPIO_PAR_BUSCTL_TIP_MASK (0x03) +#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01) +#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02) +#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03) +#define GPIO_PAR_BS(x) ((x)&0x0F) +#define GPIO_PAR_BS_MASK (0x0F) +#define GPIO_PAR_CS(x) (((x)&0x7F)<<1) +#define GPIO_PAR_CS_MASK (0xFE) +#define GPIO_PAR_CS_CS7 (0x80) +#define GPIO_PAR_CS_CS6 (0x40) +#define GPIO_PAR_CS_CS5 (0x20) +#define GPIO_PAR_CS_CS4 (0x10) +#define GPIO_PAR_CS_CS3 (0x08) +#define GPIO_PAR_CS_CS2 (0x04) +#define GPIO_PAR_CS_CS1 (0x02) +#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3 +#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2 +#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6) +#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0) +#define GPIO_PAR_SDRAM_SDWE (0x20) +#define GPIO_PAR_SDRAM_SCAS (0x10) +#define GPIO_PAR_SDRAM_SRAS (0x08) +#define GPIO_PAR_SDRAM_SCKE (0x04) +#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03) +#define GPIO_PAR_SDRAM_SDCS_MASK (0x03) +#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6) +#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0) +#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40) +#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80) +#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0) +#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4) +#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30) +#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10) +#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20) +#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) +#define GPIO_PAR_FECI2C_SCL_MASK (0x0C) +#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08) +#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C) +#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03) +#define GPIO_PAR_FECI2C_SDA_MASK (0x03) +#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02) +#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03) +#define GPIO_PAR_UART_DREQ2 (0x8000) +#define GPIO_PAR_UART_CAN1EN (0x4000) +#define GPIO_PAR_UART_U2RXD (0x2000) +#define GPIO_PAR_UART_U2TXD (0x1000) +#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10) +#define GPIO_PAR_UART_U1RXD_MASK (0x0C00) +#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) +#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8) +#define GPIO_PAR_UART_U1TXD_MASK (0x0300) +#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) +#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6) +#define GPIO_PAR_UART_U1CTS_MASK (0x00C0) +#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0) +#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4) +#define GPIO_PAR_UART_U1RTS_MASK (0x0030) +#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030) +#define GPIO_PAR_UART_U0RXD (0x0008) +#define GPIO_PAR_UART_U0TXD (0x0004) +#define GPIO_PAR_UART_U0CTS (0x0002) +#define GPIO_PAR_UART_U0RTS (0x0001) +#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6) +#define GPIO_PAR_QSPI_CS1_MASK (0xC0) +#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80) +#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0) +#define GPIO_PAR_QSPI_CS0 (0x20) +#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3) +#define GPIO_PAR_QSPI_DIN_MASK (0x18) +#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10) +#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18) +#define GPIO_PAR_QSPI_DOUT (0x04) +#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03) +#define GPIO_PAR_QSPI_SCK_MASK (0x03) +#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02) +#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03) +#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14) +#define GPIO_PAR_DT3IN_MASK (0xC000) +#define GPIO_PAR_DT3IN_QSPICS2 (0x4000) +#define GPIO_PAR_DT3IN_U2CTS (0x8000) +#define GPIO_PAR_DT3IN_DT3IN (0xC000) +#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12) +#define GPIO_PAR_DT2IN_MASK (0x3000) +#define GPIO_PAR_DT2IN_DT2OUT (0x1000) +#define GPIO_PAR_DT2IN_DREQ2 (0x2000) +#define GPIO_PAR_DT2IN_DT2IN (0x3000) +#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10) +#define GPIO_PAR_DT1IN_MASK (0x0C00) +#define GPIO_PAR_DT1IN_DT1OUT (0x0400) +#define GPIO_PAR_DT1IN_DREQ1 (0x0800) +#define GPIO_PAR_DT1IN_DT1IN (0x0C00) +#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8) +#define GPIO_PAR_DT0IN_MASK (0x0300) +#define GPIO_PAR_DT0IN_DREQ0 (0x0200) +#define GPIO_PAR_DT0IN_DT0IN (0x0300) +#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6) +#define GPIO_PAR_DT3OUT_MASK (0x00C0) +#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040) +#define GPIO_PAR_DT3OUT_U2RTS (0x0080) +#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0) +#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4) +#define GPIO_PAR_DT2OUT_MASK (0x0030) +#define GPIO_PAR_DT2OUT_DACK2 (0x0020) +#define GPIO_PAR_DT2OUT_DT2OUT (0x0030) +#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2) +#define GPIO_PAR_DT1OUT_MASK (0x000C) +#define GPIO_PAR_DT1OUT_DACK1 (0x0008) +#define GPIO_PAR_DT1OUT_DT1OUT (0x000C) +#define GPIO_PAR_DT0OUT(x) ((x)&0x03) +#define GPIO_PAR_DT0OUT_MASK (0x0003) +#define GPIO_PAR_DT0OUT_DACK0 (0x0002) +#define GPIO_PAR_DT0OUT_DT0OUT (0x0003) +#define GPIO_PAR_ETPU_TCRCLK (0x04) +#define GPIO_PAR_ETPU_UTPU_ODIS (0x02) +#define GPIO_PAR_ETPU_LTPU_ODIS (0x01) + +/* Bit definitions and macros for GPIO_DSCR */ +#define GPIO_DSCR_EIM_EIM1 (0x10) +#define GPIO_DSCR_EIM_EIM0 (0x01) +#define GPIO_DSCR_ETPU_ETPU31_24 (0x40) +#define GPIO_DSCR_ETPU_ETPU23_16 (0x10) +#define GPIO_DSCR_ETPU_ETPU15_8 (0x04) +#define GPIO_DSCR_ETPU_ETPU7_0 (0x01) +#define GPIO_DSCR_FECI2C_FEC (0x10) +#define GPIO_DSCR_FECI2C_I2C (0x01) +#define GPIO_DSCR_UART_IRQ (0x40) +#define GPIO_DSCR_UART_UART2 (0x10) +#define GPIO_DSCR_UART_UART1 (0x04) +#define GPIO_DSCR_UART_UART0 (0x01) +#define GPIO_DSCR_QSPI_QSPI (0x01) +#define GPIO_DSCR_TIMER (0x01) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ +/* Bit definitions and macros for CCM_RCR */ +#define CCM_RCR_SOFTRST (0x80) +#define CCM_RCR_FRCRSTOUT (0x40) + +/* Bit definitions and macros for CCM_RSR */ +#define CCM_RSR_SOFT (0x20) +#define CCM_RSR_WDR (0x10) +#define CCM_RSR_POR (0x08) +#define CCM_RSR_EXT (0x04) +#define CCM_RSR_LOC (0x02) +#define CCM_RSR_LOL (0x01) + +/* Bit definitions and macros for CCM_CCR */ +#define CCM_CCR_LOAD (0x8000) +#define CCM_CCR_SZEN (0x0040) +#define CCM_CCR_PSTEN (0x0020) +#define CCM_CCR_BME (0x0008) +#define CCM_CCR_BMT(x) ((x)&0x07) +#define CCM_CCR_BMT_MASK (0x0007) +#define CCM_CCR_BMT_64K (0x0000) +#define CCM_CCR_BMT_32K (0x0001) +#define CCM_CCR_BMT_16K (0x0002) +#define CCM_CCR_BMT_8K (0x0003) +#define CCM_CCR_BMT_4K (0x0004) +#define CCM_CCR_BMT_2K (0x0005) +#define CCM_CCR_BMT_1K (0x0006) +#define CCM_CCR_BMT_512 (0x0007) + +/* Bit definitions and macros for CCM_RCON */ +#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8) +#define CCM_RCON_RLOAD (0x0020) +#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) +#define CCM_RCON_BOOTPS_MASK (0x0018) +#define CCM_RCON_BOOTPS_32 (0x0018) +#define CCM_RCON_BOOTPS_16 (0x0008) +#define CCM_RCON_BOOTPS_8 (0x0010) +#define CCM_RCON_MODE (0x0001) + +/* Bit definitions and macros for CCM_CIR */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) +#define CCM_CIR_PRN(x) ((x)&0x003F) + +/********************************************************************* +* PLL Clock Module +*********************************************************************/ +/* Bit definitions and macros for PLL_SYNCR */ +#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24) +#define PLL_SYNCR_MFD_MASK (0x07000000) +#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19) +#define PLL_SYNCR_RFC_MASK (0x00380000) +#define PLL_SYNCR_LOCEN (0x00040000) +#define PLL_SYNCR_LOLRE (0x00020000) +#define PLL_SYNCR_LOCRE (0x00010000) +#define PLL_SYNCR_DISCLK (0x00008000) +#define PLL_SYNCR_LOLIRQ (0x00004000) +#define PLL_SYNCR_LOCIRQ (0x00002000) +#define PLL_SYNCR_RATE (0x00001000) +#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10) +#define PLL_SYNCR_EXP(x) ((x)&0x03FF) + +/* Bit definitions and macros for PLL_SYNSR */ +#define PLL_SYNSR_LOLF (0x00000200) +#define PLL_SYNSR_LOC (0x00000100) +#define PLL_SYNSR_MODE (0x00000080) +#define PLL_SYNSR_PLLSEL (0x00000040) +#define PLL_SYNSR_PLLREF (0x00000020) +#define PLL_SYNSR_LOCKS (0x00000010) +#define PLL_SYNSR_LOCK (0x00000008) +#define PLL_SYNSR_LOCF (0x00000004) +#define PLL_SYNSR_CALDONE (0x00000002) +#define PLL_SYNSR_CALPASS (0x00000001) + +/********************************************************************* + * Edge Port +*********************************************************************/ +#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14) +#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12) +#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10) +#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8) +#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6) +#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4) +#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2) + +#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x) +#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x) +#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x) +#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x) +#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x) +#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x) +#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x) + +#define EPORT_EPIER_EPIE7 (0x80) +#define EPORT_EPIER_EPIE6 (0x40) +#define EPORT_EPIER_EPIE5 (0x20) +#define EPORT_EPIER_EPIE4 (0x10) +#define EPORT_EPIER_EPIE3 (0x08) +#define EPORT_EPIER_EPIE2 (0x04) +#define EPORT_EPIER_EPIE1 (0x02) + +#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7 +#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6 +#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5 +#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4 +#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3 +#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2 +#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1 + +#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7 +#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6 +#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5 +#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4 +#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3 +#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2 +#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1 + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ +/* Bit definitions and macros for WTM_WCR */ +#define WTM_WCR_WAIT (0x0008) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_EN (0x0001) + +/********************************************************************* +* FlexCAN Module (CAN) +*********************************************************************/ +/* Bit definitions and macros for CAN_CANMCR */ +#define CANMCR_MDIS (0x80000000) +#define CANMCR_FRZ (0x40000000) +#define CANMCR_HALT (0x10000000) +#define CANMCR_NORDY (0x08000000) +#define CANMCR_SOFTRST (0x02000000) +#define CANMCR_FRZACK (0x01000000) +#define CANMCR_SUPV (0x00800000) +#define CANMCR_LPMACK (0x00100000) +#define CANMCR_MAXMB(x) (((x)&0x0F)) + +/* Bit definitions and macros for CAN_CANCTRL */ +#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) +#define CANCTRL_RJW(x) (((x)&0x03)<<22) +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) +#define CANCTRL_BOFFMSK (0x00008000) +#define CANCTRL_ERRMSK (0x00004000) +#define CANCTRL_CLKSRC (0x00002000) +#define CANCTRL_LPB (0x00001000) +#define CANCTRL_SMP (0x00000080) +#define CANCTRL_BOFFREC (0x00000040) +#define CANCTRL_TSYNC (0x00000020) +#define CANCTRL_LBUF (0x00000010) +#define CANCTRL_LOM (0x00000008) +#define CANCTRL_PROPSEG(x) (((x)&0x07)) + +/* Bit definitions and macros for CAN_TIMER */ +#define TIMER_TIMER(x) ((x)&0xFFFF) + +/* Bit definitions and macros for CAN_RXGMASK */ +#define RXGMASK_MI(x) ((x)&0x1FFFFFFF) + +/* Bit definitions and macros for CAN_ERRCNT */ +#define ERRCNT_TXECTR(x) (((x)&0xFF)) +#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) + +/* Bit definitions and macros for CAN_ERRSTAT */ +#define ERRSTAT_BITERR1 (0x00008000) +#define ERRSTAT_BITERR0 (0x00004000) +#define ERRSTAT_ACKERR (0x00002000) +#define ERRSTAT_CRCERR (0x00001000) +#define ERRSTAT_FRMERR (0x00000800) +#define ERRSTAT_STFERR (0x00000400) +#define ERRSTAT_TXWRN (0x00000200) +#define ERRSTAT_RXWRN (0x00000100) +#define ERRSTAT_IDLE (0x00000080) +#define ERRSTAT_TXRX (0x00000040) +#define ERRSTAT_FLT_BUSOFF (0x00000020) +#define ERRSTAT_FLT_PASSIVE (0x00000010) +#define ERRSTAT_FLT_ACTIVE (0x00000000) +#define ERRSTAT_BOFFINT (0x00000004) +#define ERRSTAT_ERRINT (0x00000002) + +/* Bit definitions and macros for CAN_IMASK */ +#define IMASK_BUF15M (0x00008000) +#define IMASK_BUF14M (0x00004000) +#define IMASK_BUF13M (0x00002000) +#define IMASK_BUF12M (0x00001000) +#define IMASK_BUF11M (0x00000800) +#define IMASK_BUF10M (0x00000400) +#define IMASK_BUF9M (0x00000200) +#define IMASK_BUF8M (0x00000100) +#define IMASK_BUF7M (0x00000080) +#define IMASK_BUF6M (0x00000040) +#define IMASK_BUF5M (0x00000020) +#define IMASK_BUF4M (0x00000010) +#define IMASK_BUF3M (0x00000008) +#define IMASK_BUF2M (0x00000004) +#define IMASK_BUF1M (0x00000002) +#define IMASK_BUF0M (0x00000001) + +/* Bit definitions and macros for CAN_IFLAG */ +#define IFLAG_BUF15I (0x00008000) +#define IFLAG_BUF14I (0x00004000) +#define IFLAG_BUF13I (0x00002000) +#define IFLAG_BUF12I (0x00001000) +#define IFLAG_BUF11I (0x00000800) +#define IFLAG_BUF10I (0x00000400) +#define IFLAG_BUF9I (0x00000200) +#define IFLAG_BUF8I (0x00000100) +#define IFLAG_BUF7I (0x00000080) +#define IFLAG_BUF6I (0x00000040) +#define IFLAG_BUF5I (0x00000020) +#define IFLAG_BUF4I (0x00000010) +#define IFLAG_BUF3I (0x00000008) +#define IFLAG_BUF2I (0x00000004) +#define IFLAG_BUF1I (0x00000002) +#define IFLAG_BUF0I (0x00000001) + +#endif /* mcf5235_h */ diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h index 8c1b077..5ed3cbc 100644 --- a/include/asm-m68k/m5249.h +++ b/include/asm-m68k/m5249.h @@ -24,7 +24,6 @@ * MA 02111-1307 USA */ - #ifndef mcf5249_h #define mcf5249_h /****************************************************************************/ @@ -32,22 +31,21 @@ /* * useful definitions for reading/writing MBAR offset memory */ -#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y - +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y /* * Size of internal RAM */ -#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ -#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ +#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ +#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ /* * Define the 5249 SIM register set addresses. @@ -56,51 +54,47 @@ /***************** ***** MBAR1 ***** *****************/ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ -#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ - -#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ -#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ -#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ -#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ -#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ -#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ -#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ -#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ -#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ -#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ - -#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ -#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ - -#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ -#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ -#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ -#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ -#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ -#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ -#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ -#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ -#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ -#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ - -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ - -/** UART Bases **/ -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ + +#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ + +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ + +#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ + +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ /***************** ***** MBAR2 ***** @@ -109,39 +103,39 @@ /* GPIO Addresses * Note: These are offset from MBAR2! */ -#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ -#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/ -#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/ -#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ -#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ -#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ -#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ -#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ - -#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ -#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ -#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ - -#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ -#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ -#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ - -#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ -#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ -#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ -#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ -#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ -#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ -#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ -#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ - -#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ -#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ - -#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ -#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ - -#define MCFSIM_PLLCR 0x180 /* PLL Control register */ +#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ +#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */ +#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */ +#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ +#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ +#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ +#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ +#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ + +#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ +#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ +#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ + +#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ +#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ +#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ + +#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ +#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ +#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ +#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ +#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ +#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ +#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ +#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ + +#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ +#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ + +#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ +#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ + +#define MCFSIM_PLLCR 0x180 /* PLL Control register */ /* * Some symbol defines for the above... @@ -158,21 +152,20 @@ /* * Bit definitions for the ICR family of registers. */ -#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ -#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ -#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ -#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ -#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ -#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ -#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ -#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ -#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ - -#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ -#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ -#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ -#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ - +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ + +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ /* * Macros to read/set IMR register. It is 32 bits on the 5249. @@ -184,4 +177,4 @@ #define mcf_setimr(imr) \ *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); -#endif /* mcf5249_h */ +#endif /* mcf5249_h */ diff --git a/include/asm-m68k/m5253.h b/include/asm-m68k/m5253.h new file mode 100644 index 0000000..eda3472 --- /dev/null +++ b/include/asm-m68k/m5253.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef m5253_h +#define m5253_h +/****************************************************************************/ + +/* +* PLL Module (PLL) +*/ + +/* Register read/write macros */ +#define PLL_PLLCR (0x000180) + +#define SIM_RSR (0x000000) +#define SIM_SYPCR (0x000001) +#define SIM_SWIVR (0x000002) +#define SIM_SWSR (0x000003) +#define SIM_MPARK (0x00000C) + +/* Bit definitions and macros for RSR */ +#define SIM_RSR_SWTR (0x20) +#define SIM_RSR_HRST (0x80) + +/* Register read/write macros */ +#define CIM_MISCCR (0x000500) +#define CIM_ATA_DADDR (0x000504) +#define CIM_ATA_DCOUNT (0x000508) +#define CIM_RTC_TIME (0x00050C) +#define CIM_USB_CANCLK (0x000510) + +/* Bit definitions and macros for MISCCR */ +#define CIM_MISCCR_ADTA (0x00000001) +#define CIM_MISCCR_ADTD (0x00000002) +#define CIM_MISCCR_ADIE (0x00000004) +#define CIM_MISCCR_ADIC (0x00000008) +#define CIM_MISCCR_ADIP (0x00000010) +#define CIM_MISCCR_CPUEND (0x00000020) +#define CIM_MISCCR_DMAEND (0x00000040) +#define CIM_MISCCR_RTCCLR (0x00000080) +#define CIM_MISCCR_RTCPL (0x00000100) +#define CIM_MISCCR_URIE (0x00000800) +#define CIM_MISCCR_URIC (0x00001000) +#define CIM_MISCCR_URIP (0x00002000) + +/* Bit definitions and macros for ATA_DADDR */ +#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2) +#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for ATA_DCOUNT */ +#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF)) + +#endif /* m5253_h */ diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h index e0f02cf..be34398 100644 --- a/include/asm-m68k/m5271.h +++ b/include/asm-m68k/m5271.h @@ -25,7 +25,6 @@ * MA 02111-1307 USA */ - #ifndef _MCF5271_H_ #define _MCF5271_H_ @@ -91,7 +90,7 @@ #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 -#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) #define MCF_SDRAMC_DCR 0x000040 #define MCF_SDRAMC_DACR0 0x000048 @@ -117,4 +116,104 @@ #define MCFSIM_ICR1 0x000C41 -#endif /* _MCF5271_H_ */ +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_SCM (8) +#define INT0_LO_DMA0 (9) +#define INT0_LO_DMA1 (10) +#define INT0_LO_DMA2 (11) +#define INT0_LO_DMA3 (12) +#define INT0_LO_UART0 (13) +#define INT0_LO_UART1 (14) +#define INT0_LO_UART2 (15) +#define INT0_LO_RSVD1 (16) +#define INT0_LO_I2C (17) +#define INT0_LO_QSPI (18) +#define INT0_LO_DTMR0 (19) +#define INT0_LO_DTMR1 (20) +#define INT0_LO_DTMR2 (21) +#define INT0_LO_DTMR3 (22) +#define INT0_LO_FEC_TXF (23) +#define INT0_LO_FEC_TXB (24) +#define INT0_LO_FEC_UN (25) +#define INT0_LO_FEC_RL (26) +#define INT0_LO_FEC_RXF (27) +#define INT0_LO_FEC_RXB (28) +#define INT0_LO_FEC_MII (29) +#define INT0_LO_FEC_LC (30) +#define INT0_LO_FEC_HBERR (31) +#define INT0_HI_FEC_GRA (32) +#define INT0_HI_FEC_EBERR (33) +#define INT0_HI_FEC_BABT (34) +#define INT0_HI_FEC_BABR (35) +#define INT0_HI_PIT0 (36) +#define INT0_HI_PIT1 (37) +#define INT0_HI_PIT2 (38) +#define INT0_HI_PIT3 (39) +#define INT0_HI_RNG (40) +#define INT0_HI_SKHA (41) +#define INT0_HI_MDHA (42) +#define INT0_HI_CAN1_BUF0I (43) +#define INT0_HI_CAN1_BUF1I (44) +#define INT0_HI_CAN1_BUF2I (45) +#define INT0_HI_CAN1_BUF3I (46) +#define INT0_HI_CAN1_BUF4I (47) +#define INT0_HI_CAN1_BUF5I (48) +#define INT0_HI_CAN1_BUF6I (49) +#define INT0_HI_CAN1_BUF7I (50) +#define INT0_HI_CAN1_BUF8I (51) +#define INT0_HI_CAN1_BUF9I (52) +#define INT0_HI_CAN1_BUF10I (53) +#define INT0_HI_CAN1_BUF11I (54) +#define INT0_HI_CAN1_BUF12I (55) +#define INT0_HI_CAN1_BUF13I (56) +#define INT0_HI_CAN1_BUF14I (57) +#define INT0_HI_CAN1_BUF15I (58) +#define INT0_HI_CAN1_ERRINT (59) +#define INT0_HI_CAN1_BOFFINT (60) +/* 60-63 Reserved */ + +/* Bit definitions and macros for INTC_IPRL */ +#define INTC_IPRL_INT31 (0x80000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT0 (0x00000001) + +#endif /* _MCF5271_H_ */ diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h index 54d4a32..895f89d 100644 --- a/include/asm-m68k/m5272.h +++ b/include/asm-m68k/m5272.h @@ -24,7 +24,6 @@ * MA 02111-1307 USA */ - #ifndef mcf5272_h #define mcf5272_h /****************************************************************************/ @@ -35,65 +34,173 @@ #define INT_RAM_SIZE 4096 +#define GPIO_PACNT_PA15MSK (0xC0000000) +#define GPIO_PACNT_DGNT1 (0x40000000) +#define GPIO_PACNT_PA14MSK (0x30000000) +#define GPIO_PACNT_DREQ1 (0x10000000) +#define GPIO_PACNT_PA13MSK (0x0C000000) +#define GPIO_PACNT_DFSC3 (0x04000000) +#define GPIO_PACNT_PA12MSK (0x03000000) +#define GPIO_PACNT_DFSC2 (0x01000000) +#define GPIO_PACNT_PA11MSK (0x00C00000) +#define GPIO_PACNT_QSPI_CS1 (0x00800000) +#define GPIO_PACNT_PA10MSK (0x00300000) +#define GPIO_PACNT_DREQ0 (0x00100000) +#define GPIO_PACNT_PA9MSK (0x000C0000) +#define GPIO_PACNT_DGNT0 (0x00040000) +#define GPIO_PACNT_PA8MSK (0x00030000) +#define GPIO_PACNT_FSC0 (0x00010000) +#define GPIO_PACNT_FSR0 (0x00010000) +#define GPIO_PACNT_PA7MSK (0x0000C000) +#define GPIO_PACNT_DOUT3 (0x00008000) +#define GPIO_PACNT_QSPI_CS3 (0x00004000) +#define GPIO_PACNT_PA6MSK (0x00003000) +#define GPIO_PACNT_USB_RXD (0x00001000) +#define GPIO_PACNT_PA5MSK (0x00000C00) +#define GPIO_PACNT_USB_TXEN (0x00000400) +#define GPIO_PACNT_PA4MSK (0x00000300) +#define GPIO_PACNT_USB_SUSP (0x00000100) +#define GPIO_PACNT_PA3MSK (0x000000C0) +#define GPIO_PACNT_USB_TN (0x00000040) +#define GPIO_PACNT_PA2MSK (0x00000030) +#define GPIO_PACNT_USB_RN (0x00000010) +#define GPIO_PACNT_PA1MSK (0x0000000C) +#define GPIO_PACNT_USB_RP (0x00000004) +#define GPIO_PACNT_PA0MSK (0x00000003) +#define GPIO_PACNT_USB_TP (0x00000001) -/* - * Define the 5272 SIM register set addresses. - */ -#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ -#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ -#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ -#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ -#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ - -#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ - -#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ -#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ -#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ -#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ +#define GPIO_PBCNT_PB15MSK (0xC0000000) +#define GPIO_PBCNT_E_MDC (0x40000000) +#define GPIO_PBCNT_PB14MSK (0x30000000) +#define GPIO_PBCNT_E_RXER (0x10000000) +#define GPIO_PBCNT_PB13MSK (0x0C000000) +#define GPIO_PBCNT_E_RXD1 (0x04000000) +#define GPIO_PBCNT_PB12MSK (0x03000000) +#define GPIO_PBCNT_E_RXD2 (0x01000000) +#define GPIO_PBCNT_PB11MSK (0x00C00000) +#define GPIO_PBCNT_E_RXD3 (0x00400000) +#define GPIO_PBCNT_PB10MSK (0x00300000) +#define GPIO_PBCNT_E_TXD1 (0x00100000) +#define GPIO_PBCNT_PB9MSK (0x000C0000) +#define GPIO_PBCNT_E_TXD2 (0x00040000) +#define GPIO_PBCNT_PB8MSK (0x00030000) +#define GPIO_PBCNT_E_TXD3 (0x00010000) +#define GPIO_PBCNT_PB7MSK (0x0000C000) +#define GPIO_PBCNT_TOUT0 (0x00004000) +#define GPIO_PBCNT_PB6MSK (0x00003000) +#define GPIO_PBCNT_TA (0x00001000) +#define GPIO_PBCNT_PB4MSK (0x00000300) +#define GPIO_PBCNT_URT0_CLK (0x00000100) +#define GPIO_PBCNT_PB3MSK (0x000000C0) +#define GPIO_PBCNT_URT0_RTS (0x00000040) +#define GPIO_PBCNT_PB2MSK (0x00000030) +#define GPIO_PBCNT_URT0_CTS (0x00000010) +#define GPIO_PBCNT_PB1MSK (0x0000000C) +#define GPIO_PBCNT_URT0_RXD (0x00000004) +#define GPIO_PBCNT_URT0_TIN2 (0x00000004) +#define GPIO_PBCNT_PB0MSK (0x00000003) +#define GPIO_PBCNT_URT0_TXD (0x00000001) -#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ -#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ -#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ -#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ +#define GPIO_PDCNT_PD7MSK (0x0000C000) +#define GPIO_PDCNT_TIN1 (0x00008000) +#define GPIO_PDCNT_PWM_OUT2 (0x00004000) +#define GPIO_PDCNT_PD6MSK (0x00003000) +#define GPIO_PDCNT_TOUT1 (0x00002000) +#define GPIO_PDCNT_PWM_OUT1 (0x00001000) +#define GPIO_PDCNT_PD5MSK (0x00000C00) +#define GPIO_PDCNT_INT4 (0x00000C00) +#define GPIO_PDCNT_DIN3 (0x00000800) +#define GPIO_PDCNT_PD4MSK (0x00000300) +#define GPIO_PDCNT_URT1_TXD (0x00000200) +#define GPIO_PDCNT_DOUT0 (0x00000100) +#define GPIO_PDCNT_PD3MSK (0x000000C0) +#define GPIO_PDCNT_INT5 (0x000000C0) +#define GPIO_PDCNT_URT1_RTS (0x00000080) +#define GPIO_PDCNT_PD2MSK (0x00000030) +#define GPIO_PDCNT_QSPI_CS2 (0x00000030) +#define GPIO_PDCNT_URT1_CTS (0x00000020) +#define GPIO_PDCNT_PD1MSK (0x0000000C) +#define GPIO_PDCNT_URT1_RXD (0x00000008) +#define GPIO_PDCNT_URT1_TIN3 (0x00000008) +#define GPIO_PDCNT_DIN0 (0x00000004) +#define GPIO_PDCNT_PD0MSK (0x00000003) +#define GPIO_PDCNT_URT1_CLK (0x00000002) +#define GPIO_PDCNT_DCL0 (0x00000001) -#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ -#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ -#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ -#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ -#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ -#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ -#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ -#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ -#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ -#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ -#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ -#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ -#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ -#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ -#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ -#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ +#define INT_RSVD0 (0) +#define INT_INT1 (1) +#define INT_INT2 (2) +#define INT_INT3 (3) +#define INT_INT4 (4) +#define INT_TMR0 (5) +#define INT_TMR1 (6) +#define INT_TMR2 (7) +#define INT_TMR3 (8) +#define INT_UART1 (9) +#define INT_UART2 (10) +#define INT_PLIP (11) +#define INT_PLIA (12) +#define INT_USB0 (13) +#define INT_USB1 (14) +#define INT_USB2 (15) +#define INT_USB3 (16) +#define INT_USB4 (17) +#define INT_USB5 (18) +#define INT_USB6 (19) +#define INT_USB7 (20) +#define INT_DMA (21) +#define INT_ERX (22) +#define INT_ETX (23) +#define INT_ENTC (24) +#define INT_QSPI (25) +#define INT_INT5 (26) +#define INT_INT6 (27) +#define INT_SWTO (28) -#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ -#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ -#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ -#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ -#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ -#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ +#define INT_ICR1_TMR0MASK (0x000F000) +#define INT_ICR1_TMR0PI (0x0008000) +#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12) +#define INT_ICR1_TMR1MASK (0x0000F00) +#define INT_ICR1_TMR1PI (0x0000800) +#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8) +#define INT_ICR1_TMR2MASK (0x00000F0) +#define INT_ICR1_TMR2PI (0x0000080) +#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4) +#define INT_ICR1_TMR3MASK (0x000000F) +#define INT_ICR1_TMR3PI (0x0000008) +#define INT_ICR1_TMR3IPL(x) (((x)&0x7)) -#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ -#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ -#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ -#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ -#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ -#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ -#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ -#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ -#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ +#define INT_ISR_INT31 (0x80000000) +#define INT_ISR_INT30 (0x40000000) +#define INT_ISR_INT29 (0x20000000) +#define INT_ISR_INT28 (0x10000000) +#define INT_ISR_INT27 (0x08000000) +#define INT_ISR_INT26 (0x04000000) +#define INT_ISR_INT25 (0x02000000) +#define INT_ISR_INT24 (0x01000000) +#define INT_ISR_INT23 (0x00800000) +#define INT_ISR_INT22 (0x00400000) +#define INT_ISR_INT21 (0x00200000) +#define INT_ISR_INT20 (0x00100000) +#define INT_ISR_INT19 (0x00080000) +#define INT_ISR_INT18 (0x00040000) +#define INT_ISR_INT17 (0x00020000) +#define INT_ISR_INT16 (0x00010000) +#define INT_ISR_INT15 (0x00008000) +#define INT_ISR_INT14 (0x00004000) +#define INT_ISR_INT13 (0x00002000) +#define INT_ISR_INT12 (0x00001000) +#define INT_ISR_INT11 (0x00000800) +#define INT_ISR_INT10 (0x00000400) +#define INT_ISR_INT9 (0x00000200) +#define INT_ISR_INT8 (0x00000100) +#define INT_ISR_INT7 (0x00000080) +#define INT_ISR_INT6 (0x00000040) +#define INT_ISR_INT5 (0x00000020) +#define INT_ISR_INT4 (0x00000010) +#define INT_ISR_INT3 (0x00000008) +#define INT_ISR_INT2 (0x00000004) +#define INT_ISR_INT1 (0x00000002) +#define INT_ISR_INT0 (0x00000001) -#endif /* mcf5272_h */ +#endif /* mcf5272_h */ diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h index e5058a4..7473bb9 100644 --- a/include/asm-m68k/m5282.h +++ b/include/asm-m68k/m5282.h @@ -23,7 +23,99 @@ /****************************************************************************/ #ifndef m5282_h #define m5282_h -/****************************************************************************/ + +/********************************************************************* +* PLL Clock Module +*********************************************************************/ +/* Bit definitions and macros for PLL_SYNCR */ +#define PLL_SYNCR_LOLRE (0x8000) +#define PLL_SYNCR_MFD2 (0x4000) +#define PLL_SYNCR_MFD1 (0x2000) +#define PLL_SYNCR_MFD0 (0x1000) +#define PLL_SYNCR_LOCRE (0x0800) +#define PLL_SYNCR_RFC2 (0x0400) +#define PLL_SYNCR_RFC1 (0x0200) +#define PLL_SYNCR_RFC0 (0x0100) +#define PLL_SYNCR_LOCEN (0x0080) +#define PLL_SYNCR_DISCLK (0x0040) +#define PLL_SYNCR_FWKUP (0x0020) +#define PLL_SYNCR_STPMD1 (0x0008) +#define PLL_SYNCR_STPMD0 (0x0004) + +/* Bit definitions and macros for PLL_SYNSR */ +#define PLL_SYNSR_MODE (0x0080) +#define PLL_SYNSR_PLLSEL (0x0040) +#define PLL_SYNSR_PLLREF (0x0020) +#define PLL_SYNSR_LOCKS (0x0010) +#define PLL_SYNSR_LOCK (0x0008) +#define PLL_SYNSR_LOCS (0x0004) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_SCM_SWT1 (8) +#define INT0_LO_DMA_00 (9) +#define INT0_LO_DMA_01 (10) +#define INT0_LO_DMA_02 (11) +#define INT0_LO_DMA_03 (12) +#define INT0_LO_UART0 (13) +#define INT0_LO_UART1 (14) +#define INT0_LO_UART2 (15) +#define INT0_LO_RSVD1 (16) +#define INT0_LO_I2C (17) +#define INT0_LO_QSPI (18) +#define INT0_LO_DTMR0 (19) +#define INT0_LO_DTMR1 (20) +#define INT0_LO_DTMR2 (21) +#define INT0_LO_DTMR3 (22) +#define INT0_LO_FEC_TXF (23) +#define INT0_LO_FEC_TXB (24) +#define INT0_LO_FEC_UN (25) +#define INT0_LO_FEC_RL (26) +#define INT0_LO_FEC_RXF (27) +#define INT0_LO_FEC_RXB (28) +#define INT0_LO_FEC_MII (29) +#define INT0_LO_FEC_LC (30) +#define INT0_LO_FEC_HBERR (31) +#define INT0_HI_FEC_GRA (32) +#define INT0_HI_FEC_EBERR (33) +#define INT0_HI_FEC_BABT (34) +#define INT0_HI_FEC_BABR (35) +#define INT0_HI_PMM_LVDF (36) +#define INT0_HI_QADC_CF1 (37) +#define INT0_HI_QADC_CF2 (38) +#define INT0_HI_QADC_PF1 (39) +#define INT0_HI_QADC_PF2 (40) +#define INT0_HI_GPTA_TOF (41) +#define INT0_HI_GPTA_PAIF (42) +#define INT0_HI_GPTA_PAOVF (43) +#define INT0_HI_GPTA_C0F (44) +#define INT0_HI_GPTA_C1F (45) +#define INT0_HI_GPTA_C2F (46) +#define INT0_HI_GPTA_C3F (47) +#define INT0_HI_GPTB_TOF (48) +#define INT0_HI_GPTB_PAIF (49) +#define INT0_HI_GPTB_PAOVF (50) +#define INT0_HI_GPTB_C0F (51) +#define INT0_HI_GPTB_C1F (52) +#define INT0_HI_GPTB_C2F (53) +#define INT0_HI_GPTB_C3F (54) +#define INT0_HI_PIT0 (55) +#define INT0_HI_PIT1 (56) +#define INT0_HI_PIT2 (57) +#define INT0_HI_PIT3 (58) +#define INT0_HI_CFM_CBEIF (59) +#define INT0_HI_CFM_CCIF (60) +#define INT0_HI_CFM_PVIF (61) +#define INT0_HI_CFM_AEIF (62) /* * Size of internal RAM @@ -96,49 +188,49 @@ #define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B)) #define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C)) #define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) - -#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) - -#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) +#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) + +#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) + +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) /* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -171,7 +263,6 @@ #define MCFGPIO_Px0 (0x01) #define MCFGPIO_Px(x) (0x01<<x) - #define MCFGPIO_PBCDPAR_PBPA (0x80) #define MCFGPIO_PBCDPAR_PCDPA (0x40) @@ -236,7 +327,7 @@ /* System Conrol Module SCM */ -#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008)) +#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008)) #define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010)) #define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011)) #define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012)) @@ -256,34 +347,33 @@ #define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030)) #define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031)) - #define MCFSCM_CRSR_EXT (0x80) #define MCFSCM_CRSR_CWDR (0x20) -#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000) -#define MCFSCM_RAMBAR_BDE (0x00000200) +#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000) +#define MCFSCM_RAMBAR_BDE (0x00000200) /* Reset Controller Module RCM */ #define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000)) #define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001)) -#define MCFRESET_RCR_SOFTRST (0x80) -#define MCFRESET_RCR_FRCRSTOUT (0x40) -#define MCFRESET_RCR_LVDF (0x10) -#define MCFRESET_RCR_LVDIE (0x08) -#define MCFRESET_RCR_LVDRE (0x04) -#define MCFRESET_RCR_LVDE (0x01) - -#define MCFRESET_RSR_LVD (0x40) -#define MCFRESET_RSR_SOFT (0x20) -#define MCFRESET_RSR_WDR (0x10) -#define MCFRESET_RSR_POR (0x08) -#define MCFRESET_RSR_EXT (0x04) -#define MCFRESET_RSR_LOC (0x02) -#define MCFRESET_RSR_LOL (0x01) -#define MCFRESET_RSR_ALL (0x7F) -#define MCFRESET_RCR_SOFTRST (0x80) -#define MCFRESET_RCR_FRCRSTOUT (0x40) +#define MCFRESET_RCR_SOFTRST (0x80) +#define MCFRESET_RCR_FRCRSTOUT (0x40) +#define MCFRESET_RCR_LVDF (0x10) +#define MCFRESET_RCR_LVDIE (0x08) +#define MCFRESET_RCR_LVDRE (0x04) +#define MCFRESET_RCR_LVDE (0x01) + +#define MCFRESET_RSR_LVD (0x40) +#define MCFRESET_RSR_SOFT (0x20) +#define MCFRESET_RSR_WDR (0x10) +#define MCFRESET_RSR_POR (0x08) +#define MCFRESET_RSR_EXT (0x04) +#define MCFRESET_RSR_LOC (0x02) +#define MCFRESET_RSR_LOL (0x01) +#define MCFRESET_RSR_ALL (0x7F) +#define MCFRESET_RCR_SOFTRST (0x80) +#define MCFRESET_RCR_FRCRSTOUT (0x40) /* Chip Configuration Module CCM */ @@ -291,26 +381,25 @@ #define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008)) #define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A)) - /* Bit level definitions and macros */ #define MCFCCM_CCR_LOAD (0x8000) #define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8) -#define MCFCCM_CCR_SZEN (0x0040) -#define MCFCCM_CCR_PSTEN (0x0020) +#define MCFCCM_CCR_SZEN (0x0040) +#define MCFCCM_CCR_PSTEN (0x0020) #define MCFCCM_CCR_BME (0x0008) -#define MCFCCM_CCR_BMT(x) (((x)&0x0007)) +#define MCFCCM_CCR_BMT(x) (((x)&0x0007)) #define MCFCCM_CIR_PIN_MASK (0xFF00) #define MCFCCM_CIR_PRN_MASK (0x00FF) /* Clock Module */ -#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000)) -#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002)) +#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000)) +#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002)) -#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) -#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) -#define MCFCLOCK_SYNSR_LOCK 0x08 +#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) +#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) +#define MCFCLOCK_SYNSR_LOCK 0x08 #define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040)) #define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048)) @@ -337,19 +426,19 @@ #define MCFSDRAMC_DACR_IMRS (0x00000040) #define MCFSDRAMC_DMR_BAM_16M (0x00FC0000) -#define MCFSDRAMC_DMR_WP (0x00000100) -#define MCFSDRAMC_DMR_CI (0x00000040) -#define MCFSDRAMC_DMR_AM (0x00000020) -#define MCFSDRAMC_DMR_SC (0x00000010) -#define MCFSDRAMC_DMR_SD (0x00000008) -#define MCFSDRAMC_DMR_UC (0x00000004) -#define MCFSDRAMC_DMR_UD (0x00000002) -#define MCFSDRAMC_DMR_V (0x00000001) - -#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000)) -#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002)) -#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004)) -#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006)) +#define MCFSDRAMC_DMR_WP (0x00000100) +#define MCFSDRAMC_DMR_CI (0x00000040) +#define MCFSDRAMC_DMR_AM (0x00000020) +#define MCFSDRAMC_DMR_SC (0x00000010) +#define MCFSDRAMC_DMR_SD (0x00000008) +#define MCFSDRAMC_DMR_UC (0x00000004) +#define MCFSDRAMC_DMR_UD (0x00000002) +#define MCFSDRAMC_DMR_V (0x00000001) + +#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000)) +#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002)) +#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004)) +#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006)) /* Chip SELECT Module CSM */ #define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080)) @@ -375,9 +464,7 @@ #define MCFCSM_CSCR_PS_16 (0x0080) /********************************************************************* -* * General Purpose Timer (GPT) Module -* *********************************************************************/ #define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000)) @@ -403,7 +490,6 @@ #define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D)) #define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E)) - #define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000)) #define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001)) #define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002)) @@ -542,4 +628,4 @@ #define MCFCFM_CMD_MASERS 0x41 /****************************************************************************/ -#endif /* m5282_h */ +#endif /* m5282_h */ diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h new file mode 100644 index 0000000..cd69fb0 --- /dev/null +++ b/include/asm-m68k/m5329.h @@ -0,0 +1,1658 @@ +/* + * mcf5329.h -- Definitions for Freescale Coldfire 5329 + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef mcf5329_h +#define mcf5329_h +/****************************************************************************/ + +/********************************************************************* +* System Control Module (SCM) +*********************************************************************/ +/* Bit definitions and macros for SCM_MPR */ +#define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) +#define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) +#define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) +#define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) +#define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) +#define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) +#define MPROT_MTR 4 +#define MPROT_MTW 2 +#define MPROT_MPL 1 + +/* Bit definitions and macros for SCM_BMT */ +#define BMT_BME (0x08) +#define BMT_8 (0x07) +#define BMT_16 (0x06) +#define BMT_32 (0x05) +#define BMT_64 (0x04) +#define BMT_128 (0x03) +#define BMT_256 (0x02) +#define BMT_512 (0x01) +#define BMT_1024 (0x00) + +/* Bit definitions and macros for SCM_PACRA */ +#define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) +#define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) +#define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) +#define PACR_SP 4 +#define PACR_WP 2 +#define PACR_TP 1 + +/* Bit definitions and macros for SCM_PACRB */ +#define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) +#define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12) + +/* Bit definitions and macros for SCM_PACRC */ +#define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28) +#define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24) +#define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20) +#define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16) +#define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8) +#define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4) +#define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRD */ +#define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28) +#define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24) +#define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20) +#define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12) +#define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8) +#define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4) +#define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRE */ +#define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28) +#define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24) +#define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20) +#define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16) +#define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12) +#define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8) +#define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4) + +/* Bit definitions and macros for SCM_PACRF */ +#define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28) +#define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24) +#define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20) +#define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16) +#define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12) +#define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8) +#define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4) +#define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRG */ +#define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28) + +/* Bit definitions and macros for SCM_PACRH */ +#define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28) +#define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24) +#define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20) + +/* PACRn Assignments */ +#define PACR0(x) SCM_PACRA_PACR0(x) +#define PACR1(x) SCM_PACRA_PACR1(x) +#define PACR2(x) SCM_PACRA_PACR2(x) +#define PACR8(x) SCM_PACRB_PACR8(x) +#define PACR12(x) SCM_PACRB_PACR12(x) +#define PACR16(x) SCM_PACRC_PACR16(x) +#define PACR17(x) SCM_PACRC_PACR17(x) +#define PACR18(x) SCM_PACRC_PACR18(x) +#define PACR19(x) SCM_PACRC_PACR19(x) +#define PACR21(x) SCM_PACRC_PACR21(x) +#define PACR22(x) SCM_PACRC_PACR22(x) +#define PACR23(x) SCM_PACRC_PACR23(x) +#define PACR24(x) SCM_PACRD_PACR24(x) +#define PACR25(x) SCM_PACRD_PACR25(x) +#define PACR26(x) SCM_PACRD_PACR26(x) +#define PACR28(x) SCM_PACRD_PACR28(x) +#define PACR29(x) SCM_PACRD_PACR29(x) +#define PACR30(x) SCM_PACRD_PACR30(x) +#define PACR31(x) SCM_PACRD_PACR31(x) +#define PACR32(x) SCM_PACRE_PACR32(x) +#define PACR33(x) SCM_PACRE_PACR33(x) +#define PACR34(x) SCM_PACRE_PACR34(x) +#define PACR35(x) SCM_PACRE_PACR35(x) +#define PACR36(x) SCM_PACRE_PACR36(x) +#define PACR37(x) SCM_PACRE_PACR37(x) +#define PACR38(x) SCM_PACRE_PACR38(x) +#define PACR40(x) SCM_PACRF_PACR40(x) +#define PACR41(x) SCM_PACRF_PACR41(x) +#define PACR42(x) SCM_PACRF_PACR42(x) +#define PACR43(x) SCM_PACRF_PACR43(x) +#define PACR44(x) SCM_PACRF_PACR44(x) +#define PACR45(x) SCM_PACRF_PACR45(x) +#define PACR46(x) SCM_PACRF_PACR46(x) +#define PACR47(x) SCM_PACRF_PACR47(x) +#define PACR48(x) SCM_PACRG_PACR48(x) +#define PACR56(x) SCM_PACRH_PACR56(x) +#define PACR57(x) SCM_PACRH_PACR57(x) +#define PACR58(x) SCM_PACRH_PACR58(x) + +/* Bit definitions and macros for SCM_CWCR */ +#define CWCR_RO (0x8000) +#define CWCR_CWR_WH (0x0100) +#define CWCR_CWE (0x0080) +#define CWRI_WINDOW (0x0060) +#define CWRI_RESET (0x0040) +#define CWRI_INT_RESET (0x0020) +#define CWRI_INT (0x0000) +#define CWCR_CWT(x) (((x)&0x001F)) + +/* Bit definitions and macros for SCM_ISR */ +#define SCMISR_CFEI (0x02) +#define SCMISR_CWIC (0x01) + +/* Bit definitions and macros for SCM_BCR */ +#define BCR_GBR (0x00000200) +#define BCR_GBW (0x00000100) +#define BCR_S7 (0x00000080) +#define BCR_S6 (0x00000040) +#define BCR_S4 (0x00000010) +#define BCR_S1 (0x00000002) + +/* Bit definitions and macros for SCM_CFIER */ +#define CFIER_ECFEI (0x01) + +/* Bit definitions and macros for SCM_CFLOC */ +#define CFLOC_LOC (0x80) + +/* Bit definitions and macros for SCM_CFATR */ +#define CFATR_WRITE (0x80) +#define CFATR_SZ32 (0x20) +#define CFATR_SZ16 (0x10) +#define CFATR_SZ08 (0x00) +#define CFATR_CACHE (0x08) +#define CFATR_MODE (0x02) +#define CFATR_TYPE (0x01) + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ +/* Bit definitions and macros for FBCS_CSAR */ +#define CSAR_BA(x) (((x)&0xFFFF)<<16) + +/* Bit definitions and macros for FBCS_CSMR */ +#define CSMR_BAM(x) (((x)&0xFFFF)<<16) +#define CSMR_BAM_4G (0xFFFF0000) +#define CSMR_BAM_2G (0x7FFF0000) +#define CSMR_BAM_1G (0x3FFF0000) +#define CSMR_BAM_1024M (0x3FFF0000) +#define CSMR_BAM_512M (0x1FFF0000) +#define CSMR_BAM_256M (0x0FFF0000) +#define CSMR_BAM_128M (0x07FF0000) +#define CSMR_BAM_64M (0x03FF0000) +#define CSMR_BAM_32M (0x01FF0000) +#define CSMR_BAM_16M (0x00FF0000) +#define CSMR_BAM_8M (0x007F0000) +#define CSMR_BAM_4M (0x003F0000) +#define CSMR_BAM_2M (0x001F0000) +#define CSMR_BAM_1M (0x000F0000) +#define CSMR_BAM_1024K (0x000F0000) +#define CSMR_BAM_512K (0x00070000) +#define CSMR_BAM_256K (0x00030000) +#define CSMR_BAM_128K (0x00010000) +#define CSMR_BAM_64K (0x00000000) +#define CSMR_WP (0x00000100) +#define CSMR_V (0x00000001) + +/* Bit definitions and macros for FBCS_CSCR */ +#define CSCR_SWS(x) (((x)&0x3F)<<26) +#define CSCR_ASET(x) (((x)&0x03)<<20) +#define CSCR_SWSEN (0x00800000) +#define CSCR_ASET_4CLK (0x00300000) +#define CSCR_ASET_3CLK (0x00200000) +#define CSCR_ASET_2CLK (0x00100000) +#define CSCR_ASET_1CLK (0x00000000) +#define CSCR_RDAH(x) (((x)&0x03)<<18) +#define CSCR_RDAH_4CYC (0x000C0000) +#define CSCR_RDAH_3CYC (0x00080000) +#define CSCR_RDAH_2CYC (0x00040000) +#define CSCR_RDAH_1CYC (0x00000000) +#define CSCR_WRAH(x) (((x)&0x03)<<16) +#define CSCR_WDAH_4CYC (0x00003000) +#define CSCR_WDAH_3CYC (0x00002000) +#define CSCR_WDAH_2CYC (0x00001000) +#define CSCR_WDAH_1CYC (0x00000000) +#define CSCR_WS(x) (((x)&0x3F)<<10) +#define CSCR_SBM (0x00000200) +#define CSCR_AA (0x00000100) +#define CSCR_PS_MASK (0x000000C0) +#define CSCR_PS_32 (0x00000000) +#define CSCR_PS_16 (0x00000080) +#define CSCR_PS_8 (0x00000040) +#define CSCR_BEM (0x00000020) +#define CSCR_BSTR (0x00000010) +#define CSCR_BSTW (0x00000008) + +/********************************************************************* +* FlexCAN Module (CAN) +*********************************************************************/ +/* Bit definitions and macros for CAN_CANMCR */ +#define CANMCR_MDIS (0x80000000) +#define CANMCR_FRZ (0x40000000) +#define CANMCR_HALT (0x10000000) +#define CANMCR_NORDY (0x08000000) +#define CANMCR_SOFTRST (0x02000000) +#define CANMCR_FRZACK (0x01000000) +#define CANMCR_SUPV (0x00800000) +#define CANMCR_LPMACK (0x00100000) +#define CANMCR_MAXMB(x) (((x)&0x0F)) + +/* Bit definitions and macros for CAN_CANCTRL */ +#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) +#define CANCTRL_RJW(x) (((x)&0x03)<<22) +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) +#define CANCTRL_BOFFMSK (0x00008000) +#define CANCTRL_ERRMSK (0x00004000) +#define CANCTRL_CLKSRC (0x00002000) +#define CANCTRL_LPB (0x00001000) +#define CANCTRL_SMP (0x00000080) +#define CANCTRL_BOFFREC (0x00000040) +#define CANCTRL_TSYNC (0x00000020) +#define CANCTRL_LBUF (0x00000010) +#define CANCTRL_LOM (0x00000008) +#define CANCTRL_PROPSEG(x) (((x)&0x07)) + +/* Bit definitions and macros for CAN_TIMER */ +#define TIMER_TIMER(x) ((x)&0xFFFF) + +/* Bit definitions and macros for CAN_RXGMASK */ +#define RXGMASK_MI(x) ((x)&0x1FFFFFFF) + +/* Bit definitions and macros for CAN_ERRCNT */ +#define ERRCNT_TXECTR(x) (((x)&0xFF)) +#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) + +/* Bit definitions and macros for CAN_ERRSTAT */ +#define ERRSTAT_BITERR1 (0x00008000) +#define ERRSTAT_BITERR0 (0x00004000) +#define ERRSTAT_ACKERR (0x00002000) +#define ERRSTAT_CRCERR (0x00001000) +#define ERRSTAT_FRMERR (0x00000800) +#define ERRSTAT_STFERR (0x00000400) +#define ERRSTAT_TXWRN (0x00000200) +#define ERRSTAT_RXWRN (0x00000100) +#define ERRSTAT_IDLE (0x00000080) +#define ERRSTAT_TXRX (0x00000040) +#define ERRSTAT_FLT_BUSOFF (0x00000020) +#define ERRSTAT_FLT_PASSIVE (0x00000010) +#define ERRSTAT_FLT_ACTIVE (0x00000000) +#define ERRSTAT_BOFFINT (0x00000004) +#define ERRSTAT_ERRINT (0x00000002) +#define ERRSTAT_WAKINT (0x00000001) + +/* Bit definitions and macros for CAN_IMASK */ +#define IMASK_BUF15M (0x00008000) +#define IMASK_BUF14M (0x00004000) +#define IMASK_BUF13M (0x00002000) +#define IMASK_BUF12M (0x00001000) +#define IMASK_BUF11M (0x00000800) +#define IMASK_BUF10M (0x00000400) +#define IMASK_BUF9M (0x00000200) +#define IMASK_BUF8M (0x00000100) +#define IMASK_BUF7M (0x00000080) +#define IMASK_BUF6M (0x00000040) +#define IMASK_BUF5M (0x00000020) +#define IMASK_BUF4M (0x00000010) +#define IMASK_BUF3M (0x00000008) +#define IMASK_BUF2M (0x00000004) +#define IMASK_BUF1M (0x00000002) +#define IMASK_BUF0M (0x00000001) + +/* Bit definitions and macros for CAN_IFLAG */ +#define IFLAG_BUF15I (0x00008000) +#define IFLAG_BUF14I (0x00004000) +#define IFLAG_BUF13I (0x00002000) +#define IFLAG_BUF12I (0x00001000) +#define IFLAG_BUF11I (0x00000800) +#define IFLAG_BUF10I (0x00000400) +#define IFLAG_BUF9I (0x00000200) +#define IFLAG_BUF8I (0x00000100) +#define IFLAG_BUF7I (0x00000080) +#define IFLAG_BUF6I (0x00000040) +#define IFLAG_BUF5I (0x00000020) +#define IFLAG_BUF4I (0x00000010) +#define IFLAG_BUF3I (0x00000008) +#define IFLAG_BUF2I (0x00000004) +#define IFLAG_BUF1I (0x00000002) +#define IFLAG_BUF0I (0x00000001) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INTC0_EPORT INTC_IPRL_INT1 + +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC_TXF (36) +#define INT0_HI_FEC_TXB (37) +#define INT0_HI_FEC_UN (38) +#define INT0_HI_FEC_RL (39) +#define INT0_HI_FEC_RXF (40) +#define INT0_HI_FEC_RXB (41) +#define INT0_HI_FEC_MII (42) +#define INT0_HI_FEC_LC (43) +#define INT0_HI_FEC_HBERR (44) +#define INT0_HI_FEC_GRA (45) +#define INT0_HI_FEC_EBERR (46) +#define INT0_HI_FEC_BABT (47) +#define INT0_HI_FEC_BABR (48) +/* 49 - 61 Reserved */ +#define INT0_HI_SCM (62) + +/* Bit definitions and macros for INTC_IPRH */ +#define INTC_IPRH_INT63 (0x80000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT32 (0x00000001) + +/* Bit definitions and macros for INTC_IPRL */ +#define INTC_IPRL_INT31 (0x80000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT0 (0x00000001) + +/* Bit definitions and macros for INTC_ICONFIG */ +#define INTC_ICFG_ELVLPRI7 (0x8000) +#define INTC_ICFG_ELVLPRI6 (0x4000) +#define INTC_ICFG_ELVLPRI5 (0x2000) +#define INTC_ICFG_ELVLPRI4 (0x1000) +#define INTC_ICFG_ELVLPRI3 (0x0800) +#define INTC_ICFG_ELVLPRI2 (0x0400) +#define INTC_ICFG_ELVLPRI1 (0x0200) +#define INTC_ICFG_EMASK (0x0020) + +/* Bit definitions and macros for INTC_SIMR */ +#define INTC_SIMR_SALL (0x40) +#define INTC_SIMR_SIMR(x) ((x)&0x3F) + +/* Bit definitions and macros for INTC_CIMR */ +#define INTC_CIMR_CALL (0x40) +#define INTC_CIMR_CIMR(x) ((x)&0x3F) + +/* Bit definitions and macros for INTC_CLMASK */ +#define INTC_CLMASK_CLMASK(x) ((x)&0x0F) + +/* Bit definitions and macros for INTC_SLMASK */ +#define INTC_SLMASK_SLMASK(x) ((x)&0x0F) + +/* Bit definitions and macros for INTC_ICR */ +#define INTC_ICR_IL(x) ((x)&0x07) + +/********************************************************************* +* Queued Serial Peripheral Interface (QSPI) +*********************************************************************/ +/* Bit definitions and macros for QSPI_QMR */ +#define QSPI_QMR_MSTR (0x8000) +#define QSPI_QMR_DOHIE (0x4000) +#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define QSPI_QMR_CPOL (0x0200) +#define QSPI_QMR_CPHA (0x0100) +#define QSPI_QMR_BAUD(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QDLYR */ +#define QSPI_QDLYR_SPE (0x8000) +#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QWR */ +#define QSPI_QWR_NEWQP(x) ((x)&0x000F) +#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define QSPI_QWR_CSIV (0x1000) +#define QSPI_QWR_WRTO (0x2000) +#define QSPI_QWR_WREN (0x4000) +#define QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for QSPI_QIR */ +#define QSPI_QIR_WCEFB (0x8000) +#define QSPI_QIR_ABRTB (0x4000) +#define QSPI_QIR_ABRTL (0x1000) +#define QSPI_QIR_WCEFE (0x0800) +#define QSPI_QIR_ABRTE (0x0400) +#define QSPI_QIR_SPIFE (0x0100) +#define QSPI_QIR_WCEF (0x0008) +#define QSPI_QIR_ABRT (0x0004) +#define QSPI_QIR_SPIF (0x0001) + +/* Bit definitions and macros for QSPI_QAR */ +#define QSPI_QAR_ADDR(x) ((x)&0x003F) +#define QSPI_QAR_TRANS (0x0000) +#define QSPI_QAR_RECV (0x0010) +#define QSPI_QAR_CMD (0x0020) + +/* Bit definitions and macros for QSPI_QDR */ +#define QSPI_QDR_CONT (0x8000) +#define QSPI_QDR_BITSE (0x4000) +#define QSPI_QDR_DT (0x2000) +#define QSPI_QDR_DSCK (0x1000) +#define QSPI_QDR_QSPI_CS3 (0x0800) +#define QSPI_QDR_QSPI_CS2 (0x0400) +#define QSPI_QDR_QSPI_CS1 (0x0200) +#define QSPI_QDR_QSPI_CS0 (0x0100) + +/********************************************************************* +* Pulse Width Modulation (PWM) +*********************************************************************/ +/* Bit definitions and macros for PWM_E */ +#define PWM_EN_PWME7 (0x80) +#define PWM_EN_PWME5 (0x20) +#define PWM_EN_PWME3 (0x08) +#define PWM_EN_PWME1 (0x02) + +/* Bit definitions and macros for PWM_POL */ +#define PWM_POL_PPOL7 (0x80) +#define PWM_POL_PPOL5 (0x20) +#define PWM_POL_PPOL3 (0x08) +#define PWM_POL_PPOL1 (0x02) + +/* Bit definitions and macros for PWM_CLK */ +#define PWM_CLK_PCLK7 (0x80) +#define PWM_CLK_PCLK5 (0x20) +#define PWM_CLK_PCLK3 (0x08) +#define PWM_CLK_PCLK1 (0x02) + +/* Bit definitions and macros for PWM_PRCLK */ +#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4) +#define PWM_PRCLK_PCKA(x) ((x)&0x07) + +/* Bit definitions and macros for PWM_CAE */ +#define PWM_CAE_CAE7 (0x80) +#define PWM_CAE_CAE5 (0x20) +#define PWM_CAE_CAE3 (0x08) +#define PWM_CAE_CAE1 (0x02) + +/* Bit definitions and macros for PWM_CTL */ +#define PWM_CTL_CON67 (0x80) +#define PWM_CTL_CON45 (0x40) +#define PWM_CTL_CON23 (0x20) +#define PWM_CTL_CON01 (0x10) +#define PWM_CTL_PSWAR (0x08) +#define PWM_CTL_PFRZ (0x04) + +/* Bit definitions and macros for PWM_SDN */ +#define PWM_SDN_IF (0x80) +#define PWM_SDN_IE (0x40) +#define PWM_SDN_RESTART (0x20) +#define PWM_SDN_LVL (0x10) +#define PWM_SDN_PWM7IN (0x04) +#define PWM_SDN_PWM7IL (0x02) +#define PWM_SDN_SDNEN (0x01) + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ +/* Bit definitions and macros for WTM_WCR */ +#define WTM_WCR_WAIT (0x0008) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_EN (0x0001) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ +/* Bit definitions and macros for CCM_CCR */ +#define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) +#define CCM_CCR_LIMP (0x0041) +#define CCM_CCR_LOAD (0x0021) +#define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define CCM_CCR_OSC_MODE (0x0005) +#define CCM_CCR_PLL_MODE (0x0003) +#define CCM_CCR_RESERVED (0x0001) + +/* Bit definitions and macros for CCM_RCON */ +#define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) +#define CCM_RCON_LIMP (0x0041) +#define CCM_RCON_LOAD (0x0021) +#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define CCM_RCON_OSC_MODE (0x0005) +#define CCM_RCON_PLL_MODE (0x0003) +#define CCM_RCON_RESERVED (0x0001) + +/* Bit definitions and macros for CCM_CIR */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) +#define CCM_CIR_PRN(x) ((x)&0x003F) + +/* Bit definitions and macros for CCM_MISCCR */ +#define CCM_MISCCR_PLL_LOCK (0x2000) +#define CCM_MISCCR_LIMP (0x1000) +#define CCM_MISCCR_LCD_CHEN (0x0100) +#define CCM_MISCCR_SSI_PUE (0x0080) +#define CCM_MISCCR_SSI_PUS (0x0040) +#define CCM_MISCCR_TIM_DMA (0x0020) +#define CCM_MISCCR_SSI_SRC (0x0010) +#define CCM_MISCCR_USBDIV (0x0002) +#define CCM_MISCCR_USBSRC (0x0001) + +/* Bit definitions and macros for CCM_CDR */ +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) +#define CCM_CDR_SSIDIV(x) ((x)&0x000F) + +/* Bit definitions and macros for CCM_UHCSR */ +#define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) +#define CCM_UHCSR_WKUP (0x0004) +#define CCM_UHCSR_UHMIE (0x0002) +#define CCM_UHCSR_XPDE (0x0001) + +/* Bit definitions and macros for CCM_UOCSR */ +#define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) +#define CCM_UOCSR_DPPD (0x2000) +#define CCM_UOCSR_DMPD (0x1000) +#define CCM_UOCSR_DRV_VBUS (0x0800) +#define CCM_UOCSR_CRG_VBUS (0x0400) +#define CCM_UOCSR_DCR_VBUS (0x0200) +#define CCM_UOCSR_DPPU (0x0100) +#define CCM_UOCSR_AVLD (0x0080) +#define CCM_UOCSR_BVLD (0x0040) +#define CCM_UOCSR_VVLD (0x0020) +#define CCM_UOCSR_SEND (0x0010) +#define CCM_UOCSR_PWRFLT (0x0008) +#define CCM_UOCSR_WKUP (0x0004) +#define CCM_UOCSR_UOMIE (0x0002) +#define CCM_UOCSR_XPDE (0x0001) + +/* not done yet */ +/********************************************************************* +* General Purpose I/O (GPIO) +*********************************************************************/ +/* Bit definitions and macros for GPIO_PODR_FECH_L */ +#define GPIO_PODR_FECH_L7 (0x80) +#define GPIO_PODR_FECH_L6 (0x40) +#define GPIO_PODR_FECH_L5 (0x20) +#define GPIO_PODR_FECH_L4 (0x10) +#define GPIO_PODR_FECH_L3 (0x08) +#define GPIO_PODR_FECH_L2 (0x04) +#define GPIO_PODR_FECH_L1 (0x02) +#define GPIO_PODR_FECH_L0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_SSI */ +#define GPIO_PODR_SSI_4 (0x10) +#define GPIO_PODR_SSI_3 (0x08) +#define GPIO_PODR_SSI_2 (0x04) +#define GPIO_PODR_SSI_1 (0x02) +#define GPIO_PODR_SSI_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_BUSCTL */ +#define GPIO_PODR_BUSCTL_3 (0x08) +#define GPIO_PODR_BUSCTL_2 (0x04) +#define GPIO_PODR_BUSCTL_1 (0x02) +#define GPIO_PODR_BUSCTL_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_BE */ +#define GPIO_PODR_BE_3 (0x08) +#define GPIO_PODR_BE_2 (0x04) +#define GPIO_PODR_BE_1 (0x02) +#define GPIO_PODR_BE_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_CS */ +#define GPIO_PODR_CS_5 (0x20) +#define GPIO_PODR_CS_4 (0x10) +#define GPIO_PODR_CS_3 (0x08) +#define GPIO_PODR_CS_2 (0x04) +#define GPIO_PODR_CS_1 (0x02) + +/* Bit definitions and macros for GPIO_PODR_PWM */ +#define GPIO_PODR_PWM_5 (0x20) +#define GPIO_PODR_PWM_4 (0x10) +#define GPIO_PODR_PWM_3 (0x08) +#define GPIO_PODR_PWM_2 (0x04) + +/* Bit definitions and macros for GPIO_PODR_FECI2C */ +#define GPIO_PODR_FECI2C_3 (0x08) +#define GPIO_PODR_FECI2C_2 (0x04) +#define GPIO_PODR_FECI2C_1 (0x02) +#define GPIO_PODR_FECI2C_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_UART */ +#define GPIO_PODR_UART_7 (0x80) +#define GPIO_PODR_UART_6 (0x40) +#define GPIO_PODR_UART_5 (0x20) +#define GPIO_PODR_UART_4 (0x10) +#define GPIO_PODR_UART_3 (0x08) +#define GPIO_PODR_UART_2 (0x04) +#define GPIO_PODR_UART_1 (0x02) +#define GPIO_PODR_UART_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_QSPI */ +#define GPIO_PODR_QSPI_5 (0x20) +#define GPIO_PODR_QSPI_4 (0x10) +#define GPIO_PODR_QSPI_3 (0x08) +#define GPIO_PODR_QSPI_2 (0x04) +#define GPIO_PODR_QSPI_1 (0x02) +#define GPIO_PODR_QSPI_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_TIMER */ +#define GPIO_PODR_TIMER_3 (0x08) +#define GPIO_PODR_TIMER_2 (0x04) +#define GPIO_PODR_TIMER_1 (0x02) +#define GPIO_PODR_TIMER_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAH */ +#define GPIO_PODR_LCDDATAH_1 (0x02) +#define GPIO_PODR_LCDDATAH_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAM */ +#define GPIO_PODR_LCDDATAM_7 (0x80) +#define GPIO_PODR_LCDDATAM_6 (0x40) +#define GPIO_PODR_LCDDATAM_5 (0x20) +#define GPIO_PODR_LCDDATAM_4 (0x10) +#define GPIO_PODR_LCDDATAM_3 (0x08) +#define GPIO_PODR_LCDDATAM_2 (0x04) +#define GPIO_PODR_LCDDATAM_1 (0x02) +#define GPIO_PODR_LCDDATAM_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAL */ +#define GPIO_PODR_LCDDATAL_7 (0x80) +#define GPIO_PODR_LCDDATAL_6 (0x40) +#define GPIO_PODR_LCDDATAL_5 (0x20) +#define GPIO_PODR_LCDDATAL_4 (0x10) +#define GPIO_PODR_LCDDATAL_3 (0x08) +#define GPIO_PODR_LCDDATAL_2 (0x04) +#define GPIO_PODR_LCDDATAL_1 (0x02) +#define GPIO_PODR_LCDDATAL_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDCTLH */ +#define GPIO_PODR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDCTLL */ +#define GPIO_PODR_LCDCTLL_7 (0x80) +#define GPIO_PODR_LCDCTLL_6 (0x40) +#define GPIO_PODR_LCDCTLL_5 (0x20) +#define GPIO_PODR_LCDCTLL_4 (0x10) +#define GPIO_PODR_LCDCTLL_3 (0x08) +#define GPIO_PODR_LCDCTLL_2 (0x04) +#define GPIO_PODR_LCDCTLL_1 (0x02) +#define GPIO_PODR_LCDCTLL_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_FECH */ +#define GPIO_PDDR_FECH_L7 (0x80) +#define GPIO_PDDR_FECH_L6 (0x40) +#define GPIO_PDDR_FECH_L5 (0x20) +#define GPIO_PDDR_FECH_L4 (0x10) +#define GPIO_PDDR_FECH_L3 (0x08) +#define GPIO_PDDR_FECH_L2 (0x04) +#define GPIO_PDDR_FECH_L1 (0x02) +#define GPIO_PDDR_FECH_L0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_SSI */ +#define GPIO_PDDR_SSI_4 (0x10) +#define GPIO_PDDR_SSI_3 (0x08) +#define GPIO_PDDR_SSI_2 (0x04) +#define GPIO_PDDR_SSI_1 (0x02) +#define GPIO_PDDR_SSI_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_BUSCTL */ +#define GPIO_PDDR_BUSCTL_3 (0x08) +#define GPIO_PDDR_BUSCTL_2 (0x04) +#define GPIO_PDDR_BUSCTL_1 (0x02) +#define GPIO_PDDR_BUSCTL_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_BE */ +#define GPIO_PDDR_BE_3 (0x08) +#define GPIO_PDDR_BE_2 (0x04) +#define GPIO_PDDR_BE_1 (0x02) +#define GPIO_PDDR_BE_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_CS */ +#define GPIO_PDDR_CS_1 (0x02) +#define GPIO_PDDR_CS_2 (0x04) +#define GPIO_PDDR_CS_3 (0x08) +#define GPIO_PDDR_CS_4 (0x10) +#define GPIO_PDDR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_PWM */ +#define GPIO_PDDR_PWM_2 (0x04) +#define GPIO_PDDR_PWM_3 (0x08) +#define GPIO_PDDR_PWM_4 (0x10) +#define GPIO_PDDR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_FECI2C */ +#define GPIO_PDDR_FECI2C_0 (0x01) +#define GPIO_PDDR_FECI2C_1 (0x02) +#define GPIO_PDDR_FECI2C_2 (0x04) +#define GPIO_PDDR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PDDR_UART */ +#define GPIO_PDDR_UART_0 (0x01) +#define GPIO_PDDR_UART_1 (0x02) +#define GPIO_PDDR_UART_2 (0x04) +#define GPIO_PDDR_UART_3 (0x08) +#define GPIO_PDDR_UART_4 (0x10) +#define GPIO_PDDR_UART_5 (0x20) +#define GPIO_PDDR_UART_6 (0x40) +#define GPIO_PDDR_UART_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_QSPI */ +#define GPIO_PDDR_QSPI_0 (0x01) +#define GPIO_PDDR_QSPI_1 (0x02) +#define GPIO_PDDR_QSPI_2 (0x04) +#define GPIO_PDDR_QSPI_3 (0x08) +#define GPIO_PDDR_QSPI_4 (0x10) +#define GPIO_PDDR_QSPI_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_TIMER */ +#define GPIO_PDDR_TIMER_0 (0x01) +#define GPIO_PDDR_TIMER_1 (0x02) +#define GPIO_PDDR_TIMER_2 (0x04) +#define GPIO_PDDR_TIMER_3 (0x08) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAH */ +#define GPIO_PDDR_LCDDATAH_0 (0x01) +#define GPIO_PDDR_LCDDATAH_1 (0x02) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAM */ +#define GPIO_PDDR_LCDDATAM_0 (0x01) +#define GPIO_PDDR_LCDDATAM_1 (0x02) +#define GPIO_PDDR_LCDDATAM_2 (0x04) +#define GPIO_PDDR_LCDDATAM_3 (0x08) +#define GPIO_PDDR_LCDDATAM_4 (0x10) +#define GPIO_PDDR_LCDDATAM_5 (0x20) +#define GPIO_PDDR_LCDDATAM_6 (0x40) +#define GPIO_PDDR_LCDDATAM_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAL */ +#define GPIO_PDDR_LCDDATAL_0 (0x01) +#define GPIO_PDDR_LCDDATAL_1 (0x02) +#define GPIO_PDDR_LCDDATAL_2 (0x04) +#define GPIO_PDDR_LCDDATAL_3 (0x08) +#define GPIO_PDDR_LCDDATAL_4 (0x10) +#define GPIO_PDDR_LCDDATAL_5 (0x20) +#define GPIO_PDDR_LCDDATAL_6 (0x40) +#define GPIO_PDDR_LCDDATAL_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_LCDCTLH */ +#define GPIO_PDDR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_LCDCTLL */ +#define GPIO_PDDR_LCDCTLL_0 (0x01) +#define GPIO_PDDR_LCDCTLL_1 (0x02) +#define GPIO_PDDR_LCDCTLL_2 (0x04) +#define GPIO_PDDR_LCDCTLL_3 (0x08) +#define GPIO_PDDR_LCDCTLL_4 (0x10) +#define GPIO_PDDR_LCDCTLL_5 (0x20) +#define GPIO_PDDR_LCDCTLL_6 (0x40) +#define GPIO_PDDR_LCDCTLL_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_FECH */ +#define GPIO_PPDSDR_FECH_L0 (0x01) +#define GPIO_PPDSDR_FECH_L1 (0x02) +#define GPIO_PPDSDR_FECH_L2 (0x04) +#define GPIO_PPDSDR_FECH_L3 (0x08) +#define GPIO_PPDSDR_FECH_L4 (0x10) +#define GPIO_PPDSDR_FECH_L5 (0x20) +#define GPIO_PPDSDR_FECH_L6 (0x40) +#define GPIO_PPDSDR_FECH_L7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_SSI */ +#define GPIO_PPDSDR_SSI_0 (0x01) +#define GPIO_PPDSDR_SSI_1 (0x02) +#define GPIO_PPDSDR_SSI_2 (0x04) +#define GPIO_PPDSDR_SSI_3 (0x08) +#define GPIO_PPDSDR_SSI_4 (0x10) + +/* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */ +#define GPIO_PPDSDR_BUSCTL_0 (0x01) +#define GPIO_PPDSDR_BUSCTL_1 (0x02) +#define GPIO_PPDSDR_BUSCTL_2 (0x04) +#define GPIO_PPDSDR_BUSCTL_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_BE */ +#define GPIO_PPDSDR_BE_0 (0x01) +#define GPIO_PPDSDR_BE_1 (0x02) +#define GPIO_PPDSDR_BE_2 (0x04) +#define GPIO_PPDSDR_BE_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_CS */ +#define GPIO_PPDSDR_CS_1 (0x02) +#define GPIO_PPDSDR_CS_2 (0x04) +#define GPIO_PPDSDR_CS_3 (0x08) +#define GPIO_PPDSDR_CS_4 (0x10) +#define GPIO_PPDSDR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_PWM */ +#define GPIO_PPDSDR_PWM_2 (0x04) +#define GPIO_PPDSDR_PWM_3 (0x08) +#define GPIO_PPDSDR_PWM_4 (0x10) +#define GPIO_PPDSDR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_FECI2C */ +#define GPIO_PPDSDR_FECI2C_0 (0x01) +#define GPIO_PPDSDR_FECI2C_1 (0x02) +#define GPIO_PPDSDR_FECI2C_2 (0x04) +#define GPIO_PPDSDR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_UART */ +#define GPIO_PPDSDR_UART_0 (0x01) +#define GPIO_PPDSDR_UART_1 (0x02) +#define GPIO_PPDSDR_UART_2 (0x04) +#define GPIO_PPDSDR_UART_3 (0x08) +#define GPIO_PPDSDR_UART_4 (0x10) +#define GPIO_PPDSDR_UART_5 (0x20) +#define GPIO_PPDSDR_UART_6 (0x40) +#define GPIO_PPDSDR_UART_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_QSPI */ +#define GPIO_PPDSDR_QSPI_0 (0x01) +#define GPIO_PPDSDR_QSPI_1 (0x02) +#define GPIO_PPDSDR_QSPI_2 (0x04) +#define GPIO_PPDSDR_QSPI_3 (0x08) +#define GPIO_PPDSDR_QSPI_4 (0x10) +#define GPIO_PPDSDR_QSPI_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_TIMER */ +#define GPIO_PPDSDR_TIMER_0 (0x01) +#define GPIO_PPDSDR_TIMER_1 (0x02) +#define GPIO_PPDSDR_TIMER_2 (0x04) +#define GPIO_PPDSDR_TIMER_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */ +#define GPIO_PPDSDR_LCDDATAH_0 (0x01) +#define GPIO_PPDSDR_LCDDATAH_1 (0x02) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */ +#define GPIO_PPDSDR_LCDDATAM_0 (0x01) +#define GPIO_PPDSDR_LCDDATAM_1 (0x02) +#define GPIO_PPDSDR_LCDDATAM_2 (0x04) +#define GPIO_PPDSDR_LCDDATAM_3 (0x08) +#define GPIO_PPDSDR_LCDDATAM_4 (0x10) +#define GPIO_PPDSDR_LCDDATAM_5 (0x20) +#define GPIO_PPDSDR_LCDDATAM_6 (0x40) +#define GPIO_PPDSDR_LCDDATAM_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */ +#define GPIO_PPDSDR_LCDDATAL_0 (0x01) +#define GPIO_PPDSDR_LCDDATAL_1 (0x02) +#define GPIO_PPDSDR_LCDDATAL_2 (0x04) +#define GPIO_PPDSDR_LCDDATAL_3 (0x08) +#define GPIO_PPDSDR_LCDDATAL_4 (0x10) +#define GPIO_PPDSDR_LCDDATAL_5 (0x20) +#define GPIO_PPDSDR_LCDDATAL_6 (0x40) +#define GPIO_PPDSDR_LCDDATAL_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */ +#define GPIO_PPDSDR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */ +#define GPIO_PPDSDR_LCDCTLL_0 (0x01) +#define GPIO_PPDSDR_LCDCTLL_1 (0x02) +#define GPIO_PPDSDR_LCDCTLL_2 (0x04) +#define GPIO_PPDSDR_LCDCTLL_3 (0x08) +#define GPIO_PPDSDR_LCDCTLL_4 (0x10) +#define GPIO_PPDSDR_LCDCTLL_5 (0x20) +#define GPIO_PPDSDR_LCDCTLL_6 (0x40) +#define GPIO_PPDSDR_LCDCTLL_7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_FECH */ +#define GPIO_PCLRR_FECH_L0 (0x01) +#define GPIO_PCLRR_FECH_L1 (0x02) +#define GPIO_PCLRR_FECH_L2 (0x04) +#define GPIO_PCLRR_FECH_L3 (0x08) +#define GPIO_PCLRR_FECH_L4 (0x10) +#define GPIO_PCLRR_FECH_L5 (0x20) +#define GPIO_PCLRR_FECH_L6 (0x40) +#define GPIO_PCLRR_FECH_L7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_SSI */ +#define GPIO_PCLRR_SSI_0 (0x01) +#define GPIO_PCLRR_SSI_1 (0x02) +#define GPIO_PCLRR_SSI_2 (0x04) +#define GPIO_PCLRR_SSI_3 (0x08) +#define GPIO_PCLRR_SSI_4 (0x10) + +/* Bit definitions and macros for GPIO_PCLRR_BUSCTL */ +#define GPIO_PCLRR_BUSCTL_L0 (0x01) +#define GPIO_PCLRR_BUSCTL_L1 (0x02) +#define GPIO_PCLRR_BUSCTL_L2 (0x04) +#define GPIO_PCLRR_BUSCTL_L3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_BE */ +#define GPIO_PCLRR_BE_0 (0x01) +#define GPIO_PCLRR_BE_1 (0x02) +#define GPIO_PCLRR_BE_2 (0x04) +#define GPIO_PCLRR_BE_3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_CS */ +#define GPIO_PCLRR_CS_1 (0x02) +#define GPIO_PCLRR_CS_2 (0x04) +#define GPIO_PCLRR_CS_3 (0x08) +#define GPIO_PCLRR_CS_4 (0x10) +#define GPIO_PCLRR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_PWM */ +#define GPIO_PCLRR_PWM_2 (0x04) +#define GPIO_PCLRR_PWM_3 (0x08) +#define GPIO_PCLRR_PWM_4 (0x10) +#define GPIO_PCLRR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_FECI2C */ +#define GPIO_PCLRR_FECI2C_0 (0x01) +#define GPIO_PCLRR_FECI2C_1 (0x02) +#define GPIO_PCLRR_FECI2C_2 (0x04) +#define GPIO_PCLRR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_UART */ +#define GPIO_PCLRR_UART0 (0x01) +#define GPIO_PCLRR_UART1 (0x02) +#define GPIO_PCLRR_UART2 (0x04) +#define GPIO_PCLRR_UART3 (0x08) +#define GPIO_PCLRR_UART4 (0x10) +#define GPIO_PCLRR_UART5 (0x20) +#define GPIO_PCLRR_UART6 (0x40) +#define GPIO_PCLRR_UART7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_QSPI */ +#define GPIO_PCLRR_QSPI0 (0x01) +#define GPIO_PCLRR_QSPI1 (0x02) +#define GPIO_PCLRR_QSPI2 (0x04) +#define GPIO_PCLRR_QSPI3 (0x08) +#define GPIO_PCLRR_QSPI4 (0x10) +#define GPIO_PCLRR_QSPI5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_TIMER */ +#define GPIO_PCLRR_TIMER0 (0x01) +#define GPIO_PCLRR_TIMER1 (0x02) +#define GPIO_PCLRR_TIMER2 (0x04) +#define GPIO_PCLRR_TIMER3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */ +#define GPIO_PCLRR_LCDDATAH0 (0x01) +#define GPIO_PCLRR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */ +#define GPIO_PCLRR_LCDDATAM0 (0x01) +#define GPIO_PCLRR_LCDDATAM1 (0x02) +#define GPIO_PCLRR_LCDDATAM2 (0x04) +#define GPIO_PCLRR_LCDDATAM3 (0x08) +#define GPIO_PCLRR_LCDDATAM4 (0x10) +#define GPIO_PCLRR_LCDDATAM5 (0x20) +#define GPIO_PCLRR_LCDDATAM6 (0x40) +#define GPIO_PCLRR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */ +#define GPIO_PCLRR_LCDDATAL0 (0x01) +#define GPIO_PCLRR_LCDDATAL1 (0x02) +#define GPIO_PCLRR_LCDDATAL2 (0x04) +#define GPIO_PCLRR_LCDDATAL3 (0x08) +#define GPIO_PCLRR_LCDDATAL4 (0x10) +#define GPIO_PCLRR_LCDDATAL5 (0x20) +#define GPIO_PCLRR_LCDDATAL6 (0x40) +#define GPIO_PCLRR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */ +#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */ +#define GPIO_PCLRR_LCDCTLL0 (0x01) +#define GPIO_PCLRR_LCDCTLL1 (0x02) +#define GPIO_PCLRR_LCDCTLL2 (0x04) +#define GPIO_PCLRR_LCDCTLL3 (0x08) +#define GPIO_PCLRR_LCDCTLL4 (0x10) +#define GPIO_PCLRR_LCDCTLL5 (0x20) +#define GPIO_PCLRR_LCDCTLL6 (0x40) +#define GPIO_PCLRR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for GPIO_PAR_FEC */ +#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) +#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) +#define GPIO_PAR_FEC_7W_GPIO (0x00) +#define GPIO_PAR_FEC_7W_URTS1 (0x04) +#define GPIO_PAR_FEC_7W_FEC (0x0C) +#define GPIO_PAR_FEC_MII_GPIO (0x00) +#define GPIO_PAR_FEC_MII_UART (0x01) +#define GPIO_PAR_FEC_MII_FEC (0x03) + +/* Bit definitions and macros for GPIO_PAR_PWM */ +#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) +#define GPIO_PAR_PWM3(x) (((x)&0x03)<<2) +#define GPIO_PAR_PWM5 (0x10) +#define GPIO_PAR_PWM7 (0x20) + +/* Bit definitions and macros for GPIO_PAR_BUSCTL */ +#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3) +#define GPIO_PAR_BUSCTL_RWB (0x20) +#define GPIO_PAR_BUSCTL_TA (0x40) +#define GPIO_PAR_BUSCTL_OE (0x80) +#define GPIO_PAR_BUSCTL_OE_GPIO (0x00) +#define GPIO_PAR_BUSCTL_OE_OE (0x80) +#define GPIO_PAR_BUSCTL_TA_GPIO (0x00) +#define GPIO_PAR_BUSCTL_TA_TA (0x40) +#define GPIO_PAR_BUSCTL_RWB_GPIO (0x00) +#define GPIO_PAR_BUSCTL_RWB_RWB (0x20) +#define GPIO_PAR_BUSCTL_TS_GPIO (0x00) +#define GPIO_PAR_BUSCTL_TS_DACK0 (0x10) +#define GPIO_PAR_BUSCTL_TS_TS (0x18) + +/* Bit definitions and macros for GPIO_PAR_FECI2C */ +#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) +#define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4) +#define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6) +#define GPIO_PAR_FECI2C_MDC_GPIO (0x00) +#define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40) +#define GPIO_PAR_FECI2C_MDC_SCL (0x80) +#define GPIO_PAR_FECI2C_MDC_EMDC (0xC0) +#define GPIO_PAR_FECI2C_MDIO_GPIO (0x00) +#define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10) +#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) +#define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30) +#define GPIO_PAR_FECI2C_SCL_GPIO (0x00) +#define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04) +#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) +#define GPIO_PAR_FECI2C_SDA_GPIO (0x00) +#define GPIO_PAR_FECI2C_SDA_URXD2 (0x02) +#define GPIO_PAR_FECI2C_SDA_SDA (0x03) + +/* Bit definitions and macros for GPIO_PAR_BE */ +#define GPIO_PAR_BE0 (0x01) +#define GPIO_PAR_BE1 (0x02) +#define GPIO_PAR_BE2 (0x04) +#define GPIO_PAR_BE3 (0x08) + +/* Bit definitions and macros for GPIO_PAR_CS */ +#define GPIO_PAR_CS1 (0x02) +#define GPIO_PAR_CS2 (0x04) +#define GPIO_PAR_CS3 (0x08) +#define GPIO_PAR_CS4 (0x10) +#define GPIO_PAR_CS5 (0x20) +#define GPIO_PAR_CS1_GPIO (0x00) +#define GPIO_PAR_CS1_SDCS1 (0x01) +#define GPIO_PAR_CS1_CS1 (0x03) + +/* Bit definitions and macros for GPIO_PAR_SSI */ +#define GPIO_PAR_SSI_MCLK (0x0080) +#define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8) +#define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10) +#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12) +#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for GPIO_PAR_UART */ +#define GPIO_PAR_UART_TXD0 (0x0001) +#define GPIO_PAR_UART_RXD0 (0x0002) +#define GPIO_PAR_UART_RTS0 (0x0004) +#define GPIO_PAR_UART_CTS0 (0x0008) +#define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4) +#define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6) +#define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8) +#define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10) +#define GPIO_PAR_UART_CTS1_GPIO (0x0000) +#define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800) +#define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400) +#define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00) +#define GPIO_PAR_UART_RTS1_GPIO (0x0000) +#define GPIO_PAR_UART_RTS1_SSI_FS (0x0200) +#define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100) +#define GPIO_PAR_UART_RTS1_URTS1 (0x0300) +#define GPIO_PAR_UART_RXD1_GPIO (0x0000) +#define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080) +#define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040) +#define GPIO_PAR_UART_RXD1_URXD1 (0x00C0) +#define GPIO_PAR_UART_TXD1_GPIO (0x0000) +#define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020) +#define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010) +#define GPIO_PAR_UART_TXD1_UTXD1 (0x0030) + +/* Bit definitions and macros for GPIO_PAR_QSPI */ +#define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4) +#define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6) +#define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8) +#define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10) +#define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12) +#define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for GPIO_PAR_TIMER */ +#define GPIO_PAR_TIN0(x) (((x)&0x03)<<0) +#define GPIO_PAR_TIN1(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIN2(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIN3(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIN3_GPIO (0x00) +#define GPIO_PAR_TIN3_TOUT3 (0x80) +#define GPIO_PAR_TIN3_URXD2 (0x40) +#define GPIO_PAR_TIN3_TIN3 (0xC0) +#define GPIO_PAR_TIN2_GPIO (0x00) +#define GPIO_PAR_TIN2_TOUT2 (0x20) +#define GPIO_PAR_TIN2_UTXD2 (0x10) +#define GPIO_PAR_TIN2_TIN2 (0x30) +#define GPIO_PAR_TIN1_GPIO (0x00) +#define GPIO_PAR_TIN1_TOUT1 (0x08) +#define GPIO_PAR_TIN1_DACK1 (0x04) +#define GPIO_PAR_TIN1_TIN1 (0x0C) +#define GPIO_PAR_TIN0_GPIO (0x00) +#define GPIO_PAR_TIN0_TOUT0 (0x02) +#define GPIO_PAR_TIN0_DREQ0 (0x01) +#define GPIO_PAR_TIN0_TIN0 (0x03) + +/* Bit definitions and macros for GPIO_PAR_LCDDATA */ +#define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03) +#define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2) +#define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4) +#define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6) + +/* Bit definitions and macros for GPIO_PAR_LCDCTL */ +#define GPIO_PAR_LCDCTL_CLS (0x0001) +#define GPIO_PAR_LCDCTL_PS (0x0002) +#define GPIO_PAR_LCDCTL_REV (0x0004) +#define GPIO_PAR_LCDCTL_SPL_SPR (0x0008) +#define GPIO_PAR_LCDCTL_CONTRAST (0x0010) +#define GPIO_PAR_LCDCTL_LSCLK (0x0020) +#define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040) +#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080) +#define GPIO_PAR_LCDCTL_ACD_OE (0x0100) + +/* Bit definitions and macros for GPIO_PAR_IRQ */ +#define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4) +#define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6) +#define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8) +#define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10) +#define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12) + +/* Bit definitions and macros for GPIO_MSCR_FLEXBUS */ +#define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03) +#define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2) +#define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for GPIO_MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03) +#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for GPIO_DSCR_I2C */ +#define GPIO_DSCR_I2C_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_PWM */ +#define GPIO_DSCR_PWM_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_FEC */ +#define GPIO_DSCR_FEC_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_UART */ +#define GPIO_DSCR_UART0_DSE(x) ((x)&0x03) +#define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2) + +/* Bit definitions and macros for GPIO_DSCR_QSPI */ +#define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_TIMER */ +#define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_SSI */ +#define GPIO_DSCR_SSI_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_LCD */ +#define GPIO_DSCR_LCD_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_DEBUG */ +#define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_CLKRST */ +#define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_IRQ */ +#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03) + +/* not done yet */ +/********************************************************************* +* LCD Controller (LCDC) +*********************************************************************/ +/* Bit definitions and macros for LCDC_LSSAR */ +#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for LCDC_LSR */ +#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) +#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for LCDC_LVPWR */ +#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for LCDC_LCPR */ +#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) +#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) +#define LCDC_LCPR_OP (0x10000000) +#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) +#define LCDC_LCPR_CC_TRANSPARENT (0x00000000) +#define LCDC_LCPR_CC_OR (0x40000000) +#define LCDC_LCPR_CC_XOR (0x80000000) +#define LCDC_LCPR_CC_AND (0xC0000000) +#define LCDC_LCPR_OP_ON (0x10000000) +#define LCDC_LCPR_OP_OFF (0x00000000) + +/* Bit definitions and macros for LCDC_LCWHBR */ +#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) +#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) +#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) +#define LCDC_LCWHBR_BK_EN (0x80000000) +#define LCDC_LCWHBR_BK_EN_ON (0x80000000) +#define LCDC_LCWHBR_BK_EN_OFF (0x00000000) + +/* Bit definitions and macros for LCDC_LCCMR */ +#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) +#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) +#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) + +/* Bit definitions and macros for LCDC_LPCR */ +#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) +#define LCDC_LPCR_SHARP (0x00000040) +#define LCDC_LPCR_SCLKSEL (0x00000080) +#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) +#define LCDC_LPCR_ACDSEL (0x00008000) +#define LCDC_LPCR_REV_VS (0x00010000) +#define LCDC_LPCR_SWAP_SEL (0x00020000) +#define LCDC_LPCR_ENDSEL (0x00040000) +#define LCDC_LPCR_SCLKIDLE (0x00080000) +#define LCDC_LPCR_OEPOL (0x00100000) +#define LCDC_LPCR_CLKPOL (0x00200000) +#define LCDC_LPCR_LPPOL (0x00400000) +#define LCDC_LPCR_FLM (0x00800000) +#define LCDC_LPCR_PIXPOL (0x01000000) +#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) +#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) +#define LCDC_LPCR_COLOR (0x40000000) +#define LCDC_LPCR_TFT (0x80000000) +#define LCDC_LPCR_MODE_MONOCHROME (0x00000000) +#define LCDC_LPCR_MODE_CSTN (0x40000000) +#define LCDC_LPCR_MODE_TFT (0xC0000000) +#define LCDC_LPCR_PBSIZ_1 (0x00000000) +#define LCDC_LPCR_PBSIZ_2 (0x10000000) +#define LCDC_LPCR_PBSIZ_4 (0x20000000) +#define LCDC_LPCR_PBSIZ_8 (0x30000000) +#define LCDC_LPCR_BPIX_1bpp (0x00000000) +#define LCDC_LPCR_BPIX_2bpp (0x02000000) +#define LCDC_LPCR_BPIX_4bpp (0x04000000) +#define LCDC_LPCR_BPIX_8bpp (0x06000000) +#define LCDC_LPCR_BPIX_12bpp (0x08000000) +#define LCDC_LPCR_BPIX_16bpp (0x0A000000) +#define LCDC_LPCR_BPIX_18bpp (0x0C000000) + +#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for LCDC_LHCR */ +#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) +#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) +#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for LCDC_LVCR */ +#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) +#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) +#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for LCDC_LPOR */ +#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for LCDC_LPCCR */ +#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) +#define LCDC_LPCCR_CC_EN (0x00000100) +#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) +#define LCDC_LPCCR_LDMSK (0x00008000) +#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) +#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000) +#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000) +#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) + +/* Bit definitions and macros for LCDC_LDCR */ +#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) +#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) +#define LCDC_LDCR_BURST (0x80000000) + +/* Bit definitions and macros for LCDC_LRMCR */ +#define LCDC_LRMCR_SEL_REF (0x00000001) + +/* Bit definitions and macros for LCDC_LICR */ +#define LCDC_LICR_INTCON (0x00000001) +#define LCDC_LICR_INTSYN (0x00000004) +#define LCDC_LICR_GW_INT_CON (0x00000010) + +/* Bit definitions and macros for LCDC_LIER */ +#define LCDC_LIER_BOF_EN (0x00000001) +#define LCDC_LIER_EOF_EN (0x00000002) +#define LCDC_LIER_ERR_RES_EN (0x00000004) +#define LCDC_LIER_UDR_ERR_EN (0x00000008) +#define LCDC_LIER_GW_BOF_EN (0x00000010) +#define LCDC_LIER_GW_EOF_EN (0x00000020) +#define LCDC_LIER_GW_ERR_RES_EN (0x00000040) +#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080) + +/* Bit definitions and macros for LCDC_LISR */ +#define LCDC_LISR_BOF (0x00000001) +#define LCDC_LISR_EOF (0x00000002) +#define LCDC_LISR_ERR_RES (0x00000004) +#define LCDC_LISR_UDR_ERR (0x00000008) +#define LCDC_LISR_GW_BOF (0x00000010) +#define LCDC_LISR_GW_EOF (0x00000020) +#define LCDC_LISR_GW_ERR_RES (0x00000040) +#define LCDC_LISR_GW_UDR_ERR (0x00000080) + +/* Bit definitions and macros for LCDC_LGWSAR */ +#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for LCDC_LGWSR */ +#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for LCDC_LGWVPWR */ +#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for LCDC_LGWPOR */ +#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for LCDC_LGWPR */ +#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) + +/* Bit definitions and macros for LCDC_LGWCR */ +#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) +#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) +#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) +#define LCDC_LGWCR_GW_RVS (0x00200000) +#define LCDC_LGWCR_GWE (0x00400000) +#define LCDC_LGWCR_GWCKE (0x00800000) +#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for LCDC_LGWDCR */ +#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) +#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) +#define LCDC_LGWDCR_GWBT (0x80000000) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ +/* Bit definitions and macros for SDRAMC_SDMR */ +#define SDRAMC_SDMR_BNKAD_LEMR (0x40000000) +#define SDRAMC_SDMR_BNKAD_LMR (0x00000000) +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +#define SDRAMC_SDMR_CMD (0x00010000) + +/* Bit definitions and macros for SDRAMC_SDCR */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) +#define SDRAMC_SDCR_CKE (0x40000000) +#define SDRAMC_SDCR_DDR (0x20000000) +#define SDRAMC_SDCR_REF (0x10000000) +#define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +#define SDRAMC_SDCR_OE_RULE (0x00400000) +#define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +#define SDRAMC_SDCR_PS_32 (0x00000000) +#define SDRAMC_SDCR_PS_16 (0x00002000) +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +#define SDRAMC_SDCR_IREF (0x00000004) +#define SDRAMC_SDCR_IPALL (0x00000002) + +/* Bit definitions and macros for SDRAMC_SDCFG1 */ +#define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) +#define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +#define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +#define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) + +/* Bit definitions and macros for SDRAMC_SDCFG2 */ +#define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) +#define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +#define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) + +/* Bit definitions and macros for SDRAMC_SDDS */ +#define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) +#define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) +#define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) +#define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) +#define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003) + +/* Bit definitions and macros for SDRAMC_SDCS */ +#define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) +#define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ +/* Bit definitions and macros for SSI_CR */ +#define SSI_CR_CIS (0x00000200) +#define SSI_CR_TCH (0x00000100) +#define SSI_CR_MCE (0x00000080) +#define SSI_CR_I2S_SLAVE (0x00000040) +#define SSI_CR_I2S_MASTER (0x00000020) +#define SSI_CR_I2S_NORMAL (0x00000000) +#define SSI_CR_SYN (0x00000010) +#define SSI_CR_NET (0x00000008) +#define SSI_CR_RE (0x00000004) +#define SSI_CR_TE (0x00000002) +#define SSI_CR_SSI_EN (0x00000001) + +/* Bit definitions and macros for SSI_ISR */ +#define SSI_ISR_CMDAU (0x00040000) +#define SSI_ISR_CMDDU (0x00020000) +#define SSI_ISR_RXT (0x00010000) +#define SSI_ISR_RDR1 (0x00008000) +#define SSI_ISR_RDR0 (0x00004000) +#define SSI_ISR_TDE1 (0x00002000) +#define SSI_ISR_TDE0 (0x00001000) +#define SSI_ISR_ROE1 (0x00000800) +#define SSI_ISR_ROE0 (0x00000400) +#define SSI_ISR_TUE1 (0x00000200) +#define SSI_ISR_TUE0 (0x00000100) +#define SSI_ISR_TFS (0x00000080) +#define SSI_ISR_RFS (0x00000040) +#define SSI_ISR_TLS (0x00000020) +#define SSI_ISR_RLS (0x00000010) +#define SSI_ISR_RFF1 (0x00000008) +#define SSI_ISR_RFF0 (0x00000004) +#define SSI_ISR_TFE1 (0x00000002) +#define SSI_ISR_TFE0 (0x00000001) + +/* Bit definitions and macros for SSI_IER */ +#define SSI_IER_RDMAE (0x00400000) +#define SSI_IER_RIE (0x00200000) +#define SSI_IER_TDMAE (0x00100000) +#define SSI_IER_TIE (0x00080000) +#define SSI_IER_CMDAU (0x00040000) +#define SSI_IER_CMDU (0x00020000) +#define SSI_IER_RXT (0x00010000) +#define SSI_IER_RDR1 (0x00008000) +#define SSI_IER_RDR0 (0x00004000) +#define SSI_IER_TDE1 (0x00002000) +#define SSI_IER_TDE0 (0x00001000) +#define SSI_IER_ROE1 (0x00000800) +#define SSI_IER_ROE0 (0x00000400) +#define SSI_IER_TUE1 (0x00000200) +#define SSI_IER_TUE0 (0x00000100) +#define SSI_IER_TFS (0x00000080) +#define SSI_IER_RFS (0x00000040) +#define SSI_IER_TLS (0x00000020) +#define SSI_IER_RLS (0x00000010) +#define SSI_IER_RFF1 (0x00000008) +#define SSI_IER_RFF0 (0x00000004) +#define SSI_IER_TFE1 (0x00000002) +#define SSI_IER_TFE0 (0x00000001) + +/* Bit definitions and macros for SSI_TCR */ +#define SSI_TCR_TXBIT0 (0x00000200) +#define SSI_TCR_TFEN1 (0x00000100) +#define SSI_TCR_TFEN0 (0x00000080) +#define SSI_TCR_TFDIR (0x00000040) +#define SSI_TCR_TXDIR (0x00000020) +#define SSI_TCR_TSHFD (0x00000010) +#define SSI_TCR_TSCKP (0x00000008) +#define SSI_TCR_TFSI (0x00000004) +#define SSI_TCR_TFSL (0x00000002) +#define SSI_TCR_TEFS (0x00000001) + +/* Bit definitions and macros for SSI_RCR */ +#define SSI_RCR_RXEXT (0x00000400) +#define SSI_RCR_RXBIT0 (0x00000200) +#define SSI_RCR_RFEN1 (0x00000100) +#define SSI_RCR_RFEN0 (0x00000080) +#define SSI_RCR_RSHFD (0x00000010) +#define SSI_RCR_RSCKP (0x00000008) +#define SSI_RCR_RFSI (0x00000004) +#define SSI_RCR_RFSL (0x00000002) +#define SSI_RCR_REFS (0x00000001) + +/* Bit definitions and macros for SSI_CCR */ +#define SSI_CCR_DIV2 (0x00040000) +#define SSI_CCR_PSR (0x00020000) +#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define SSI_CCR_PM(x) ((x)&0x000000FF) + +/* Bit definitions and macros for SSI_FCSR */ +#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) +#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F) + +/* Bit definitions and macros for SSI_ACR */ +#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) +#define SSI_ACR_WR (0x00000010) +#define SSI_ACR_RD (0x00000008) +#define SSI_ACR_TIF (0x00000004) +#define SSI_ACR_FV (0x00000002) +#define SSI_ACR_AC97EN (0x00000001) + +/* Bit definitions and macros for SSI_ACADD */ +#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF) + +/* Bit definitions and macros for SSI_ACDAT */ +#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF) + +/* Bit definitions and macros for SSI_ATAG */ +#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ +/* Bit definitions and macros for PLL_PODR */ +#define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) +#define PLL_PODR_BUSDIV(x) ((x)&0x0F) + +/* Bit definitions and macros for PLL_PLLCR */ +#define PLL_PLLCR_DITHEN (0x80) +#define PLL_PLLCR_DITHDEV(x) ((x)&0x07) + +#endif /* mcf5329_h */ diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h new file mode 100644 index 0000000..8b886b0 --- /dev/null +++ b/include/asm-m68k/m5445x.h @@ -0,0 +1,1541 @@ +/* + * MCF5445x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCF5445X__ +#define __MCF5445X__ + +/********************************************************************* +* Cross-bar switch (XBS) +*********************************************************************/ + +/* Bit definitions and macros for PRS group */ +#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */ +#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */ +#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */ +#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */ +#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */ +#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */ +#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */ + +/* Bit definitions and macros for CRS group */ +#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */ +#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */ +#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */ +#define XBS_CRS_RO (0x80000000) /* Read Only */ + +#define XBS_CRS_PCTL_PARK_FIELD (0) +#define XBS_CRS_PCTL_PARK_ON_LAST (1) +#define XBS_CRS_PCTL_PARK_NONE (2) +#define XBS_CRS_PCTL_PARK_CORE (0) +#define XBS_CRS_PCTL_PARK_EDMA (1) +#define XBS_CRS_PCTL_PARK_FEC0 (2) +#define XBS_CRS_PCTL_PARK_FEC1 (3) +#define XBS_CRS_PCTL_PARK_PCI (5) +#define XBS_CRS_PCTL_PARK_USB (6) +#define XBS_CRS_PCTL_PARK_SBF (7) + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ + +/* Bit definitions and macros for CSAR group */ +#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for CSMR group */ +#define FBCS_CSMR_V (0x00000001) /* Valid bit */ +#define FBCS_CSMR_WP (0x00000100) /* Write protect */ +#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ +#define FBCS_CSMR_BAM_4G (0xFFFF0000) +#define FBCS_CSMR_BAM_2G (0x7FFF0000) +#define FBCS_CSMR_BAM_1G (0x3FFF0000) +#define FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define FBCS_CSMR_BAM_512M (0x1FFF0000) +#define FBCS_CSMR_BAM_256M (0x0FFF0000) +#define FBCS_CSMR_BAM_128M (0x07FF0000) +#define FBCS_CSMR_BAM_64M (0x03FF0000) +#define FBCS_CSMR_BAM_32M (0x01FF0000) +#define FBCS_CSMR_BAM_16M (0x00FF0000) +#define FBCS_CSMR_BAM_8M (0x007F0000) +#define FBCS_CSMR_BAM_4M (0x003F0000) +#define FBCS_CSMR_BAM_2M (0x001F0000) +#define FBCS_CSMR_BAM_1M (0x000F0000) +#define FBCS_CSMR_BAM_1024K (0x000F0000) +#define FBCS_CSMR_BAM_512K (0x00070000) +#define FBCS_CSMR_BAM_256K (0x00030000) +#define FBCS_CSMR_BAM_128K (0x00010000) +#define FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for CSCR group */ +#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */ +#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */ +#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */ +#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */ +#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */ +#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ +#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ +#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ +#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ +#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */ +#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ + +#define FBCS_CSCR_PS_8 (0x00000040) +#define FBCS_CSCR_PS_16 (0x00000080) +#define FBCS_CSCR_PS_32 (0x00000000) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC0_TXF (36) +#define INT0_HI_FEC0_TXB (37) +#define INT0_HI_FEC0_UN (38) +#define INT0_HI_FEC0_RL (39) +#define INT0_HI_FEC0_RXF (40) +#define INT0_HI_FEC0_RXB (41) +#define INT0_HI_FEC0_MII (42) +#define INT0_HI_FEC0_LC (43) +#define INT0_HI_FEC0_HBERR (44) +#define INT0_HI_FEC0_GRA (45) +#define INT0_HI_FEC0_EBERR (46) +#define INT0_HI_FEC0_BABT (47) +#define INT0_HI_FEC0_BABR (48) +#define INT0_HI_FEC1_TXF (49) +#define INT0_HI_FEC1_TXB (50) +#define INT0_HI_FEC1_UN (51) +#define INT0_HI_FEC1_RL (52) +#define INT0_HI_FEC1_RXF (53) +#define INT0_HI_FEC1_RXB (54) +#define INT0_HI_FEC1_MII (55) +#define INT0_HI_FEC1_LC (56) +#define INT0_HI_FEC1_HBERR (57) +#define INT0_HI_FEC1_GRA (58) +#define INT0_HI_FEC1_EBERR (59) +#define INT0_HI_FEC1_BABT (60) +#define INT0_HI_FEC1_BABR (61) +#define INT0_HI_SCMIR (62) +#define INT0_HI_RTC_ISR (63) + +#define INT1_HI_DSPI_EOQF (33) +#define INT1_HI_DSPI_TFFF (34) +#define INT1_HI_DSPI_TCF (35) +#define INT1_HI_DSPI_TFUF (36) +#define INT1_HI_DSPI_RFDF (37) +#define INT1_HI_DSPI_RFOF (38) +#define INT1_HI_DSPI_RFOF_TFUF (39) +#define INT1_HI_RNG_EI (40) +#define INT1_HI_PIT0_PIF (43) +#define INT1_HI_PIT1_PIF (44) +#define INT1_HI_PIT2_PIF (45) +#define INT1_HI_PIT3_PIF (46) +#define INT1_HI_USBOTG_USBSTS (47) +#define INT1_HI_SSI_ISR (49) +#define INT1_HI_CCM_UOCSR (53) +#define INT1_HI_ATA_ISR (54) +#define INT1_HI_PCI_SCR (55) +#define INT1_HI_PCI_ASR (56) +#define INT1_HI_PLL_LOCKS (57) + +/* Bit definitions and macros for IPRH */ +#define INTC_IPRH_INT32 (0x00000001) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for IPRL */ +#define INTC_IPRL_INT0 (0x00000001) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for IMRH */ +#define INTC_IMRH_INT_MASK32 (0x00000001) +#define INTC_IMRH_INT_MASK33 (0x00000002) +#define INTC_IMRH_INT_MASK34 (0x00000004) +#define INTC_IMRH_INT_MASK35 (0x00000008) +#define INTC_IMRH_INT_MASK36 (0x00000010) +#define INTC_IMRH_INT_MASK37 (0x00000020) +#define INTC_IMRH_INT_MASK38 (0x00000040) +#define INTC_IMRH_INT_MASK39 (0x00000080) +#define INTC_IMRH_INT_MASK40 (0x00000100) +#define INTC_IMRH_INT_MASK41 (0x00000200) +#define INTC_IMRH_INT_MASK42 (0x00000400) +#define INTC_IMRH_INT_MASK43 (0x00000800) +#define INTC_IMRH_INT_MASK44 (0x00001000) +#define INTC_IMRH_INT_MASK45 (0x00002000) +#define INTC_IMRH_INT_MASK46 (0x00004000) +#define INTC_IMRH_INT_MASK47 (0x00008000) +#define INTC_IMRH_INT_MASK48 (0x00010000) +#define INTC_IMRH_INT_MASK49 (0x00020000) +#define INTC_IMRH_INT_MASK50 (0x00040000) +#define INTC_IMRH_INT_MASK51 (0x00080000) +#define INTC_IMRH_INT_MASK52 (0x00100000) +#define INTC_IMRH_INT_MASK53 (0x00200000) +#define INTC_IMRH_INT_MASK54 (0x00400000) +#define INTC_IMRH_INT_MASK55 (0x00800000) +#define INTC_IMRH_INT_MASK56 (0x01000000) +#define INTC_IMRH_INT_MASK57 (0x02000000) +#define INTC_IMRH_INT_MASK58 (0x04000000) +#define INTC_IMRH_INT_MASK59 (0x08000000) +#define INTC_IMRH_INT_MASK60 (0x10000000) +#define INTC_IMRH_INT_MASK61 (0x20000000) +#define INTC_IMRH_INT_MASK62 (0x40000000) +#define INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for IMRL */ +#define INTC_IMRL_INT_MASK0 (0x00000001) +#define INTC_IMRL_INT_MASK1 (0x00000002) +#define INTC_IMRL_INT_MASK2 (0x00000004) +#define INTC_IMRL_INT_MASK3 (0x00000008) +#define INTC_IMRL_INT_MASK4 (0x00000010) +#define INTC_IMRL_INT_MASK5 (0x00000020) +#define INTC_IMRL_INT_MASK6 (0x00000040) +#define INTC_IMRL_INT_MASK7 (0x00000080) +#define INTC_IMRL_INT_MASK8 (0x00000100) +#define INTC_IMRL_INT_MASK9 (0x00000200) +#define INTC_IMRL_INT_MASK10 (0x00000400) +#define INTC_IMRL_INT_MASK11 (0x00000800) +#define INTC_IMRL_INT_MASK12 (0x00001000) +#define INTC_IMRL_INT_MASK13 (0x00002000) +#define INTC_IMRL_INT_MASK14 (0x00004000) +#define INTC_IMRL_INT_MASK15 (0x00008000) +#define INTC_IMRL_INT_MASK16 (0x00010000) +#define INTC_IMRL_INT_MASK17 (0x00020000) +#define INTC_IMRL_INT_MASK18 (0x00040000) +#define INTC_IMRL_INT_MASK19 (0x00080000) +#define INTC_IMRL_INT_MASK20 (0x00100000) +#define INTC_IMRL_INT_MASK21 (0x00200000) +#define INTC_IMRL_INT_MASK22 (0x00400000) +#define INTC_IMRL_INT_MASK23 (0x00800000) +#define INTC_IMRL_INT_MASK24 (0x01000000) +#define INTC_IMRL_INT_MASK25 (0x02000000) +#define INTC_IMRL_INT_MASK26 (0x04000000) +#define INTC_IMRL_INT_MASK27 (0x08000000) +#define INTC_IMRL_INT_MASK28 (0x10000000) +#define INTC_IMRL_INT_MASK29 (0x20000000) +#define INTC_IMRL_INT_MASK30 (0x40000000) +#define INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for INTFRCH */ +#define INTC_INTFRCH_INTFRC32 (0x00000001) +#define INTC_INTFRCH_INTFRC33 (0x00000002) +#define INTC_INTFRCH_INTFRC34 (0x00000004) +#define INTC_INTFRCH_INTFRC35 (0x00000008) +#define INTC_INTFRCH_INTFRC36 (0x00000010) +#define INTC_INTFRCH_INTFRC37 (0x00000020) +#define INTC_INTFRCH_INTFRC38 (0x00000040) +#define INTC_INTFRCH_INTFRC39 (0x00000080) +#define INTC_INTFRCH_INTFRC40 (0x00000100) +#define INTC_INTFRCH_INTFRC41 (0x00000200) +#define INTC_INTFRCH_INTFRC42 (0x00000400) +#define INTC_INTFRCH_INTFRC43 (0x00000800) +#define INTC_INTFRCH_INTFRC44 (0x00001000) +#define INTC_INTFRCH_INTFRC45 (0x00002000) +#define INTC_INTFRCH_INTFRC46 (0x00004000) +#define INTC_INTFRCH_INTFRC47 (0x00008000) +#define INTC_INTFRCH_INTFRC48 (0x00010000) +#define INTC_INTFRCH_INTFRC49 (0x00020000) +#define INTC_INTFRCH_INTFRC50 (0x00040000) +#define INTC_INTFRCH_INTFRC51 (0x00080000) +#define INTC_INTFRCH_INTFRC52 (0x00100000) +#define INTC_INTFRCH_INTFRC53 (0x00200000) +#define INTC_INTFRCH_INTFRC54 (0x00400000) +#define INTC_INTFRCH_INTFRC55 (0x00800000) +#define INTC_INTFRCH_INTFRC56 (0x01000000) +#define INTC_INTFRCH_INTFRC57 (0x02000000) +#define INTC_INTFRCH_INTFRC58 (0x04000000) +#define INTC_INTFRCH_INTFRC59 (0x08000000) +#define INTC_INTFRCH_INTFRC60 (0x10000000) +#define INTC_INTFRCH_INTFRC61 (0x20000000) +#define INTC_INTFRCH_INTFRC62 (0x40000000) +#define INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for INTFRCL */ +#define INTC_INTFRCL_INTFRC0 (0x00000001) +#define INTC_INTFRCL_INTFRC1 (0x00000002) +#define INTC_INTFRCL_INTFRC2 (0x00000004) +#define INTC_INTFRCL_INTFRC3 (0x00000008) +#define INTC_INTFRCL_INTFRC4 (0x00000010) +#define INTC_INTFRCL_INTFRC5 (0x00000020) +#define INTC_INTFRCL_INTFRC6 (0x00000040) +#define INTC_INTFRCL_INTFRC7 (0x00000080) +#define INTC_INTFRCL_INTFRC8 (0x00000100) +#define INTC_INTFRCL_INTFRC9 (0x00000200) +#define INTC_INTFRCL_INTFRC10 (0x00000400) +#define INTC_INTFRCL_INTFRC11 (0x00000800) +#define INTC_INTFRCL_INTFRC12 (0x00001000) +#define INTC_INTFRCL_INTFRC13 (0x00002000) +#define INTC_INTFRCL_INTFRC14 (0x00004000) +#define INTC_INTFRCL_INTFRC15 (0x00008000) +#define INTC_INTFRCL_INTFRC16 (0x00010000) +#define INTC_INTFRCL_INTFRC17 (0x00020000) +#define INTC_INTFRCL_INTFRC18 (0x00040000) +#define INTC_INTFRCL_INTFRC19 (0x00080000) +#define INTC_INTFRCL_INTFRC20 (0x00100000) +#define INTC_INTFRCL_INTFRC21 (0x00200000) +#define INTC_INTFRCL_INTFRC22 (0x00400000) +#define INTC_INTFRCL_INTFRC23 (0x00800000) +#define INTC_INTFRCL_INTFRC24 (0x01000000) +#define INTC_INTFRCL_INTFRC25 (0x02000000) +#define INTC_INTFRCL_INTFRC26 (0x04000000) +#define INTC_INTFRCL_INTFRC27 (0x08000000) +#define INTC_INTFRCL_INTFRC28 (0x10000000) +#define INTC_INTFRCL_INTFRC29 (0x20000000) +#define INTC_INTFRCL_INTFRC30 (0x40000000) +#define INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for ICONFIG */ +#define INTC_ICONFIG_EMASK (0x0020) +#define INTC_ICONFIG_ELVLPRI1 (0x0200) +#define INTC_ICONFIG_ELVLPRI2 (0x0400) +#define INTC_ICONFIG_ELVLPRI3 (0x0800) +#define INTC_ICONFIG_ELVLPRI4 (0x1000) +#define INTC_ICONFIG_ELVLPRI5 (0x2000) +#define INTC_ICONFIG_ELVLPRI6 (0x4000) +#define INTC_ICONFIG_ELVLPRI7 (0x8000) + +/* Bit definitions and macros for SIMR */ +#define INTC_SIMR_SIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CIMR */ +#define INTC_CIMR_CIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CLMASK */ +#define INTC_CLMASK_CLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for SLMASK */ +#define INTC_SLMASK_SLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for ICR group */ +#define INTC_ICR_IL(x) (((x)&0x07)) + +/********************************************************************* +* DMA Serial Peripheral Interface (DSPI) +*********************************************************************/ + +/* Bit definitions and macros for DMCR */ +#define DSPI_DMCR_HALT (0x00000001) +#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) +#define DSPI_DMCR_CRXF (0x00000400) +#define DSPI_DMCR_CTXF (0x00000800) +#define DSPI_DMCR_DRXF (0x00001000) +#define DSPI_DMCR_DTXF (0x00002000) +#define DSPI_DMCR_CSIS0 (0x00010000) +#define DSPI_DMCR_CSIS2 (0x00040000) +#define DSPI_DMCR_CSIS3 (0x00080000) +#define DSPI_DMCR_CSIS5 (0x00200000) +#define DSPI_DMCR_ROOE (0x01000000) +#define DSPI_DMCR_PCSSE (0x02000000) +#define DSPI_DMCR_MTFE (0x04000000) +#define DSPI_DMCR_FRZ (0x08000000) +#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) +#define DSPI_DMCR_CSCK (0x40000000) +#define DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for DTCR */ +#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for DCTAR group */ +#define DSPI_DCTAR_BR(x) (((x)&0x0000000F)) +#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) +#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) +#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) +#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) +#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) +#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) +#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) +#define DSPI_DCTAR_LSBFE (0x01000000) +#define DSPI_DCTAR_CPHA (0x02000000) +#define DSPI_DCTAR_CPOL (0x04000000) +#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) +#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000) +#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000) +#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000) +#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) +#define DSPI_DCTAR_PASC_1CLK (0x00000000) +#define DSPI_DCTAR_PASC_3CLK (0x00100000) +#define DSPI_DCTAR_PASC_5CLK (0x00200000) +#define DSPI_DCTAR_PASC_7CLK (0x00300000) +#define DSPI_DCTAR_PDT_1CLK (0x00000000) +#define DSPI_DCTAR_PDT_3CLK (0x00040000) +#define DSPI_DCTAR_PDT_5CLK (0x00080000) +#define DSPI_DCTAR_PDT_7CLK (0x000A0000) +#define DSPI_DCTAR_PBR_1CLK (0x00000000) +#define DSPI_DCTAR_PBR_3CLK (0x00010000) +#define DSPI_DCTAR_PBR_5CLK (0x00020000) +#define DSPI_DCTAR_PBR_7CLK (0x00030000) + +/* Bit definitions and macros for DSR */ +#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) +#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) +#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) +#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) +#define DSPI_DSR_RFDF (0x00020000) +#define DSPI_DSR_RFOF (0x00080000) +#define DSPI_DSR_TFFF (0x02000000) +#define DSPI_DSR_TFUF (0x08000000) +#define DSPI_DSR_EOQF (0x10000000) +#define DSPI_DSR_TXRXS (0x40000000) +#define DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for DIRSR */ +#define DSPI_DIRSR_RFDFS (0x00010000) +#define DSPI_DIRSR_RFDFE (0x00020000) +#define DSPI_DIRSR_RFOFE (0x00080000) +#define DSPI_DIRSR_TFFFS (0x01000000) +#define DSPI_DIRSR_TFFFE (0x02000000) +#define DSPI_DIRSR_TFUFE (0x08000000) +#define DSPI_DIRSR_EOQFE (0x10000000) +#define DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for DTFR */ +#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) +#define DSPI_DTFR_CS0 (0x00010000) +#define DSPI_DTFR_CS2 (0x00040000) +#define DSPI_DTFR_CS3 (0x00080000) +#define DSPI_DTFR_CS5 (0x00200000) +#define DSPI_DTFR_CTCNT (0x04000000) +#define DSPI_DTFR_EOQ (0x08000000) +#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) +#define DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for DRFR */ +#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) + +/* Bit definitions and macros for DTFDR group */ +#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) +#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for DRFDR group */ +#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) + +/********************************************************************* +* Edge Port Module (EPORT) +*********************************************************************/ + +/* Bit definitions and macros for EPPAR */ +#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define EPORT_EPPAR_LEVEL (0) +#define EPORT_EPPAR_RISING (1) +#define EPORT_EPPAR_FALLING (2) +#define EPORT_EPPAR_BOTH (3) +#define EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA7_RISING (0x4000) +#define EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA6_RISING (0x1000) +#define EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA5_RISING (0x0400) +#define EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA4_RISING (0x0100) +#define EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA3_RISING (0x0040) +#define EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA2_RISING (0x0010) +#define EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA1_RISING (0x0004) +#define EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for EPDDR */ +#define EPORT_EPDDR_EPDD1 (0x02) +#define EPORT_EPDDR_EPDD2 (0x04) +#define EPORT_EPDDR_EPDD3 (0x08) +#define EPORT_EPDDR_EPDD4 (0x10) +#define EPORT_EPDDR_EPDD5 (0x20) +#define EPORT_EPDDR_EPDD6 (0x40) +#define EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for EPIER */ +#define EPORT_EPIER_EPIE1 (0x02) +#define EPORT_EPIER_EPIE2 (0x04) +#define EPORT_EPIER_EPIE3 (0x08) +#define EPORT_EPIER_EPIE4 (0x10) +#define EPORT_EPIER_EPIE5 (0x20) +#define EPORT_EPIER_EPIE6 (0x40) +#define EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for EPDR */ +#define EPORT_EPDR_EPD1 (0x02) +#define EPORT_EPDR_EPD2 (0x04) +#define EPORT_EPDR_EPD3 (0x08) +#define EPORT_EPDR_EPD4 (0x10) +#define EPORT_EPDR_EPD5 (0x20) +#define EPORT_EPDR_EPD6 (0x40) +#define EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for EPPDR */ +#define EPORT_EPPDR_EPPD1 (0x02) +#define EPORT_EPPDR_EPPD2 (0x04) +#define EPORT_EPPDR_EPPD3 (0x08) +#define EPORT_EPPDR_EPPD4 (0x10) +#define EPORT_EPPDR_EPPD5 (0x20) +#define EPORT_EPPDR_EPPD6 (0x40) +#define EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for EPFR */ +#define EPORT_EPFR_EPF1 (0x02) +#define EPORT_EPFR_EPF2 (0x04) +#define EPORT_EPFR_EPF3 (0x08) +#define EPORT_EPFR_EPF4 (0x10) +#define EPORT_EPFR_EPF5 (0x20) +#define EPORT_EPFR_EPF6 (0x40) +#define EPORT_EPFR_EPF7 (0x80) + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ + +/* Bit definitions and macros for WCR */ +#define WTM_WCR_EN (0x0001) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_WAIT (0x0008) + +/********************************************************************* +* Serial Boot Facility (SBF) +*********************************************************************/ + +/* Bit definitions and macros for SBFCR */ +#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ +#define SBF_SBFCR_FR (0x0010) /* Fast read */ + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +/* Bit definitions and macros for RCR */ +#define RCM_RCR_FRCRSTOUT (0x40) +#define RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for RSR */ +#define RCM_RSR_LOL (0x01) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_SOFT (0x20) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +/* Bit definitions and macros for CCR_360 */ +#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ +#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ +#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ +#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ +#define CCM_CCR_360_FBCONFIG_MASK (0x00E0) +#define CCM_CCR_360_PLLMULT2_MASK (0x0003) +#define CCM_CCR_360_PLLMULT3_MASK (0x0007) +#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) +#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) +#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) +#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) +#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) +#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) +#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) +#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) +#define CCM_CCR_360_PLLMULT2_12X (0x0000) +#define CCM_CCR_360_PLLMULT2_6X (0x0001) +#define CCM_CCR_360_PLLMULT2_16X (0x0002) +#define CCM_CCR_360_PLLMULT2_8X (0x0003) +#define CCM_CCR_360_PLLMULT3_20X (0x0000) +#define CCM_CCR_360_PLLMULT3_10X (0x0001) +#define CCM_CCR_360_PLLMULT3_24X (0x0002) +#define CCM_CCR_360_PLLMULT3_18X (0x0003) +#define CCM_CCR_360_PLLMULT3_12X (0x0004) +#define CCM_CCR_360_PLLMULT3_6X (0x0005) +#define CCM_CCR_360_PLLMULT3_16X (0x0006) +#define CCM_CCR_360_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for CCR_256 */ +#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ +#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ +#define CCM_CCR_256_FBCONFIG_MASK (0x00E0) +#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) +#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) +#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) +#define CCM_CCR_256_FBCONFIG_M_32 (0x0080) +#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) +#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) +#define CCM_CCR_256_PLLMULT3_MASK (0x0007) +#define CCM_CCR_256_PLLMULT3_20X (0x0000) +#define CCM_CCR_256_PLLMULT3_10X (0x0001) +#define CCM_CCR_256_PLLMULT3_24X (0x0002) +#define CCM_CCR_256_PLLMULT3_18X (0x0003) +#define CCM_CCR_256_PLLMULT3_12X (0x0004) +#define CCM_CCR_256_PLLMULT3_6X (0x0005) +#define CCM_CCR_256_PLLMULT3_16X (0x0006) +#define CCM_CCR_256_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for RCON_360 */ +#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ +#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for RCON_256 */ +#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ +#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for CIR */ +#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ +#define CCM_CIR_PIN_MASK (0xFFC0) +#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN_MCF54450 (0x4F<<6) +#define CCM_CIR_PIN_MCF54451 (0x4D<<6) +#define CCM_CIR_PIN_MCF54452 (0x4B<<6) +#define CCM_CIR_PIN_MCF54453 (0x49<<6) +#define CCM_CIR_PIN_MCF54454 (0x4A<<6) +#define CCM_CIR_PIN_MCF54455 (0x48<<6) + +/* Bit definitions and macros for MISCCR */ +#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ +#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ +#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ +#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ +#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ +#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ +#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ +#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ +#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ +#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ +#define CCM_MISCCR_BMT_65536 (0) +#define CCM_MISCCR_BMT_32768 (1) +#define CCM_MISCCR_BMT_16384 (2) +#define CCM_MISCCR_BMT_8192 (3) +#define CCM_MISCCR_BMT_4096 (4) +#define CCM_MISCCR_BMT_2048 (5) +#define CCM_MISCCR_BMT_1024 (6) +#define CCM_MISCCR_BMT_512 (7) +#define CCM_MISCCR_SSIPUS_UP (1) +#define CCM_MISCCR_SSIPUS_DOWN (0) +#define CCM_MISCCR_TIMDMA_TIM (1) +#define CCM_MISCCR_TIMDMA_SSI (0) +#define CCM_MISCCR_SSISRC_CLKIN (0) +#define CCM_MISCCR_SSISRC_PLL (1) +#define CCM_MISCCR_USBOC_ACTHI (0) +#define CCM_MISCCR_USBOV_ACTLO (1) +#define CCM_MISCCR_USBSRC_CLKIN (0) +#define CCM_MISCCR_USBSRC_PLL (1) + +/* Bit definitions and macros for CDR */ +#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ + +/* Bit definitions and macros for UOCSR */ +#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ +#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ +#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ +#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ +#define CCM_UOCSR_SEND (0x0010) /* Session end */ +#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ +#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ +#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ +#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ +#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ +#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ +#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ +#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ + +/* Bit definitions and macros for PAR_FEC */ +#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) +#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) +#define GPIO_PAR_FEC_FEC1_MASK (0x8F) +#define GPIO_PAR_FEC_FEC1_MII (0x70) +#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) +#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) +#define GPIO_PAR_FEC_FEC1_ATA (0x10) +#define GPIO_PAR_FEC_FEC1_GPIO (0x00) +#define GPIO_PAR_FEC_FEC0_MASK (0xF8) +#define GPIO_PAR_FEC_FEC0_MII (0x07) +#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) +#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02) +#define GPIO_PAR_FEC_FEC0_ATA (0x01) +#define GPIO_PAR_FEC_FEC0_GPIO (0x00) + +/* Bit definitions and macros for PAR_DMA */ +#define GPIO_PAR_DMA_DREQ0 (0x01) +#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) +#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) +#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) +#define GPIO_PAR_DMA_DACK1_MASK (0x3F) +#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) +#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) +#define GPIO_PAR_DMA_DACK1_GPIO (0x00) +#define GPIO_PAR_DMA_DREQ1_MASK (0xCF) +#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) +#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) +#define GPIO_PAR_DMA_DREQ1_GPIO (0x00) +#define GPIO_PAR_DMA_DACK0_MASK (0xF3) +#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) +#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) +#define GPIO_PAR_DMA_DACK0_GPIO (0x00) +#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) +#define GPIO_PAR_DMA_DREQ0_GPIO (0x00) + +/* Bit definitions and macros for PAR_FBCTL */ +#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) +#define GPIO_PAR_FBCTL_RW (0x20) +#define GPIO_PAR_FBCTL_TA (0x40) +#define GPIO_PAR_FBCTL_OE (0x80) +#define GPIO_PAR_FBCTL_OE_OE (0x80) +#define GPIO_PAR_FBCTL_OE_GPIO (0x00) +#define GPIO_PAR_FBCTL_TA_TA (0x40) +#define GPIO_PAR_FBCTL_TA_GPIO (0x00) +#define GPIO_PAR_FBCTL_RW_RW (0x20) +#define GPIO_PAR_FBCTL_RW_GPIO (0x00) +#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_TS (0x18) +#define GPIO_PAR_FBCTL_TS_ALE (0x10) +#define GPIO_PAR_FBCTL_TS_TBST (0x08) +#define GPIO_PAR_FBCTL_TS_GPIO (0x80) + +/* Bit definitions and macros for PAR_DSPI */ +#define GPIO_PAR_DSPI_SCK (0x01) +#define GPIO_PAR_DSPI_SOUT (0x02) +#define GPIO_PAR_DSPI_SIN (0x04) +#define GPIO_PAR_DSPI_PCS0 (0x08) +#define GPIO_PAR_DSPI_PCS1 (0x10) +#define GPIO_PAR_DSPI_PCS2 (0x20) +#define GPIO_PAR_DSPI_PCS5 (0x40) +#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) +#define GPIO_PAR_DSPI_PCS5_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) +#define GPIO_PAR_DSPI_PCS2_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) +#define GPIO_PAR_DSPI_PCS1_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) +#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) +#define GPIO_PAR_DSPI_SIN_SIN (0x04) +#define GPIO_PAR_DSPI_SIN_GPIO (0x00) +#define GPIO_PAR_DSPI_SOUT_SOUT (0x02) +#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) +#define GPIO_PAR_DSPI_SCK_SCK (0x01) +#define GPIO_PAR_DSPI_SCK_GPIO (0x00) + +/* Bit definitions and macros for PAR_BE */ +#define GPIO_PAR_BE_BS0 (0x01) +#define GPIO_PAR_BE_BS1 (0x04) +#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) +#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) +#define GPIO_PAR_BE_BE3_MASK (0x3F) +#define GPIO_PAR_BE_BE3_BE3 (0xC0) +#define GPIO_PAR_BE_BE3_TSIZ1 (0x80) +#define GPIO_PAR_BE_BE3_GPIO (0x00) +#define GPIO_PAR_BE_BE2_MASK (0xCF) +#define GPIO_PAR_BE_BE2_BE2 (0x30) +#define GPIO_PAR_BE_BE2_TSIZ0 (0x20) +#define GPIO_PAR_BE_BE2_GPIO (0x00) +#define GPIO_PAR_BE_BE1_BE1 (0x04) +#define GPIO_PAR_BE_BE1_GPIO (0x00) +#define GPIO_PAR_BE_BE0_BE0 (0x01) +#define GPIO_PAR_BE_BE0_GPIO (0x00) + +/* Bit definitions and macros for PAR_CS */ +#define GPIO_PAR_CS_CS1 (0x02) +#define GPIO_PAR_CS_CS2 (0x04) +#define GPIO_PAR_CS_CS3 (0x08) +#define GPIO_PAR_CS_CS3_CS3 (0x08) +#define GPIO_PAR_CS_CS3_GPIO (0x00) +#define GPIO_PAR_CS_CS2_CS2 (0x04) +#define GPIO_PAR_CS_CS2_GPIO (0x00) +#define GPIO_PAR_CS_CS1_CS1 (0x02) +#define GPIO_PAR_CS_CS1_GPIO (0x00) + +/* Bit definitions and macros for PAR_TIMER */ +#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) +#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) +#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) +#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) +#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) +#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) +#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) +#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) +#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) +#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) +#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) +#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) +#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) +#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) + +/* Bit definitions and macros for PAR_USB */ +#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) +#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) +#define GPIO_PAR_USB_VBUSEN_MASK (0xF3) +#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) +#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) +#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) +#define GPIO_PAR_USB_VBUSEN_GPIO (0x00) +#define GPIO_PAR_USB_VBUSOC_MASK (0xFC) +#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) +#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) +#define GPIO_PAR_USB_VBUSOC_GPIO (0x00) + +/* Bit definitions and macros for PAR_UART */ +#define GPIO_PAR_UART_U0TXD (0x01) +#define GPIO_PAR_UART_U0RXD (0x02) +#define GPIO_PAR_UART_U0RTS (0x04) +#define GPIO_PAR_UART_U0CTS (0x08) +#define GPIO_PAR_UART_U1TXD (0x10) +#define GPIO_PAR_UART_U1RXD (0x20) +#define GPIO_PAR_UART_U1RTS (0x40) +#define GPIO_PAR_UART_U1CTS (0x80) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x80) +#define GPIO_PAR_UART_U1CTS_GPIO (0x00) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x40) +#define GPIO_PAR_UART_U1RTS_GPIO (0x00) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x20) +#define GPIO_PAR_UART_U1RXD_GPIO (0x00) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x10) +#define GPIO_PAR_UART_U1TXD_GPIO (0x00) +#define GPIO_PAR_UART_U0CTS_U0CTS (0x08) +#define GPIO_PAR_UART_U0CTS_GPIO (0x00) +#define GPIO_PAR_UART_U0RTS_U0RTS (0x04) +#define GPIO_PAR_UART_U0RTS_GPIO (0x00) +#define GPIO_PAR_UART_U0RXD_U0RXD (0x02) +#define GPIO_PAR_UART_U0RXD_GPIO (0x00) +#define GPIO_PAR_UART_U0TXD_U0TXD (0x01) +#define GPIO_PAR_UART_U0TXD_GPIO (0x00) + +/* Bit definitions and macros for PAR_FECI2C */ +#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) +#define GPIO_PAR_FECI2C_MDIO0 (0x0010) +#define GPIO_PAR_FECI2C_MDC0 (0x0040) +#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) +#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) +#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) +#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) +#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) +#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) +#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) +#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) +#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) +#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) +#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) +#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) +#define GPIO_PAR_FECI2C_SCL_SCL (0x000C) +#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) +#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) +#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) +#define GPIO_PAR_FECI2C_SDA_SDA (0x0003) +#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) +#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) + +/* Bit definitions and macros for PAR_SSI */ +#define GPIO_PAR_SSI_MCLK (0x0001) +#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) +#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) +#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) +#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) +#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF) +#define GPIO_PAR_SSI_BCLK_BCLK (0x0300) +#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) +#define GPIO_PAR_SSI_BCLK_GPIO (0x0000) +#define GPIO_PAR_SSI_FS_MASK (0xFF3F) +#define GPIO_PAR_SSI_FS_FS (0x00C0) +#define GPIO_PAR_SSI_FS_U1RTS (0x0080) +#define GPIO_PAR_SSI_FS_GPIO (0x0000) +#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF) +#define GPIO_PAR_SSI_SRXD_SRXD (0x0030) +#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) +#define GPIO_PAR_SSI_SRXD_GPIO (0x0000) +#define GPIO_PAR_SSI_STXD_MASK (0xFFF3) +#define GPIO_PAR_SSI_STXD_STXD (0x000C) +#define GPIO_PAR_SSI_STXD_U1TXD (0x0008) +#define GPIO_PAR_SSI_STXD_GPIO (0x0000) +#define GPIO_PAR_SSI_MCLK_MCLK (0x0001) +#define GPIO_PAR_SSI_MCLK_GPIO (0x0000) + +/* Bit definitions and macros for PAR_ATA */ +#define GPIO_PAR_ATA_IORDY (0x0001) +#define GPIO_PAR_ATA_DMARQ (0x0002) +#define GPIO_PAR_ATA_RESET (0x0004) +#define GPIO_PAR_ATA_DA0 (0x0020) +#define GPIO_PAR_ATA_DA1 (0x0040) +#define GPIO_PAR_ATA_DA2 (0x0080) +#define GPIO_PAR_ATA_CS0 (0x0100) +#define GPIO_PAR_ATA_CS1 (0x0200) +#define GPIO_PAR_ATA_BUFEN (0x0400) +#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) +#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) +#define GPIO_PAR_ATA_CS1_CS1 (0x0200) +#define GPIO_PAR_ATA_CS1_GPIO (0x0000) +#define GPIO_PAR_ATA_CS0_CS0 (0x0100) +#define GPIO_PAR_ATA_CS0_GPIO (0x0000) +#define GPIO_PAR_ATA_DA2_DA2 (0x0080) +#define GPIO_PAR_ATA_DA2_GPIO (0x0000) +#define GPIO_PAR_ATA_DA1_DA1 (0x0040) +#define GPIO_PAR_ATA_DA1_GPIO (0x0000) +#define GPIO_PAR_ATA_DA0_DA0 (0x0020) +#define GPIO_PAR_ATA_DA0_GPIO (0x0000) +#define GPIO_PAR_ATA_RESET_RESET (0x0004) +#define GPIO_PAR_ATA_RESET_GPIO (0x0000) +#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) +#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) +#define GPIO_PAR_ATA_IORDY_IORDY (0x0001) +#define GPIO_PAR_ATA_IORDY_GPIO (0x0000) + +/* Bit definitions and macros for PAR_IRQ */ +#define GPIO_PAR_IRQ_IRQ1 (0x02) +#define GPIO_PAR_IRQ_IRQ4 (0x10) +#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) +#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) +#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) +#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) + +/* Bit definitions and macros for PAR_PCI */ +#define GPIO_PAR_PCI_REQ0 (0x0001) +#define GPIO_PAR_PCI_REQ1 (0x0004) +#define GPIO_PAR_PCI_REQ2 (0x0010) +#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) +#define GPIO_PAR_PCI_GNT0 (0x0100) +#define GPIO_PAR_PCI_GNT1 (0x0400) +#define GPIO_PAR_PCI_GNT2 (0x1000) +#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) +#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF) +#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) +#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) +#define GPIO_PAR_PCI_GNT3_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) +#define GPIO_PAR_PCI_GNT2_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) +#define GPIO_PAR_PCI_GNT1_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) +#define GPIO_PAR_PCI_GNT0_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F) +#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) +#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) +#define GPIO_PAR_PCI_REQ3_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) +#define GPIO_PAR_PCI_REQ2_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) +#define GPIO_PAR_PCI_REQ1_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) +#define GPIO_PAR_PCI_REQ0_GPIO (0x0000) + +/* Bit definitions and macros for MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) +#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) +#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) +#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) +#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) +#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) +#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) +#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) +#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) +#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) +#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) +#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) +#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) +#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) +#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) +#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) +#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) + +/* Bit definitions and macros for MSCR_PCI */ +#define GPIO_MSCR_PCI_PCI (0x01) +#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) +#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) + +/* Bit definitions and macros for DSCR_I2C */ +#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) +#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) +#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) +#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) +#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FLEXBUS */ +#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) +#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) +#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) +#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FEC */ +#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) +#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) +#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) +#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) +#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) +#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) +#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) +#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) +#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) +#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_UART */ +#define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) +#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) +#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) +#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) +#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) +#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) +#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) +#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) +#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) +#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DSPI */ +#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) +#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) +#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) +#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) +#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_TIMER */ +#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) +#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) +#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) +#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) +#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_SSI */ +#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) +#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) +#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) +#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) +#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DMA */ +#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) +#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) +#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) +#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) +#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DEBUG */ +#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_RESET */ +#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) +#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) +#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) +#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) +#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_IRQ */ +#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) +#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) +#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) +#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) +#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_USB */ +#define GPIO_DSCR_USB_USB(x) (((x)&0x03)) +#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) +#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) +#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) +#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_ATA */ +#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) +#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) +#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) +#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) +#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) + +/********************************************************************* +* Random Number Generator (RNG) +*********************************************************************/ + +/* Bit definitions and macros for RNGCR */ +#define RNG_RNGCR_GO (0x00000001) +#define RNG_RNGCR_HA (0x00000002) +#define RNG_RNGCR_IM (0x00000004) +#define RNG_RNGCR_CI (0x00000008) + +/* Bit definitions and macros for RNGSR */ +#define RNG_RNGSR_SV (0x00000001) +#define RNG_RNGSR_LRS (0x00000002) +#define RNG_RNGSR_FUF (0x00000004) +#define RNG_RNGSR_EI (0x00000008) +#define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) +#define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +/* Bit definitions and macros for SDMR */ +#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ +#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ +#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ +#define SDRAMC_SDMR_BK_LMR (0x00000000) +#define SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for SDCR */ +#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ +#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ +#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ +#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ +#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ +#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ +#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ +#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ +#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ +#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ +#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ +#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) + +/* Bit definitions and macros for SDCFG1 */ +#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ +#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ +#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ +#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ + +/* Bit definitions and macros for SDCFG2 */ +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ +#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ +#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ +#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ + +/* Bit definitions and macros for SDCS group */ +#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ +#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ + +/* Bit definitions and macros for CR */ +#define SSI_CR_SSI_EN (0x00000001) +#define SSI_CR_TE (0x00000002) +#define SSI_CR_RE (0x00000004) +#define SSI_CR_NET (0x00000008) +#define SSI_CR_SYN (0x00000010) +#define SSI_CR_I2S(x) (((x)&0x00000003)<<5) +#define SSI_CR_MCE (0x00000080) +#define SSI_CR_TCH (0x00000100) +#define SSI_CR_CIS (0x00000200) +#define SSI_CR_I2S_NORMAL (0x00000000) +#define SSI_CR_I2S_MASTER (0x00000020) +#define SSI_CR_I2S_SLAVE (0x00000040) + +/* Bit definitions and macros for ISR */ +#define SSI_ISR_TFE0 (0x00000001) +#define SSI_ISR_TFE1 (0x00000002) +#define SSI_ISR_RFF0 (0x00000004) +#define SSI_ISR_RFF1 (0x00000008) +#define SSI_ISR_RLS (0x00000010) +#define SSI_ISR_TLS (0x00000020) +#define SSI_ISR_RFS (0x00000040) +#define SSI_ISR_TFS (0x00000080) +#define SSI_ISR_TUE0 (0x00000100) +#define SSI_ISR_TUE1 (0x00000200) +#define SSI_ISR_ROE0 (0x00000400) +#define SSI_ISR_ROE1 (0x00000800) +#define SSI_ISR_TDE0 (0x00001000) +#define SSI_ISR_TDE1 (0x00002000) +#define SSI_ISR_RDR0 (0x00004000) +#define SSI_ISR_RDR1 (0x00008000) +#define SSI_ISR_RXT (0x00010000) +#define SSI_ISR_CMDDU (0x00020000) +#define SSI_ISR_CMDAU (0x00040000) + +/* Bit definitions and macros for IER */ +#define SSI_IER_TFE0 (0x00000001) +#define SSI_IER_TFE1 (0x00000002) +#define SSI_IER_RFF0 (0x00000004) +#define SSI_IER_RFF1 (0x00000008) +#define SSI_IER_RLS (0x00000010) +#define SSI_IER_TLS (0x00000020) +#define SSI_IER_RFS (0x00000040) +#define SSI_IER_TFS (0x00000080) +#define SSI_IER_TUE0 (0x00000100) +#define SSI_IER_TUE1 (0x00000200) +#define SSI_IER_ROE0 (0x00000400) +#define SSI_IER_ROE1 (0x00000800) +#define SSI_IER_TDE0 (0x00001000) +#define SSI_IER_TDE1 (0x00002000) +#define SSI_IER_RDR0 (0x00004000) +#define SSI_IER_RDR1 (0x00008000) +#define SSI_IER_RXT (0x00010000) +#define SSI_IER_CMDU (0x00020000) +#define SSI_IER_CMDAU (0x00040000) +#define SSI_IER_TIE (0x00080000) +#define SSI_IER_TDMAE (0x00100000) +#define SSI_IER_RIE (0x00200000) +#define SSI_IER_RDMAE (0x00400000) + +/* Bit definitions and macros for TCR */ +#define SSI_TCR_TEFS (0x00000001) +#define SSI_TCR_TFSL (0x00000002) +#define SSI_TCR_TFSI (0x00000004) +#define SSI_TCR_TSCKP (0x00000008) +#define SSI_TCR_TSHFD (0x00000010) +#define SSI_TCR_TXDIR (0x00000020) +#define SSI_TCR_TFDIR (0x00000040) +#define SSI_TCR_TFEN0 (0x00000080) +#define SSI_TCR_TFEN1 (0x00000100) +#define SSI_TCR_TXBIT0 (0x00000200) + +/* Bit definitions and macros for RCR */ +#define SSI_RCR_REFS (0x00000001) +#define SSI_RCR_RFSL (0x00000002) +#define SSI_RCR_RFSI (0x00000004) +#define SSI_RCR_RSCKP (0x00000008) +#define SSI_RCR_RSHFD (0x00000010) +#define SSI_RCR_RFEN0 (0x00000080) +#define SSI_RCR_RFEN1 (0x00000100) +#define SSI_RCR_RXBIT0 (0x00000200) +#define SSI_RCR_RXEXT (0x00000400) + +/* Bit definitions and macros for CCR */ +#define SSI_CCR_PM(x) (((x)&0x000000FF)) +#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define SSI_CCR_PSR (0x00020000) +#define SSI_CCR_DIV2 (0x00040000) + +/* Bit definitions and macros for FCSR */ +#define SSI_FCSR_TFWM0(x) (((x)&0x0000000F)) +#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for ACR */ +#define SSI_ACR_AC97EN (0x00000001) +#define SSI_ACR_FV (0x00000002) +#define SSI_ACR_TIF (0x00000004) +#define SSI_ACR_RD (0x00000008) +#define SSI_ACR_WR (0x00000010) +#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) + +/* Bit definitions and macros for ACADD */ +#define SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)) + +/* Bit definitions and macros for ACDAT */ +#define SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)) + +/* Bit definitions and macros for ATAG */ +#define SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +/* Bit definitions and macros for PCR */ +#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ +#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ +#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ +#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ +#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ +#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ +#define PLL_PCR_PFDR_MASK (0x000F0000) +#define PLL_PCR_OUTDIV5_MASK (0x000F0000) +#define PLL_PCR_OUTDIV4_MASK (0x0000F000) +#define PLL_PCR_OUTDIV3_MASK (0x00000F00) +#define PLL_PCR_OUTDIV2_MASK (0x000000F0) +#define PLL_PCR_OUTDIV1_MASK (0x0000000F) + +/* Bit definitions and macros for PSR */ +#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ +#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ +#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ +#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ + +/********************************************************************* +* PCI +*********************************************************************/ + +/* Bit definitions and macros for SCR */ +#define PCI_SCR_PE (0x80000000) /* Parity Error detected */ +#define PCI_SCR_SE (0x40000000) /* System error signalled */ +#define PCI_SCR_MA (0x20000000) /* Master aboart received */ +#define PCI_SCR_TR (0x10000000) /* Target abort received */ +#define PCI_SCR_TS (0x08000000) /* Target abort signalled */ +#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ +#define PCI_SCR_DP (0x01000000) /* Master data parity err */ +#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ +#define PCI_SCR_R (0x00400000) /* Reserved */ +#define PCI_SCR_66M (0x00200000) /* 66Mhz */ +#define PCI_SCR_C (0x00100000) /* Capabilities list */ +#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ +#define PCI_SCR_S (0x00000100) /* SERR enable */ +#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ +#define PCI_SCR_PER (0x00000040) /* Parity error response */ +#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ +#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ +#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ +#define PCI_SCR_B (0x00000004) /* Bus master enable */ +#define PCI_SCR_M (0x00000002) /* Memory access control */ +#define PCI_SCR_IO (0x00000001) /* I/O access control */ + +#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ +#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ +#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ +#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ + +#define PCI_BAR_BAR0(x) (x & 0xFFFC0000) +#define PCI_BAR_BAR1(x) (x & 0xFFF00000) +#define PCI_BAR_BAR2(x) (x & 0xFFC00000) +#define PCI_BAR_BAR3(x) (x & 0xFF000000) +#define PCI_BAR_BAR4(x) (x & 0xF8000000) +#define PCI_BAR_BAR5(x) (x & 0xE0000000) +#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ +#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ +#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ + +#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ +#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ +#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ +#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ + +#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ +#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ +#define PCI_GSCR_SE (0x10000000) /* SERR detected */ +#define PCI_GSCR_ER (0x08000000) /* Error response detected */ +#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ +#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ +#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ +#define PCI_GSCR_PR (0x00000001) /* PCI reset */ + +#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ +#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ +#define PCI_TCR1_P (0x00010000) /* Prefetch reads */ +#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ + +#define PCI_TCR1_B5E (0x00002000) /* */ +#define PCI_TCR1_B4E (0x00001000) /* */ +#define PCI_TCR1_B3E (0x00000800) /* */ +#define PCI_TCR1_B2E (0x00000400) /* */ +#define PCI_TCR1_B1E (0x00000200) /* */ +#define PCI_TCR1_B0E (0x00000100) /* */ +#define PCI_TCR1_CR (0x00000001) /* */ + +#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) +#define PCI_TBATR_EN (0x00000001) /* Enable */ + +#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ +#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ +#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ +#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ +#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ +#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ +#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ +#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ +#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ + +#define PCI_ICR_REE (0x04000000) /* Retry error enable */ +#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ +#define PCI_ICR_TAE (0x01000000) /* Target abort enable */ + +#define PCI_IDR_DEVID ( + +/********************************************************************/ + +#endif /* __MCF5445X__ */ diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h deleted file mode 100644 index a73b80e..0000000 --- a/include/asm-m68k/mcftimer.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * mcftimer.h -- ColdFire internal TIMER support defines. - * - * Based on mcftimer.h of uCLinux distribution: - * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/****************************************************************************/ -#ifndef mcftimer_h -#define mcftimer_h -/****************************************************************************/ - -#include <linux/config.h> - -/* - * Get address specific defines for this ColdFire member. - */ -#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ -#elif defined(CONFIG_M5272) -#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ -#elif defined(CONFIG_M5282) | defined(CONFIG_M5271) -#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */ -#endif - -/* - * Define the TIMER register set addresses. - */ -#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ -#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ -#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ -#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ -#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ - - -/* - * Define the TIMER register set addresses for 5282. - */ -#define MCFTIMER_PCSR 0 -#define MCFTIMER_PMR 1 -#define MCFTIMER_PCNTR 2 - -/* - * Bit definitions for the Timer Mode Register (TMR). - * Register bit flags are common accross ColdFires. - */ -#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ -#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ -#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ -#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ -#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ -#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ -#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ -#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ -#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ -#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ -#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ -#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ -#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ -#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ -#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ -#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ -#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ - -/* - * Bit definitions for the Timer Event Registers (TER). - */ -#define MCFTIMER_TER_CAP 0x01 /* Capture event */ -#define MCFTIMER_TER_REF 0x02 /* Refernece event */ - -/* - * Bit definitions for the 5282 PIT Control and Status Register (PCSR). - */ -#define MCFTIMER_PCSR_EN 0x0001 -#define MCFTIMER_PCSR_RLD 0x0002 -#define MCFTIMER_PCSR_PIF 0x0004 -#define MCFTIMER_PCSR_PIE 0x0008 -#define MCFTIMER_PCSR_OVW 0x0010 -#define MCFTIMER_PCSR_HALTED 0x0020 -#define MCFTIMER_PCSR_DOZE 0x0040 - - -/****************************************************************************/ -#endif /* mcftimer_h */ diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h deleted file mode 100644 index 7c0999d..0000000 --- a/include/asm-m68k/mcfuart.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * mcfuart.h -- ColdFire internal UART support defines. - * - * File copied from mcfuart.h of uCLinux distribution: - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/****************************************************************************/ -#ifndef mcfuart_h -#define mcfuart_h -/****************************************************************************/ - -#include <linux/config.h> - -/* - * Define the base address of the UARTS within the MBAR address - * space. - */ -#if defined(CONFIG_M5272) -#define MCFUART_BASE1 0x100 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#if defined(CONFIG_NETtel) -#define MCFUART_BASE1 0x180 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x140 /* Base address of UART1 */ -#define MCFUART_BASE2 0x180 /* Base address of UART2 */ -#endif -#elif defined(CONFIG_M5282) || defined(CONFIG_M5271) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ -#endif -#endif - - -/* - * Define the ColdFire UART register set addresses. - */ -#define MCFUART_UMR 0x00 /* Mode register (r/w) */ -#define MCFUART_USR 0x04 /* Status register (r) */ -#define MCFUART_UCSR 0x04 /* Clock Select (w) */ -#define MCFUART_UCR 0x08 /* Command register (w) */ -#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ -#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ -#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ -#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ -#define MCFUART_UISR 0x14 /* Interrup Status (r) */ -#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ -#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ -#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ -#ifdef CONFIG_M5272 -#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ -#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ -#else -#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ -#endif -#define MCFUART_UIPR 0x34 /* Input Port (r) */ -#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ -#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ - -#ifdef CONFIG_M5249 -/* Note: This isn't in the 5249 docs */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ -#endif - -/* - * Define bit flags in Mode Register 1 (MR1). - */ -#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ -#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ -#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ -#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ -#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ - -#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ -#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ -#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ -#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ -#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ - -#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ -#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ -#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ -#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ - -/* - * Define bit flags in Mode Register 2 (MR2). - */ -#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ -#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ -#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ -#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ -#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ - -#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ -#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ -#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ - -/* - * Define bit flags in Status Register (USR). - */ -#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ -#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ -#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ -#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ -#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ -#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ -#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ -#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ - -#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ - MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) - -/* - * Define bit flags in Clock Select Register (UCSR). - */ -#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ -#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ -#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ - -#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ -#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ -#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ - -/* - * Define bit flags in Command Register (UCR). - */ -#define MCFUART_UCR_CMDNULL 0x00 /* No command */ -#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ -#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ -#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ -#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ -#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ -#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ -#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ - -#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ -#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ -#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ -#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ -#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ -#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ - -/* - * Define bit flags in Input Port Change Register (UIPCR). - */ -#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ -#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ - -/* - * Define bit flags in Input Port Register (UIP). - */ -#define MCFUART_UIPR_CTS 0x01 /* CTS value */ - -/* - * Define bit flags in Output Port Registers (UOP). - * Clear bit by writing to UOP0, set by writing to UOP1. - */ -#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ - -/* - * Define bit flags in the Auxiliary Control Register (UACR). - */ -#define MCFUART_UACR_IEC 0x01 /* Input enable control */ - -/* - * Define bit flags in Interrupt Status Register (UISR). - * These same bits are used for the Interrupt Mask Register (UIMR). - */ -#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ -#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ -#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ -#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ - -#ifdef CONFIG_M5272 -/* - * Define bit flags in the Transmitter FIFO Register (UTF). - */ -#define MCFUART_UTF_TXB 0x1f /* transmitter data level */ -#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */ -#define MCFUART_UTF_TXS 0xc0 /* transmitter status */ - -/* - * Define bit flags in the Receiver FIFO Register (URF). - */ -#define MCFUART_URF_RXB 0x1f /* receiver data level */ -#define MCFUART_URF_FULL 0x20 /* receiver fifo full */ -#define MCFUART_URF_RXS 0xc0 /* receiver status */ -#endif - -/****************************************************************************/ -#endif /* mcfuart_h */ diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h index 75b2418..01535be 100644 --- a/include/asm-m68k/ptrace.h +++ b/include/asm-m68k/ptrace.h @@ -28,32 +28,32 @@ #ifndef __ASSEMBLY__ struct pt_regs { - ulong d0; - ulong d1; - ulong d2; - ulong d3; - ulong d4; - ulong d5; - ulong d6; - ulong d7; - ulong a0; - ulong a1; - ulong a2; - ulong a3; - ulong a4; - ulong a5; - ulong a6; -#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271) - unsigned format : 4; /* frame format specifier */ - unsigned vector : 12; /* vector offset */ + ulong d0; + ulong d1; + ulong d2; + ulong d3; + ulong d4; + ulong d5; + ulong d6; + ulong d7; + ulong a0; + ulong a1; + ulong a2; + ulong a3; + ulong a4; + ulong a5; + ulong a6; +#if defined(__M68K__) + unsigned format:4; /* frame format specifier */ + unsigned vector:12; /* vector offset */ unsigned short sr; - unsigned long pc; + unsigned long pc; #else unsigned short sr; - unsigned long pc; + unsigned long pc; #endif }; -#endif /* #ifndef __ASSEMBLY__ */ +#endif /* #ifndef __ASSEMBLY__ */ -#endif /* #ifndef _M68K_PTRACE_H */ +#endif /* #ifndef _M68K_PTRACE_H */ diff --git a/include/asm-m68k/rtc.h b/include/asm-m68k/rtc.h new file mode 100644 index 0000000..7651ca9 --- /dev/null +++ b/include/asm-m68k/rtc.h @@ -0,0 +1,109 @@ +/* + * RealTime Clock + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCFRTC_H__ +#define __MCFRTC_H__ + +/* Real time Clock */ +typedef struct rtc_ctrl { + u32 hourmin; /* 0x00 Hours and Minutes Counter Register */ + u32 seconds; /* 0x04 Seconds Counter Register */ + u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */ + u32 alrm_sec; /* 0x0C Seconds Alarm Register */ + u32 cr; /* 0x10 Control Register */ + u32 isr; /* 0x14 Interrupt Status Register */ + u32 ier; /* 0x18 Interrupt Enable Register */ + u32 stpwatch; /* 0x1C Stopwatch Minutes Register */ + u32 days; /* 0x20 Days Counter Register */ + u32 alrm_day; /* 0x24 Days Alarm Register */ + void *extended; +} rtc_t; + +/* Bit definitions and macros for HOURMIN */ +#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)) +#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for SECONDS */ +#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for ALRM_HM */ +#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)) +#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for ALRM_SEC */ +#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for CR */ +#define RTC_CR_SWR (0x00000001) +#define RTC_CR_XTL(x) (((x)&0x00000003)<<5) +#define RTC_CR_EN (0x00000080) +#define RTC_CR_32768 (0x0) +#define RTC_CR_32000 (0x1) +#define RTC_CR_38400 (0x2) + +/* Bit definitions and macros for ISR */ +#define RTC_ISR_SW (0x00000001) +#define RTC_ISR_MIN (0x00000002) +#define RTC_ISR_ALM (0x00000004) +#define RTC_ISR_DAY (0x00000008) +#define RTC_ISR_1HZ (0x00000010) +#define RTC_ISR_HR (0x00000020) +#define RTC_ISR_2HZ (0x00000080) +#define RTC_ISR_SAM0 (0x00000100) +#define RTC_ISR_SAM1 (0x00000200) +#define RTC_ISR_SAM2 (0x00000400) +#define RTC_ISR_SAM3 (0x00000800) +#define RTC_ISR_SAM4 (0x00001000) +#define RTC_ISR_SAM5 (0x00002000) +#define RTC_ISR_SAM6 (0x00004000) +#define RTC_ISR_SAM7 (0x00008000) + +/* Bit definitions and macros for IER */ +#define RTC_IER_SW (0x00000001) +#define RTC_IER_MIN (0x00000002) +#define RTC_IER_ALM (0x00000004) +#define RTC_IER_DAY (0x00000008) +#define RTC_IER_1HZ (0x00000010) +#define RTC_IER_HR (0x00000020) +#define RTC_IER_2HZ (0x00000080) +#define RTC_IER_SAM0 (0x00000100) +#define RTC_IER_SAM1 (0x00000200) +#define RTC_IER_SAM2 (0x00000400) +#define RTC_IER_SAM3 (0x00000800) +#define RTC_IER_SAM4 (0x00001000) +#define RTC_IER_SAM5 (0x00002000) +#define RTC_IER_SAM6 (0x00004000) +#define RTC_IER_SAM7 (0x00008000) + +/* Bit definitions and macros for STPWCH */ +#define RTC_STPWCH_CNT(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for DAYS */ +#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)) + +/* Bit definitions and macros for ALRM_DAY */ +#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)) + +#endif /* __MCFRTC_H__ */ diff --git a/include/asm-m68k/timer.h b/include/asm-m68k/timer.h new file mode 100644 index 0000000..030720c --- /dev/null +++ b/include/asm-m68k/timer.h @@ -0,0 +1,118 @@ +/* + * timer.h -- ColdFire internal TIMER support defines. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/****************************************************************************/ +#ifndef timer_h +#define timer_h +/****************************************************************************/ + +/****************************************************************************/ +/* Timer structure */ +/****************************************************************************/ +/* DMA Timer module registers */ +typedef struct dtimer_ctrl { +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) + u16 tmr; /* 0x00 Mode register */ + u16 res1; /* 0x02 */ + u16 trr; /* 0x04 Reference register */ + u16 res2; /* 0x06 */ + u16 tcr; /* 0x08 Capture register */ + u16 res3; /* 0x0A */ + u16 tcn; /* 0x0C Counter register */ + u16 res4; /* 0x0E */ + u8 res6; /* 0x10 */ + u8 ter; /* 0x11 Event register */ + u16 res7; /* 0x12 */ +#else + u16 tmr; /* 0x00 Mode register */ + u8 txmr; /* 0x02 Extended Mode register */ + u8 ter; /* 0x03 Event register */ + u32 trr; /* 0x04 Reference register */ + u32 tcr; /* 0x08 Capture register */ + u32 tcn; /* 0x0C Counter register */ +#endif +} dtmr_t; + +/*Programmable Interrupt Timer */ +typedef struct pit_ctrl { + u16 pcsr; /* 0x00 Control and Status Register */ + u16 pmr; /* 0x02 Modulus Register */ + u16 pcntr; /* 0x04 Count Register */ +} pit_t; + +/********************************************************************* +* DMA Timers (DTIM) +*********************************************************************/ +/* Bit definitions and macros for DTMR */ +#define DTIM_DTMR_RST (0x0001) /* Reset */ +#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ +#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */ +#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */ +#define DTIM_DTMR_OM (0x0020) /* Output Mode */ +#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ +#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ +#define DTIM_DTMR_RST_EN (0x0001) +#define DTIM_DTMR_RST_RST (0x0000) +#define DTIM_DTMR_CE_ANY (0x00C0) +#define DTIM_DTMR_CE_FALL (0x0080) +#define DTIM_DTMR_CE_RISE (0x0040) +#define DTIM_DTMR_CE_NONE (0x0000) +#define DTIM_DTMR_CLK_DTIN (0x0006) +#define DTIM_DTMR_CLK_DIV16 (0x0004) +#define DTIM_DTMR_CLK_DIV1 (0x0002) +#define DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for DTXMR */ +#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ +#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */ + +/* Bit definitions and macros for DTER */ +#define DTIM_DTER_CAP (0x01) /* Capture event */ +#define DTIM_DTER_REF (0x02) /* Output reference event */ + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Bit definitions and macros for PCSR */ +#define PIT_PCSR_EN (0x0001) +#define PIT_PCSR_RLD (0x0002) +#define PIT_PCSR_PIF (0x0004) +#define PIT_PCSR_PIE (0x0008) +#define PIT_PCSR_OVW (0x0010) +#define PIT_PCSR_HALTED (0x0020) +#define PIT_PCSR_DOZE (0x0040) +#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for PMR */ +#define PIT_PMR_PM(x) (x) + +/* Bit definitions and macros for PCNTR */ +#define PIT_PCNTR_PC(x) (x) + +/****************************************************************************/ +#endif /* timer_h */ diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h index 7a6a8c1..93a6959 100644 --- a/include/asm-m68k/u-boot.h +++ b/include/asm-m68k/u-boot.h @@ -37,24 +37,44 @@ #ifndef __ASSEMBLY__ typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* Ethernet adress */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#ifdef CONFIG_PCI + unsigned long bi_pcifreq; /* pci Freq in MHz */ +#endif +#ifdef CONFIG_EXTRA_CLOCK + unsigned long bi_inpfreq; /* input Freq in MHz */ + unsigned long bi_vcofreq; /* vco Freq in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ +#endif + unsigned long bi_baudrate; /* Console Baudrate */ + +#ifdef CONFIG_HAS_ETH1 + /* second onboard ethernet port */ + unsigned char bi_enet1addr[6]; +#endif +#ifdef CONFIG_HAS_ETH2 + /* third onboard ethernet port */ + unsigned char bi_enet2addr[6]; +#endif +#ifdef CONFIG_HAS_ETH3 + unsigned char bi_enet3addr[6]; +#endif } bd_t; -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ */ -#endif /* __U_BOOT_H__ */ +#endif /* __U_BOOT_H__ */ diff --git a/include/asm-m68k/uart.h b/include/asm-m68k/uart.h new file mode 100644 index 0000000..9a528ea --- /dev/null +++ b/include/asm-m68k/uart.h @@ -0,0 +1,171 @@ +/* + * uart.h -- ColdFire internal UART support defines. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/****************************************************************************/ +#ifndef uart_h +#define uart_h +/****************************************************************************/ + +/* UART module registers */ +/* Register read/write struct */ +typedef struct uart { + u8 umr; /* 0x00 Mode Register */ + u8 resv0[0x3]; + union { + u8 usr; /* 0x04 Status Register */ + u8 ucsr; /* 0x04 Clock Select Register */ + }; + u8 resv1[0x3]; + u8 ucr; /* 0x08 Command Register */ + u8 resv2[0x3]; + union { + u8 utb; /* 0x0c Transmit Buffer */ + u8 urb; /* 0x0c Receive Buffer */ + }; + u8 resv3[0x3]; + union { + u8 uipcr; /* 0x10 Input Port Change Register */ + u8 uacr; /* 0x10 Auxiliary Control reg */ + }; + u8 resv4[0x3]; + union { + u8 uimr; /* 0x14 Interrupt Mask reg */ + u8 uisr; /* 0x14 Interrupt Status reg */ + }; + u8 resv5[0x3]; + u8 ubg1; /* 0x18 Counter Timer Upper Register */ + u8 resv6[0x3]; + u8 ubg2; /* 0x1c Counter Timer Lower Register */ + u8 resv7[0x17]; + u8 uip; /* 0x34 Input Port Register */ + u8 resv8[0x3]; + u8 uop1; /* 0x38 Output Port Set Register */ + u8 resv9[0x3]; + u8 uop0; /* 0x3c Output Port Reset Register */ +} uart_t; + +/********************************************************************* +* Universal Asynchronous Receiver Transmitter (UART) +*********************************************************************/ +/* Bit definitions and macros for UMR */ +#define UART_UMR_BC(x) (((x)&0x03)) +#define UART_UMR_PT (0x04) +#define UART_UMR_PM(x) (((x)&0x03)<<3) +#define UART_UMR_ERR (0x20) +#define UART_UMR_RXIRQ (0x40) +#define UART_UMR_RXRTS (0x80) +#define UART_UMR_SB(x) (((x)&0x0F)) +#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */ +#define UART_UMR_TXRTS (0x20) /* Transmit RTS */ +#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */ +#define UART_UMR_PM_MULTI_ADDR (0x1C) +#define UART_UMR_PM_MULTI_DATA (0x18) +#define UART_UMR_PM_NONE (0x10) +#define UART_UMR_PM_FORCE_HI (0x0C) +#define UART_UMR_PM_FORCE_LO (0x08) +#define UART_UMR_PM_ODD (0x04) +#define UART_UMR_PM_EVEN (0x00) +#define UART_UMR_BC_5 (0x00) +#define UART_UMR_BC_6 (0x01) +#define UART_UMR_BC_7 (0x02) +#define UART_UMR_BC_8 (0x03) +#define UART_UMR_CM_NORMAL (0x00) +#define UART_UMR_CM_ECH (0x40) +#define UART_UMR_CM_LOCAL_LOOP (0x80) +#define UART_UMR_CM_REMOTE_LOOP (0xC0) +#define UART_UMR_SB_STOP_BITS_1 (0x07) +#define UART_UMR_SB_STOP_BITS_15 (0x08) +#define UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for USR */ +#define UART_USR_RXRDY (0x01) +#define UART_USR_FFULL (0x02) +#define UART_USR_TXRDY (0x04) +#define UART_USR_TXEMP (0x08) +#define UART_USR_OE (0x10) +#define UART_USR_PE (0x20) +#define UART_USR_FE (0x40) +#define UART_USR_RB (0x80) + +/* Bit definitions and macros for UCSR */ +#define UART_UCSR_TCS(x) (((x)&0x0F)) +#define UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define UART_UCSR_RCS_SYS_CLK (0xD0) +#define UART_UCSR_RCS_CTM16 (0xE0) +#define UART_UCSR_RCS_CTM (0xF0) +#define UART_UCSR_TCS_SYS_CLK (0x0D) +#define UART_UCSR_TCS_CTM16 (0x0E) +#define UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for UCR */ +#define UART_UCR_RXC(x) (((x)&0x03)) +#define UART_UCR_TXC(x) (((x)&0x03)<<2) +#define UART_UCR_MISC(x) (((x)&0x07)<<4) +#define UART_UCR_NONE (0x00) +#define UART_UCR_STOP_BREAK (0x70) +#define UART_UCR_START_BREAK (0x60) +#define UART_UCR_BKCHGINT (0x50) +#define UART_UCR_RESET_ERROR (0x40) +#define UART_UCR_RESET_TX (0x30) +#define UART_UCR_RESET_RX (0x20) +#define UART_UCR_RESET_MR (0x10) +#define UART_UCR_TX_DISABLED (0x08) +#define UART_UCR_TX_ENABLED (0x04) +#define UART_UCR_RX_DISABLED (0x02) +#define UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for UIPCR */ +#define UART_UIPCR_CTS (0x01) +#define UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for UACR */ +#define UART_UACR_IEC (0x01) + +/* Bit definitions and macros for UIMR */ +#define UART_UIMR_TXRDY (0x01) +#define UART_UIMR_RXRDY_FU (0x02) +#define UART_UIMR_DB (0x04) +#define UART_UIMR_COS (0x80) + +/* Bit definitions and macros for UISR */ +#define UART_UISR_TXRDY (0x01) +#define UART_UISR_RXRDY_FU (0x02) +#define UART_UISR_DB (0x04) +#define UART_UISR_RXFTO (0x08) +#define UART_UISR_TXFIFO (0x10) +#define UART_UISR_RXFIFO (0x20) +#define UART_UISR_COS (0x80) + +/* Bit definitions and macros for UIP */ +#define UART_UIP_CTS (0x01) + +/* Bit definitions and macros for UOP1 */ +#define UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for UOP0 */ +#define UART_UOP0_RTS (0x01) + +/****************************************************************************/ +#endif /* mcfuart_h */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 463a111..c42ad82 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -1,126 +1,31 @@ -/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle + * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle + * Copyright (c) 2000 by Silicon Graphics, Inc. + * Copyright (c) 2001 MIPS Technologies, Inc. */ -#ifndef __ASM_MIPS_STRING_H -#define __ASM_MIPS_STRING_H - -#include <linux/config.h> - -#define __HAVE_ARCH_STRCPY -extern __inline__ char *strcpy(char *__dest, __const__ char *__src) -{ - char *__xdest = __dest; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,(%1)\n\t" - "addiu\t%1,1\n\t" - "sb\t$1,(%0)\n\t" - "bnez\t$1,1b\n\t" - "addiu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__dest), "=r" (__src) - : "0" (__dest), "1" (__src) - : "$1","memory"); - - return __xdest; -} - -#define __HAVE_ARCH_STRNCPY -extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) -{ - char *__xdest = __dest; - - if (__n == 0) - return __xdest; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,(%1)\n\t" - "subu\t%2,1\n\t" - "sb\t$1,(%0)\n\t" - "beqz\t$1,2f\n\t" - "addiu\t%0,1\n\t" - "bnez\t%2,1b\n\t" - "addiu\t%1,1\n" - "2:\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__dest), "=r" (__src), "=r" (__n) - : "0" (__dest), "1" (__src), "2" (__n) - : "$1","memory"); +#ifndef _ASM_STRING_H +#define _ASM_STRING_H - return __dest; -} - -#define __HAVE_ARCH_STRCMP -extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) -{ - int __res; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "lbu\t%2,(%0)\n" - "1:\tlbu\t$1,(%1)\n\t" - "addiu\t%0,1\n\t" - "bne\t$1,%2,2f\n\t" - "addiu\t%1,1\n\t" - "bnez\t%2,1b\n\t" - "lbu\t%2,(%0)\n\t" -#if defined(CONFIG_CPU_R3000) - "nop\n\t" -#endif - "move\t%2,$1\n" - "2:\tsubu\t%2,$1\n" - "3:\t.set\tat\n\t" - ".set\treorder" - : "=r" (__cs), "=r" (__ct), "=r" (__res) - : "0" (__cs), "1" (__ct) - : "$1"); +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ - return __res; -} +#undef __HAVE_ARCH_STRCPY +extern char *strcpy(char *__dest, __const__ char *__src); -#define __HAVE_ARCH_STRNCMP -extern __inline__ int -strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) -{ - int __res; +#undef __HAVE_ARCH_STRNCPY +extern char *strncpy(char *__dest, __const__ char *__src, size_t __n); - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t%3,(%0)\n\t" - "beqz\t%2,2f\n\t" - "lbu\t$1,(%1)\n\t" - "subu\t%2,1\n\t" - "bne\t$1,%3,3f\n\t" - "addiu\t%0,1\n\t" - "bnez\t%3,1b\n\t" - "addiu\t%1,1\n" - "2:\n\t" -#if defined(CONFIG_CPU_R3000) - "nop\n\t" -#endif - "move\t%3,$1\n" - "3:\tsubu\t%3,$1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) - : "0" (__cs), "1" (__ct), "2" (__count) - : "$1"); +#undef __HAVE_ARCH_STRCMP +extern int strcmp(__const__ char *__cs, __const__ char *__ct); - return __res; -} +#undef __HAVE_ARCH_STRNCMP +extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count); #undef __HAVE_ARCH_MEMSET extern void *memset(void *__s, int __c, size_t __count); @@ -131,27 +36,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n); #undef __HAVE_ARCH_MEMMOVE extern void *memmove(void *__dest, __const__ void *__src, size_t __n); -/* Don't build bcopy at all ... */ -#define __HAVE_ARCH_BCOPY - -#define __HAVE_ARCH_MEMSCAN -extern __inline__ void *memscan(void *__addr, int __c, size_t __size) -{ - char *__end = (char *)__addr + __size; - - __asm__(".set\tpush\n\t" - ".set\tnoat\n\t" - ".set\treorder\n\t" - "1:\tbeq\t%0,%1,2f\n\t" - "addiu\t%0,1\n\t" - "lb\t$1,-1(%0)\n\t" - "bne\t$1,%4,1b\n" - "2:\t.set\tpop" - : "=r" (__addr), "=r" (__end) - : "0" (__addr), "1" (__end), "r" (__c) - : "$1"); - - return __addr; -} - -#endif /* __ASM_MIPS_STRING_H */ +#endif /* _ASM_STRING_H */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 1f1583a..4676e2c 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -133,7 +133,7 @@ typedef struct global_data { unsigned long do_mdm_init; unsigned long be_quiet; #endif -#ifdef CONFIG_LWMON +#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5) unsigned long kbd_status; #endif void **jt; /* jump table */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 3d4816f..496fc72 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1596,7 +1596,7 @@ typedef struct ccsr_gur { uint svr; /* 0xe00a4 - System version register */ char res10a[8]; uint rstcr; /* 0xe00b0 - Reset control register */ -#ifdef MPC8568 +#ifdef CONFIG_MPC8568 char res10b[76]; par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ char res10c[3136]; diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 03289bc..11dfa1c 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -13,6 +13,9 @@ #define SIO_CONFIG_RA 0x398 #define SIO_CONFIG_RD 0x399 +#ifndef _IO_BASE +#define _IO_BASE 0 +#endif #define readb(addr) in_8((volatile u8 *)(addr)) #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) diff --git a/include/common.h b/include/common.h index 27a660a..aca281b 100644 --- a/include/common.h +++ b/include/common.h @@ -275,7 +275,7 @@ void pciinfo (int, int); # endif int is_pci_host (struct pci_controller *); #if defined(CONFIG_440SPE) - void pcie_setup_hoses(void); + void pcie_setup_hoses(int busno); #endif #endif @@ -434,6 +434,13 @@ int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); void reset_cpu (ulong addr); +#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) +void ft_cpu_setup(void *blob, bd_t *bd); +#ifdef CONFIG_PCI +void ft_pci_setup(void *blob, bd_t *bd); +#endif +#endif + /* $(CPU)/serial.c */ int serial_init (void); diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 9e0ee37..0718c85 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -53,9 +53,13 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -144,39 +148,16 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 08ef9b5..1fd2b53 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -90,8 +90,6 @@ #define CONFIG_CMD_EEPROM -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -157,34 +155,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 0a4e1e9..1b948f6 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -92,8 +92,6 @@ #define CONFIG_SUPPORT_VFAT -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index ceeba6e..fb71c5f 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -114,8 +114,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #endif -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 1aefbba..4994319 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -100,9 +100,6 @@ #define CONFIG_SUPPORT_VFAT -#define CFG_NAND_LEGACY - - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index e2652e6..29f9292 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -111,8 +111,6 @@ #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index a8697ec..dae5295 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -40,9 +40,8 @@ #define CONFIG_MISC_INIT_R -#define FEC_ENET -#define CONFIG_ETHADDR 00:CF:52:82:EB:01 - +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -84,7 +83,39 @@ #include <config_cmd_default.h> #undef CONFIG_CMD_LOADB +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:CF:52:82:EB:01 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ #define CONFIG_BOOTDELAY 5 #define CFG_PROMPT "\nEV123 U-Boot> " @@ -122,9 +153,6 @@ */ #define CFG_MBAR 0x40000000 -#define CFG_DISCOVER_PHY -/* #define CFG_ENET_BD_BASE 0x380000 */ - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ @@ -151,6 +179,7 @@ #define CFG_FLASH_BASE 0xFFE00000 #define CFG_INT_FLASH_BASE 0xF0000000 +#define CFG_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 00f481c..ea8e61a 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -141,8 +141,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ -#define CFG_NAND_LEGACY - #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -209,34 +207,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 661b895..ed669c5 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -147,36 +147,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 53261548..4c16d22 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -178,12 +178,9 @@ #endif /* CONFIG_MPC5200 */ /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h new file mode 100644 index 0000000..7f544c8 --- /dev/null +++ b/include/configs/M5235EVB.h @@ -0,0 +1,261 @@ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5235EVB_H +#define _M5235EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF523x /* define processor family */ +#define CONFIG_M5235 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x00000300 +#define CFG_IMMR CFG_MBAR + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTFILE "u-boot.bin" +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5235EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000) + +#define CFG_HZ 1000 +#define CFG_CLK 75000000 +#define CFG_CPU_CLK CFG_CLK * 2 + +#define CFG_MBAR 0x40000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x21 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +#ifdef NORFLASH_PS32BIT +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT +#else +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#endif +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#define CFG_FLASH_BASE (CFG_CS0_BASE << 16) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 +#ifdef NORFLASH_PS32BIT +# define CFG_ENV_OFFSET (0x8000) +# define CFG_ENV_SIZE 0x4000 +# define CFG_ENV_SECT_SIZE 0x4000 +#else +# define CFG_ENV_OFFSET (0x4000) +# define CFG_ENV_SIZE 0x2000 +# define CFG_ENV_SECT_SIZE 0x2000 +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + * CS6 - Available + * CS7 - Available + */ +#ifdef NORFLASH_PS32BIT +# define CFG_CS0_BASE 0xFFC0 +# define CFG_CS0_MASK 0x003f0001 +# define CFG_CS0_CTRL 0x1D00 +#else +# define CFG_CS0_BASE 0xFFE0 +# define CFG_CS0_MASK 0x001f0001 +# define CFG_CS0_CTRL 0x1D80 +#endif + +#endif /* _M5329EVB_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h new file mode 100644 index 0000000..de7ea42 --- /dev/null +++ b/include/configs/M5249EVB.h @@ -0,0 +1,194 @@ +/* + * Configuation settings for the esd TASREG board. + * + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5249EVB_H +#define _M5249EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5249 /* define processor type */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_BOOTPATH +#undef CONFIG_BOOTP_GATEWAY +#undef CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 + +/* + * Clock configuration: enable only one of the following options + */ + +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_MBAR2 0x80000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_FLASH_BASE (CFG_CSAR0 << 16) + +#if 0 /* test-only */ +#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ +#endif + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ +#define CFG_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + +/* CS0 - AMD Flash, address 0xffc00000 */ +#define CFG_CSAR0 0xffe0 +#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ +/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ +#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ + +/* CS1 - FPGA, address 0xe0000000 */ +#define CFG_CSAR1 0xe000 +#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ +#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_GPIO1_LED 0x00400000 /* user led */ + +#endif /* M5249 */ diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h new file mode 100644 index 0000000..48170e7 --- /dev/null +++ b/include/configs/M5253EVBE.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _M5253EVBE_H +#define _M5253EVBE_H + +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5253 /* define processor type */ +#define CONFIG_M5253EVBE /* define board type */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG /* disable watchdog */ + +#define CONFIG_BOOTDELAY 5 + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#else +#define CFG_ENV_ADDR 0xffe04000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#endif + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_BOOTPATH +#undef CONFIG_BOOTP_GATEWAY +#undef CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC + +/* ATA */ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_ATAPI +#undef CONFIG_LBA48 + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800) +#define CFG_ATA_IDE0_OFFSET 0 + +#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ +#define _IO_BASE 0 + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 + +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_FAST_CLK +#ifdef CFG_FAST_CLK +# define CFG_PLLCR 0x1243E054 +# define CFG_CLK 140000000 +#else +# define CFG_PLLCR 0x135a4140 +# define CFG_CLK 70000000 +#endif + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */ + +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CFG_MONITOR_BASE 0x20000 +#else +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif + +#define CFG_MONITOR_LEN 0x40000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN (64*1024) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CFG_FLASH_BASE 0xffe00000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_SIZE 0x200000 +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 16 + +/* Port configuration */ +#define CFG_FECI2C 0xF0 + +#define CFG_CSAR0 0xFFE0 +#define CFG_CSMR0 0x001F0021 +#define CFG_CSCR0 0x1D80 + +#define CFG_CSAR1 0 +#define CFG_CSMR1 0 +#define CFG_CSCR1 0 + +#define CFG_CSAR2 0 +#define CFG_CSMR2 0 +#define CFG_CSCR2 0 + +#define CFG_CSAR3 0 +#define CFG_CSMR3 0 +#define CFG_CSCR3 0 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_GPIO1_LED 0x00400000 /* user led */ + +#endif /* _M5253EVB_H */ diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 885a882..0f97050 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -31,7 +31,6 @@ #ifndef _M5271EVB_H #define _M5271EVB_H -#define DEBUG #undef DEBUG /* @@ -41,17 +40,15 @@ #define CONFIG_M5271 /* define processor type */ #define CONFIG_M5271EVB /* define board type */ -#define CONFIG_IPADDR 192.168.30.1 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_ETHADDR 00:06:3b:01:41:55 +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG /* disable watchdog */ -#define CONFIG_BOOTDELAY 5 - /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ @@ -73,7 +70,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -81,22 +77,83 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x00000300 +#define CFG_IMMR CFG_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTFILE "u-boot.bin" +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_RETRY_COUNT 5 +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5235EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe2ffff;" \ + "era ffe00000 ffe2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" #define CFG_PROMPT "=> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 @@ -114,16 +171,11 @@ #define CFG_MBAR 0x40000000 /* Register Base Addrs */ -/* Enable FEC ethernet */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 -#define CFG_ENET_BD_BASE 0x480000 - /* * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -134,7 +186,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #ifdef CONFIG_MONITOR_IS_IN_RAM @@ -152,11 +204,11 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 1000 #define CFG_FLASH_CFI 1 @@ -169,4 +221,4 @@ /* Port configuration */ #define CFG_FECI2C 0xF0 -#endif /* _M5271EVB_H */ +#endif /* _M5271EVB_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index cc456dc..2b8734b 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -33,18 +33,20 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5272 /* define processor type */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5272 /* define processor type */ -#define FEC_ENET +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } -#define CONFIG_WATCHDOG +#undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -60,7 +62,6 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif - /* * BOOTP options */ @@ -69,37 +70,82 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ #include <config_cmd_default.h> #define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_MISC +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB - #define CONFIG_BOOTDELAY 5 +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME M5272C3 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" #define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x20000 - #define CFG_MEMTEST_START 0x400 #define CFG_MEMTEST_END 0x380000 - #define CFG_HZ 1000 #define CFG_CLK 66000000 @@ -108,20 +154,15 @@ * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ - #define CFG_MBAR 0x10000000 /* Register Base Addrs */ - #define CFG_SCR 0x0003; #define CFG_SPR 0xffff; -#define CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x380000 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -132,7 +173,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #ifdef CONFIG_MONITOR_IS_IN_RAM @@ -150,13 +191,13 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 1000 /*----------------------------------------------------------------------- @@ -169,25 +210,18 @@ */ #define CFG_BR0_PRELIM 0xFFE00201 #define CFG_OR0_PRELIM 0xFFE00014 - #define CFG_BR1_PRELIM 0 #define CFG_OR1_PRELIM 0 - #define CFG_BR2_PRELIM 0x30000001 #define CFG_OR2_PRELIM 0xFFF80000 - #define CFG_BR3_PRELIM 0 #define CFG_OR3_PRELIM 0 - #define CFG_BR4_PRELIM 0 #define CFG_OR4_PRELIM 0 - #define CFG_BR5_PRELIM 0 #define CFG_OR5_PRELIM 0 - #define CFG_BR6_PRELIM 0 #define CFG_OR6_PRELIM 0 - #define CFG_BR7_PRELIM 0x00000701 #define CFG_OR7_PRELIM 0xFFC0007C @@ -197,9 +231,8 @@ #define CFG_PACNT 0x00000000 #define CFG_PADDR 0x0000 #define CFG_PADAT 0x0000 -#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ #define CFG_PBDDR 0x0000 #define CFG_PBDAT 0x0000 #define CFG_PDCNT 0x00000000 - -#endif /* _M5272C3_H */ +#endif /* _M5272C3_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index f2a7644..3c17c1e 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -33,15 +33,17 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5282 /* define processor type */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5282 /* define processor type */ -#define FEC_ENET +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } -#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -50,7 +52,6 @@ #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_IS_IN_FLASH 1 - /* * BOOTP options */ @@ -59,29 +60,73 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ #include <config_cmd_default.h> +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif #define CONFIG_BOOTDELAY 5 +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME M5272C3 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" #define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x20000 @@ -91,6 +136,10 @@ #define CFG_HZ 1000000 #define CFG_CLK 64000000 +/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ + +#define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* * Low Level Configuration Settings @@ -99,15 +148,12 @@ */ #define CFG_MBAR 0x40000000 -#undef CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x380000 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -117,49 +163,88 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #define CFG_INT_FLASH_BASE 0xf0000000 +#define CFG_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ -/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */ -#define CFG_MONITOR_BASE 0x20000 +#if (TEXT_BASE != CFG_INT_FLASH_BASE) +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#else +#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ +#endif #define CFG_MONITOR_LEN 0x20000 #define CFG_MALLOC_LEN (256 << 10) #define CFG_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_SECT 35 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_FLASH_ERASE_TOUT 10000000 +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 - /*----------------------------------------------------------------------- * Memory bank definitions */ - - +#define CFG_CS0_BASE CFG_FLASH_BASE +#define CFG_CS0_SIZE 2*1024*1024 +#define CFG_CS0_WIDTH 16 +#define CFG_CS0_RO 0 +#define CFG_CS0_WS 6 +/* +#define CFG_CS3_BASE 0xE0000000 +#define CFG_CS3_SIZE 1*1024*1024 +#define CFG_CS3_WIDTH 16 +#define CFG_CS3_RO 0 +#define CFG_CS3_WS 6 +*/ /*----------------------------------------------------------------------- * Port configuration */ +#define CFG_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_PADDR 0x0000000 +#define CFG_PADAT 0x0000000 + +#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_PBDDR 0x0000000 +#define CFG_PBDAT 0x0000000 + +#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */ +#define CFG_PCDDR 0x0000000 +#define CFG_PCDAT 0x0000000 + +#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_PCDDR 0x0000000 +#define CFG_PCDAT 0x0000000 +#define CFG_PEHLPAR 0xC0 +#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CFG_DDRUA 0x05 +#define CFG_PJPAR 0xFF; -#endif /* _CONFIG_M5282EVB_H */ +#endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h new file mode 100644 index 0000000..d3b1605 --- /dev/null +++ b/include/configs/M5329EVB.h @@ -0,0 +1,267 @@ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5329EVB_H +#define _M5329EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5329 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#ifdef NANDFLASH_SIZE +# define CONFIG_CMD_NAND +#endif + +#define CFG_UNIFY_CACHE + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5329EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#ifdef CONFIG_CMD_KGDB +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x40010000 + +#define CFG_HZ 1000 +#define CFG_CLK 80000000 +#define CFG_CPU_CLK CFG_CLK * 3 + +#define CFG_MBAR 0xFC000000 + +#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x53722730 +#define CFG_SDRAM_CFG2 0x56670000 +#define CFG_SDRAM_CTRL 0xE1092000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x018D0000 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#ifdef NANDFLASH_SIZE +# define CFG_MAX_NAND_DEVICE 1 +# define CFG_NAND_BASE (CFG_CS2_BASE << 16) +# define CFG_NAND_SIZE 1 +# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +# define NAND_MAX_CHIPS 1 +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#endif + +#define CFG_FLASH_BASE (CFG_CS0_BASE << 16) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - NAND Flash 16, 32, or 64MB + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x007f0001 +#define CFG_CS0_CTRL 0x00001fa0 + +#define CFG_CS1_BASE 0x1000 +#define CFG_CS1_MASK 0x001f0001 +#define CFG_CS1_CTRL 0x002A3780 + +#ifdef NANDFLASH_SIZE +#define CFG_CS2_BASE 0x2000 +#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) +#define CFG_CS2_CTRL 0x00001f60 +#endif + +#endif /* _M5329EVB_H */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h new file mode 100644 index 0000000..6f4859c --- /dev/null +++ b/include/configs/M54455EVB.h @@ -0,0 +1,391 @@ +/* + * Configuation settings for the Freescale MCF54455 EVB board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _JAMICA54455_H +#define _JAMICA54455_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5445x /* define processor family */ +#define CONFIG_M54455 /* define processor type */ +#define CONFIG_M54455EVB /* M54455EVB board */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_CF_DOMII +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC1_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +# define CONFIG_HAS_ETH1 + +# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME M54455EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +/* ATA configuration */ +#define CONFIG_ISO_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_ATAPI +#undef CONFIG_LBA48 + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_BASE_ADDR 0x90000000 +#define CFG_ATA_IDE0_OFFSET 0 + +#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ +#define _IO_BASE 0 + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CFG_RTC_OSCILLATOR (32 * CFG_HZ) + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2c */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +/* PCI */ +#define CONFIG_PCI 1 + +#define CFG_PCI_MEM_BUS 0xA0000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS +#define CFG_PCI_MEM_SIZE 0x10000000 + +#define CFG_PCI_IO_BUS 0xB1000000 +#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS +#define CFG_PCI_IO_SIZE 0x01000000 + +#define CFG_PCI_CFG_BUS 0xB0000000 +#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS +#define CFG_PCI_CFG_SIZE 0x01000000 + +/* FPGA - Spartan 2 */ +/* experiment +#define CONFIG_FPGA CFG_SPARTAN3 +#define CONFIG_FPGA_COUNT 1 +#define CFG_FPGA_PROG_FEEDBACK +#define CFG_FPGA_CHECK_CTRLC +*/ + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) + +#define CFG_HZ 1000 + +#define CFG_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_BASE1 0x48000000 +#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x65311610 +#define CFG_SDRAM_CFG2 0x59670000 +#define CFG_SDRAM_CTRL 0xEA0B2000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x00010033 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 +#undef CFG_ENV_IS_EMBEDDED + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CFG_ATMEL_BOOT +# define CFG_FLASH_BASE 0 +# define CFG_FLASH0_BASE CFG_CS0_BASE +# define CFG_FLASH1_BASE CFG_CS1_BASE +#else +# define CFG_FLASH_BASE CFG_FLASH0_BASE +# define CFG_FLASH0_BASE CFG_CS1_BASE +# define CFG_FLASH1_BASE CFG_CS0_BASE +#endif + +/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system +/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system + keep reset. */ +#undef CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } + +#else + +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ + +# define CFG_ATMEL_REGION 4 +# define CFG_ATMEL_TOTALSECT 11 +# define CFG_ATMEL_SECT {1, 2, 1, 7} +# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} +# define CFG_INTEL_SECT 137 + +/* max number of sectors on one chip */ +# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT) +# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */ +# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM + +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CFG_ATMEL_BOOT +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE +#else +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - CPLD + * CS3 - FPGA + * CS4 - Available + * CS5 - Available + */ + +#ifdef CFG_ATMEL_BOOT + /* Atmel Flash */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x00070001 +#define CFG_CS0_CTRL 0x00001140 +/* Intel Flash */ +#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_MASK 0x01FF0001 +#define CFG_CS1_CTRL 0x003F3D60 + +#define CFG_ATMEL_BASE CFG_CS0_BASE +#else +/* Intel Flash */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x01FF0001 +#define CFG_CS0_CTRL 0x003F3D60 + /* Atmel Flash */ +#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_MASK 0x00070001 +#define CFG_CS1_CTRL 0x00001140 + +#define CFG_ATMEL_BASE CFG_CS1_BASE +#endif + +/* CPLD */ +#define CFG_CS2_BASE 0x08000000 +#define CFG_CS2_MASK 0x00070001 +#define CFG_CS2_CTRL 0x003f1140 + +/* FPGA */ +#define CFG_CS3_BASE 0x09000000 +#define CFG_CS3_MASK 0x00070001 +#define CFG_CS3_CTRL 0x00000020 + +#endif /* _JAMICA54455_H */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 81db96f..6568fe1 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -113,12 +113,12 @@ /* 0x03200064 */ #if defined(CONFIG_DDR_2T_TIMING) #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_2T_EN \ | SDRAM_CFG_DBW_32 ) #else #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_32_BE ) /* 0x43080000 */ #endif @@ -228,12 +228,9 @@ #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8313@0" #define OF_SOC "soc8313@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -310,6 +307,8 @@ #define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0x1c #define TSEC2_PHY_ADDR 4 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 @@ -507,6 +506,7 @@ #define CONFIG_ETHADDR 00:E0:0C:00:95:01 #define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 #define CONFIG_IPADDR 10.0.0.2 diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f62ca2c..c9c6d88 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -30,6 +30,8 @@ #define CONFIG_MPC83XX 1 /* MPC83xx family */ #define CONFIG_MPC832X 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ +#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ +#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ /* * System Clock Setup @@ -87,6 +89,7 @@ #define CFG_SICRL 0x00000000 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* * IMMR new address @@ -315,12 +318,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8323@0" #define OF_SOC "soc8323@e0000000" #define OF_QE "qe@e0100000" diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1567fcf..92555ba 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -339,12 +339,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -440,6 +437,8 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -699,6 +698,7 @@ #if defined(CONFIG_TSEC_ENET) #define CONFIG_ETHADDR 00:04:9f:ef:23:33 #define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 #endif diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 44649d0..54cab52 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -296,12 +296,9 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -378,10 +375,12 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_TSEC1 #ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" #define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT #endif #ifdef CONFIG_TSEC2 @@ -391,6 +390,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define TSEC2_PHY_ADDR 4 #define TSEC2_PHYIDX 0 +#define TSEC2_FLAGS TSEC_GIGABIT #endif #define CONFIG_ETHPRIME "Freescale TSEC" diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 4b32a14..41f062c 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -32,6 +32,8 @@ #define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ +#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ +#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ /* * System Clock Setup @@ -88,6 +90,7 @@ #define CFG_SICRL 0x40000000 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* * IMMR new address @@ -309,13 +312,13 @@ /* * CS4 on Local Bus, to PIB */ -#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ +#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */ #define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* * CS5 on Local Bus, to PIB */ -#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ +#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */ #define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* @@ -348,10 +351,6 @@ #define CONFIG_OF_HAS_BD_T 1 #define CONFIG_OF_HAS_UBOOT_ENV 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8360@0" #define OF_SOC "soc8360@e0000000" #define OF_QE "qe@e0100000" diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5a7c879..be603ac 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -301,9 +301,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8540@0" #define OF_SOC "soc8540@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -374,6 +371,8 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #if CONFIG_HAS_FEC @@ -381,6 +380,7 @@ #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 #endif /* Options are: TSEC[0-1], FEC */ @@ -489,6 +489,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 0ce25cf..e376c11 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -213,10 +213,13 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 +#define CONFIG_HAS_ETH1 #define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_MPC85XX_FEC 1 +#define CONFIG_HAS_ETH2 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define TSEC1_PHY_ADDR 7 #define TSEC2_PHY_ADDR 4 @@ -224,6 +227,10 @@ #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define FEC_FLAGS 0 + /* Options are: TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 232f171..4e061bd 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -384,13 +381,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -482,6 +478,7 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 32934e1..f580cca 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -181,6 +181,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -252,9 +253,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8544@0" #define OF_SOC "soc8544@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -282,7 +280,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe1000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */ /* PCI view of System Memory */ #define CFG_PCI_MEMORY_BUS 0x00000000 @@ -294,27 +292,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCIE2_IO_BASE 0x00000000 -#define CFG_PCIE2_IO_PHYS 0xe2000000 -#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE2_IO_PHYS 0xe1010000 +#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2,tgtid 2, Base address a000 */ #define CFG_PCIE1_MEM_BASE 0xa0000000 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE -#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */ -#define CFG_PCIE1_MEM_BASE2 0xa8000000 -#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2 -#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */ -#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */ -#define CFG_PCIE1_IO_PHYS 0xaf000000 -#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe1020000 +#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address b000 */ #define CFG_PCIE3_MEM_BASE 0xb0000000 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE -#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ #define CFG_PCIE3_IO_BASE 0x00000000 -#define CFG_PCIE3_IO_PHYS 0xe3000000 +#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE3_MEM_BASE2 0xb0200000 +#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2 +#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ #if defined(CONFIG_PCI) @@ -364,15 +362,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_TSEC1_NAME "eTSEC1" #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define CONFIG_TSEC_TBI 1 /* enable internal TBI phy */ -#define CONFIG_SGMII_RISER -#define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c /* sgmii phy base */ #define TSEC1_PHY_ADDR 0 #define TSEC3_PHY_ADDR 1 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + #define TSEC1_PHYIDX 0 #define TSEC3_PHYIDX 0 @@ -474,6 +470,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index cda9fd5..6083715 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -336,9 +336,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -447,6 +444,10 @@ extern unsigned long get_clock_freq(void); #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" @@ -538,6 +539,7 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD @@ -631,7 +633,6 @@ extern unsigned long get_clock_freq(void); #define ENET_ENV "" #endif -#if 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -644,8 +645,8 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \ - "dtbaddr=c00000\0" \ - "dtbfile=mpc8548cds.dtb\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=mpc8548cds.dtb\0" \ "eoi=mw e00400b0 0\0" \ "iack=md e00400a0 1\0" \ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ @@ -667,8 +668,6 @@ extern unsigned long get_clock_freq(void); PCI_ENV1 \ PCI_ENV2 \ ENET_ENV -#endif - #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -676,8 +675,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ @@ -685,8 +684,8 @@ extern unsigned long get_clock_freq(void); "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index e8fe99a..1d1b7c9 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -384,13 +381,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -482,6 +478,7 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index c10e551..a8f362f 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -292,9 +292,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8560@0" #define OF_SOC "soc8560@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -360,11 +357,12 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -521,6 +519,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index dc9cb1f..ba744e9 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -35,7 +35,7 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_QE /* Enable QE */ +#define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -63,9 +63,9 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ /* * Only possible on E500 Version 2 or newer cores. @@ -293,9 +293,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8568@0" #define OF_SOC "soc8568@e0000000" #define OF_QE "qe@e0080000" @@ -348,7 +345,7 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_UEC_ETH #ifndef CONFIG_TSEC_ENET -#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_ETHPRIME "FSL UEC0" #endif #define CONFIG_PHY_MODE_NEED_CHANGE #define CONFIG_eTSEC_MDIO_BUS @@ -399,9 +396,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "eTSEC1" -#undef CONFIG_TSEC3 -#undef CONFIG_TSEC4 -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 3 @@ -409,7 +403,10 @@ extern unsigned long get_clock_freq(void); #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -/* Options are: eTSEC[0-3] */ +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ #define CONFIG_ETHPRIME "eTSEC0" #endif /* CONFIG_TSEC_ENET */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 64dcbd0..7d8a380 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -185,6 +185,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -268,9 +269,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8641@0" #define OF_SOC "soc8641@f8000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -417,6 +415,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define CONFIG_ETHPRIME "eTSEC1" @@ -604,6 +606,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif +#define CONFIG_HAS_ETH0 1 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH3 1 diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 5470373..4acbcd5 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -96,7 +96,6 @@ #define CONFIG_SUPPORT_VFAT #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -168,36 +167,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ @@ -276,11 +254,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -306,9 +279,6 @@ #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ /* total size of a CAT24WC16 is 2048 bytes */ -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ @@ -317,7 +287,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#if 1 /* test-only */ + /* CAT24WC08/16... */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ @@ -325,15 +295,6 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE diff --git a/include/configs/PM854.h b/include/configs/PM854.h index dbf9422..a6a1e73 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -270,15 +270,19 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 6bdfa5d..9a17e3d 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -262,11 +262,12 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #endif /* CONFIG_TSEC_ENET */ @@ -391,6 +392,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:40:42:01:00:00 #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:40:42:01:00:01 diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 2b2ae01..dccdf0c 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -43,6 +43,10 @@ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 3d98500..e0c9d81 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -701,11 +701,9 @@ * Open firmware flat tree support *----------------------------------------------------------------------- */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 661712b..0147252 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -253,6 +253,8 @@ extern int tqm834x_num_flash_banks; #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -499,6 +501,7 @@ extern int tqm834x_num_flash_banks; */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR D2:DA:5E:44:BC:29 #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d5ce3ba..2f23c50 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -94,7 +94,6 @@ */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) /* TQM8540 & 8560 need DLL-override */ @@ -266,8 +265,12 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 34f0ebd..3880ec7 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -153,36 +153,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index c1b3da8..656784a 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -145,38 +145,16 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ + #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index cd92af2..85c2b96 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -59,6 +59,8 @@ */ #include <config_cmd_default.h> +#undef CONFIG_CMD_NET /* disabeled - causes compile errors */ + #define CONFIG_CMD_MEMORY #define CONFIG_CMD_LOADB #define CONFIG_CMD_REGINFO diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 510524a..104d94e 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -65,8 +65,10 @@ * Enable use of Ethernet * --- */ +#define CONFIG_MCFFEC -#define FEC_ENET +/* Enable Dma Timer */ +#define CONFIG_MCFTMR /* --- * Define baudrate for UART1 (console output, tftp, ...) @@ -76,6 +78,8 @@ * --- */ +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -151,6 +155,26 @@ #undef CONFIG_CMD_LOADB #undef CONFIG_CMD_MII +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* *----------------------------------------------------------------------------- diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index d0bf251..9085881 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -43,7 +43,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -74,7 +73,6 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ #define CFG_INIT_RAM_END (4 << 10) diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 1ab7b27..404e88a 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -44,6 +44,8 @@ */ #define CONFIG_BOOTCOMMAND "run net_nfs" #define CONFIG_BOOTDELAY 5 +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #define CONFIG_ETHADDR 00:06:3b:01:41:55 @@ -58,6 +60,8 @@ #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \ "filesystem over NFS; echo" +#define CONFIG_MCFTMR + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -147,11 +151,27 @@ /* * Ethernet */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 -#define CFG_ENET_BD_BASE 0x480000 -#define CFG_DISCOVER_PHY 1 +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* * Definitions for initial stack pointer and data area (in DPRAM) @@ -186,7 +206,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /* FLASH organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -216,7 +236,7 @@ "-(user)"; #if defined(CONFIG_CMD_MII) -#error MII commands don't work on iDMR board and sholud not be enabled. +#error "MII commands don't work on iDMR board and should not be enabled." #endif #endif /* _IDMR_H */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index b68c5aa..b7100e9 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -145,12 +145,9 @@ #if 0 /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 110ad44..7908e5a 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -42,7 +42,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS /*----------------------------------------------------------------------- @@ -67,11 +66,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE @@ -202,6 +201,7 @@ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "kozio=bootm ffc60000\0" \ + "pciconfighost=1\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -323,7 +323,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 26dbec9..a09dd74 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -39,7 +39,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 604b7d1..be48324 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -34,8 +34,8 @@ #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -72,7 +72,6 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ #define CFG_OCM_DATA_ADDR CFG_OCM_BASE @@ -143,15 +142,16 @@ #endif /* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_ECC_ON | \ +#define CONFIG_POST (CFG_POST_CACHE | \ CFG_POST_CPU | \ - CFG_POST_UART | \ - CFG_POST_I2C | \ - CFG_POST_CACHE | \ - CFG_POST_FPU | \ + CFG_POST_ECC_ON | \ CFG_POST_ETHER | \ - CFG_POST_SPR) + CFG_POST_FPU | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_RTC | \ + CFG_POST_SPR | \ + CFG_POST_UART) #define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ #define CONFIG_LOGBUFFER @@ -162,22 +162,29 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ + /* 64 byte page write mode using*/ + /* last 6 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ +#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ + +#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ +#if 0 +#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ +#endif -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" +#define CONFIG_PREBOOT "setenv bootdelay 15" #undef CONFIG_BOOTARGS @@ -226,6 +233,7 @@ #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 300 #define CONFIG_HAS_ETH0 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ @@ -391,9 +399,11 @@ #define CFG_GPIO_PHY1_RST 12 #define CFG_GPIO_FLASH_WP 14 #define CFG_GPIO_PHY0_RST 22 -#define CFG_GPIO_WATCHDOG 58 +#define CFG_GPIO_EEPROM_EXT_WP 55 +#define CFG_GPIO_EEPROM_INT_WP 57 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 +#define CFG_GPIO_WATCHDOG 63 /*----------------------------------------------------------------------- * PPC440 GPIO Configuration diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index e0a827f..9a21632 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -417,11 +417,9 @@ extern void __led_set(led_id_t id, int state); #define CFG_RESET_ADDRESS 0xfff00100 /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index f4f33f3..bd3107a 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -80,9 +80,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,7448@0" #define OF_TSI "tsi108@c0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 8ae38cb..bec442d 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -60,7 +60,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 8e51d2d..7653ba1 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -266,7 +266,10 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -274,12 +277,10 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO +#define CONFIG_CMD_REISER #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_USB - #define CONFIG_SUPPORT_VFAT /* @@ -488,10 +489,4 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x0000) -/* These addresses need to be shifted one place to the left - * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) - * These values are shifted - */ -#define CFG_ATA_PORT_ADDR(port) ((port) << 1) - #endif /* __CONFIG_H */ diff --git a/include/configs/r5200.h b/include/configs/r5200.h index 0e743bb..fc7658b 100644 --- a/include/configs/r5200.h +++ b/include/configs/r5200.h @@ -39,13 +39,10 @@ #define CONFIG_M5271 /* define processor type */ #define CONFIG_R5200 /* define board type */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_IPADDR 192.168.0.172 -#define CONFIG_SERVERIP 192.168.0.148 -#define CONFIG_ETHADDR 00:06:3b:00:44:55 +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -87,6 +84,27 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* Note: We only copy one sectors worth of application code from location * 10200000 for speed purposes. Increase the size if necessary */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 1831bef..e7d8a5a 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -313,9 +313,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -410,6 +407,8 @@ #define TSEC2_PHY_ADDR 0x1a #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -660,6 +659,7 @@ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 68d31ca..54eac38 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -270,9 +270,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8641@0" #define OF_SOC "soc@f8000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -380,6 +377,10 @@ #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC4_FLAGS TSEC_GIGABIT #define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ @@ -492,7 +493,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -513,7 +514,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -525,7 +526,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -542,6 +543,7 @@ #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD #endif +#define CONFIG_HAS_ETH0 1 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH3 1 diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 3f75a44..c2e1386 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -343,6 +343,11 @@ #define CONFIG_CMD_USB #endif +#ifndef CONFIG_RAINIER +#define CFG_POST_FPU_ON CFG_POST_FPU +#else +#define CFG_POST_FPU_ON 0 +#endif /* POST support */ #define CONFIG_POST (CFG_POST_MEMORY | \ @@ -350,7 +355,7 @@ CFG_POST_UART | \ CFG_POST_I2C | \ CFG_POST_CACHE | \ - CFG_POST_FPU | \ + CFG_POST_FPU_ON | \ CFG_POST_ETHER | \ CFG_POST_SPR) @@ -395,7 +400,8 @@ *----------------------------------------------------------------------*/ /* General PCI */ #define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index b4ab9ad..2efc8f1 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -31,14 +31,9 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_MII -/* #define MII_DEBUG */ -/* #define CONFIG_FEC_ENET */ #undef CONFIG_ETHER_ON_FEC1 #define CONFIG_ETHER_ON_FEC2 #define FEC_ENET -/* #define CONFIG_FEC2_PHY_NORXERR */ -/* #define CFG_DISCOVER_PHY */ -/* #define CONFIG_PHY_ADDR 0x1 */ #define CONFIG_FEC2_PHY 1 #define CONFIG_BAUDRATE 19200 @@ -100,14 +95,12 @@ #define CONFIG_CMD_ECHO #define CONFIG_CMD_IMMAP #define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#undef CONFIG_CMD_NET - - /* * Miscellaneous configurable options */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 1f41cf7..c5ae0cd 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -234,12 +234,13 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ @@ -378,6 +379,7 @@ /*Note: change below for your network setting!!! */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 55e2c8d..f32ff67 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -260,12 +260,13 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ @@ -406,6 +407,7 @@ /*Note: change below for your network setting!!! */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 0dbf4b7..b035857 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -592,9 +592,6 @@ typedef unsigned int led_id_t; /* pass open firmware flat tree */ #define CONFIG_OF_FLAT_TREE 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) #define CONFIG_OF_HAS_BD_T 1 diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h new file mode 100644 index 0000000..84998d4 --- /dev/null +++ b/include/configs/trizepsiv.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ + +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ +#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ +#define CONFIG_STUART 1 /* we use STUART on Conxs */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00018000 +#define CFG_GPSR1_VAL 0x00000000 +#define CFG_GPSR2_VAL 0x400dc000 +#define CFG_GPSR3_VAL 0x00000000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x00018000 +#define CFG_GPDR1_VAL 0x00028801 +#define CFG_GPDR2_VAL 0x520dc000 +#define CFG_GPDR3_VAL 0x0001E000 +#define CFG_GAFR0_L_VAL 0x801c0000 +#define CFG_GAFR0_U_VAL 0x00000013 +#define CFG_GAFR1_L_VAL 0x6990100A +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x010900F2 +#define CFG_GAFR3_L_VAL 0x54000003 +#define CFG_GAFR3_U_VAL 0x00002401 +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GRER3_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +#define CFG_GFER3_VAL 0x00000020 + + +#define CFG_PSSR_VAL 0x20 /* CHECK */ + +/* + * Clock settings + */ +#define CFG_CKEN 0x01FFFFFF /* CHECK */ +#define CFG_CCCR 0x02000290 /* 520Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x4df84df0 +#define CFG_MSC1_VAL 0x7ff87ff4 +#define CFG_MSC2_VAL 0xa26936d4 +#define CFG_MDCNFG_VAL 0x880009C9 +#define CFG_MDREFR_VAL 0x20ca201e +#define CFG_MDMRS_VAL 0x00220022 + +#define CFG_FLYCNFG_VAL 0x00000000 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000001 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00010204 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x0000c108 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) +/* #define CONFIG_DM9000_USE_8BIT */ +/* #define CONFIG_DM9000_USE_16BIT */ +#define CONFIG_DM9000_USE_32BIT + +#define CONFIG_USB_OHCI_NEW 1 +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 +#define CFG_USB_OHCI_REGS_BASE 0x4C000000 +#define CFG_USB_OHCI_SLOT_NAME "trizepsiv" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_CPU_INIT 1 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif /* __CONFIG_H */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 3b471d0..aed80ec 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -332,7 +332,6 @@ #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ #define CONFIG_IDE_PREINIT 1 -/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */ #define CFG_ATA_IDE0_OFFSET 0x0000 diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 9c536fd..74033b4 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -46,7 +46,6 @@ #define EXTCLK_83 83333333 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS @@ -69,11 +68,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE @@ -183,6 +182,7 @@ "cp.b ${fileaddr} FFFB0000 ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ + "pciconfighost=1\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -298,7 +298,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ diff --git a/include/ide.h b/include/ide.h index 6976a6c..222f4f8 100644 --- a/include/ide.h +++ b/include/ide.h @@ -26,6 +26,8 @@ #define IDE_BUS(dev) (dev >> 1) +#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) + #ifdef CONFIG_IDE_LED /* diff --git a/include/libfdt.h b/include/libfdt.h index 340e89d..38c65a9 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -140,6 +140,8 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, }) #define fdt_setprop_string(fdt, nodeoffset, name, str) \ fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) +int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, + const void *val, int len, int create); int fdt_delprop(void *fdt, int nodeoffset, const char *name); int fdt_add_subnode_namelen(void *fdt, int parentoffset, const char *name, int namelen); diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 4b48564..49ff80f 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -348,6 +348,7 @@ struct nand_chip { #define NAND_MFR_NATIONAL 0x8f #define NAND_MFR_RENESAS 0x07 #define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_MICRON 0x2c /** * struct nand_flash_dev - NAND Flash Device ID Structure diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 829dbf9..4d32c6a 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -705,8 +705,9 @@ #define SDRAM_CFG_SREN 0x40000000 #define SDRAM_CFG_ECC_EN 0x20000000 #define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_32_BE 0x00080000 diff --git a/include/nand.h b/include/nand.h index 23493f7..3c0752e 100644 --- a/include/nand.h +++ b/include/nand.h @@ -32,6 +32,7 @@ typedef struct mtd_info nand_info_t; extern int nand_curr_device; extern nand_info_t nand_info[]; +extern void nand_init(void); static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf) { diff --git a/include/s3c2410.h b/include/s3c2410.h index 86495f6..87135b4 100644 --- a/include/s3c2410.h +++ b/include/s3c2410.h @@ -69,75 +69,75 @@ typedef enum { #include <s3c24x0.h> -static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void) +static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void) { return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; } -static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void) +static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void) { return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE; } -static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void) +static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void) { return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE; } -static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void) +static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void) { return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE; } -static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void) +static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void) { return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE; } -static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void) +static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void) { return (S3C24X0_LCD * const)S3C24X0_LCD_BASE; } -static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void) +static inline S3C2410_NAND * S3C2410_GetBase_NAND(void) { return (S3C2410_NAND * const)S3C2410_NAND_BASE; } -static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) +static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) { return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000)); } -static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void) +static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void) { return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE; } -static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void) +static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void) { return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE; } -static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void) +static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void) { return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE; } -static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void) +static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void) { return (S3C24X0_I2C * const)S3C24X0_I2C_BASE; } -static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void) +static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void) { return (S3C24X0_I2S * const)S3C24X0_I2S_BASE; } -static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void) +static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void) { return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE; } -static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void) +static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void) { return (S3C24X0_RTC * const)S3C24X0_RTC_BASE; } -static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void) +static inline S3C2410_ADC * S3C2410_GetBase_ADC(void) { return (S3C2410_ADC * const)S3C2410_ADC_BASE; } -static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void) +static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void) { return (S3C24X0_SPI * const)S3C24X0_SPI_BASE; } -static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void) +static inline S3C2410_SDI * S3C2410_GetBase_SDI(void) { return (S3C2410_SDI * const)S3C2410_SDI_BASE; } diff --git a/include/serial.h b/include/serial.h index f7412fd..30bfde3 100644 --- a/include/serial.h +++ b/include/serial.h @@ -36,6 +36,10 @@ extern struct serial_device eserial4_device; #endif +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + extern void serial_initialize(void); extern void serial_devices_init(void); extern int serial_assign(char * name); diff --git a/lib_arm/board.c b/lib_arm/board.c index d37e5da..d28afc5 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -314,6 +314,10 @@ void start_armboot (void) drv_vfd_init(); #endif /* CONFIG_VFD */ +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif + /* IP Address */ gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); diff --git a/lib_m68k/Makefile b/lib_m68k/Makefile index 82165f0..03784fd 100644 --- a/lib_m68k/Makefile +++ b/lib_m68k/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)lib$(ARCH).a SOBJS = -COBJS = cache.o traps.o time.o board.o m68k_linux.o +COBJS = cache.o traps.o time.o interrupts.o board.o m68k_linux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 293fd04..43f97c4 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -30,9 +30,7 @@ #include <malloc.h> #include <devices.h> -#ifdef CONFIG_M5272 -#include <asm/immap_5272.h> -#endif +#include <asm/immap.h> #if defined(CONFIG_CMD_IDE) #include <ide.h> @@ -139,19 +137,19 @@ void *sbrk (ptrdiff_t increment) char *strmhz(char *buf, long hz) { - long l, n; - long m; + long l, n; + long m; - n = hz / 1000000L; + n = hz / 1000000L; - l = sprintf (buf, "%ld", n); + l = sprintf (buf, "%ld", n); - m = (hz % 1000000L) / 1000L; + m = (hz % 1000000L) / 1000L; - if (m != 0) - sprintf (buf+l, ".%03ld", m); + if (m != 0) + sprintf (buf+l, ".%03ld", m); - return (buf); + return (buf); } /* @@ -169,7 +167,7 @@ char *strmhz(char *buf, long hz) typedef int (init_fnc_t) (void); /************************************************************************ - * Init Utilities * + * Init Utilities ************************************************************************ * Some of this code should be moved into the core functions, * but let's get it working (again) first... @@ -221,6 +219,7 @@ static int init_func_i2c (void) */ init_fnc_t *init_sequence[] = { + get_clocks, env_init, init_baudrate, serial_init, @@ -371,6 +370,10 @@ board_init_f (ulong bootflag) */ bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ +#ifdef CFG_INIT_RAM_ADDR + bd->bi_sramstart = CFG_INIT_RAM_ADDR; /* start of SRAM memory */ + bd->bi_sramsize = CFG_INIT_RAM_END; /* size of SRAM memory */ +#endif bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ @@ -378,6 +381,14 @@ board_init_f (ulong bootflag) WATCHDOG_RESET (); bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ +#ifdef CONFIG_PCI + bd->bi_pcifreq = gd->pci_clk; /* PCI Freq in Hz */ +#endif +#ifdef CONFIG_EXTRA_CLOCK + bd->bi_inpfreq = gd->inp_clk; /* input Freq in Hz */ + bd->bi_vcofreq = gd->vco_clk; /* vco Freq in Hz */ + bd->bi_flbfreq = gd->flb_clk; /* flexbus Freq in Hz */ +#endif bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CFG_EXTBDINFO @@ -430,6 +441,10 @@ void board_init_r (gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif + debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); WATCHDOG_RESET (); @@ -489,7 +504,7 @@ void board_init_r (gd_t *id, ulong dest_addr) /* * Setup trap handlers */ - trap_init (0); + trap_init (CFG_SDRAM_BASE); #if !defined(CFG_NO_FLASH) puts ("FLASH: "); @@ -562,12 +577,48 @@ void board_init_r (gd_t *id, ulong dest_addr) if (s) s = (*e) ? e + 1 : e; } +#ifdef CONFIG_HAS_ETH1 + /* handle the 2nd ethernet address */ + + s = getenv ("eth1addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif +#ifdef CONFIG_HAS_ETH2 + /* handle the 3rd ethernet address */ + + s = getenv ("eth2addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif + +#ifdef CONFIG_HAS_ETH3 + /* handle 4th ethernet address */ + s = getenv("eth3addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif /* IP Address */ bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); WATCHDOG_RESET (); +#if defined(CONFIG_PCI) + /* + * Do pci configuration + */ + pci_init (); +#endif /** leave this here (after malloc(), environment and PCI are working) **/ /* Initialize devices */ @@ -640,15 +691,34 @@ void board_init_r (gd_t *id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif -#if defined(CONFIG_CMD_NET) && defined(FEC_ENET) +#if defined(CONFIG_CMD_NET) WATCHDOG_RESET(); +#if defined(FEC_ENET) eth_init(bd); #endif +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); + eth_initialize (bd); +#endif +#endif #ifdef CONFIG_POST post_run (NULL, POST_RAM | post_bootmode_get(0)); #endif +#if defined(CONFIG_CMD_PCMCIA) \ + && !defined(CONFIG_CMD_IDE) + WATCHDOG_RESET (); + puts ("PCMCIA:"); + pcmcia_init (); +#endif + +#if defined(CONFIG_CMD_IDE) + WATCHDOG_RESET (); + puts ("IDE: "); + ide_init (); +#endif + #ifdef CONFIG_LAST_STAGE_INIT WATCHDOG_RESET (); /* diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c new file mode 100644 index 0000000..1635d6f --- /dev/null +++ b/lib_m68k/interrupts.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor Inc + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/processor.h> +#include <asm/immap.h> + +#define NR_IRQS (CFG_NUM_IRQS) + +/* + * Interrupt vector functions. + */ +struct interrupt_action { + interrupt_handler_t *handler; + void *arg; +}; + +static struct interrupt_action irq_vecs[NR_IRQS]; + +static __inline__ unsigned short get_sr (void) +{ + unsigned short sr; + + asm volatile ("move.w %%sr,%0":"=r" (sr):); + + return sr; +} + +static __inline__ void set_sr (unsigned short sr) +{ + asm volatile ("move.w %0,%%sr"::"r" (sr)); +} + +/************************************************************************/ +/* + * Install and free an interrupt handler + */ +void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +{ + if ((vec < 0) || (vec > NR_IRQS)) { + printf ("irq_install_handler: wrong interrupt vector %d\n", + vec); + return; + } + + irq_vecs[vec].handler = handler; + irq_vecs[vec].arg = arg; +} + +void irq_free_handler (int vec) +{ + if ((vec < 0) || (vec > NR_IRQS)) { + return; + } + + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; +} + +void enable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr & ~0x0700); +} + +int disable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr | 0x0700); + + return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ +} + +void int_handler (struct pt_regs *fp) +{ + int vec; + + vec = (fp->vector >> 2) & 0xff; + if (vec > 0x40) + vec -= 0x40; + + if (irq_vecs[vec].handler != NULL) { + irq_vecs[vec].handler (irq_vecs[vec].arg); + } else { + printf ("\nBogus External Interrupt Vector %d\n", vec); + } +} diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c index 6c194f8..bea9744 100644 --- a/lib_m68k/m68k_linux.c +++ b/lib_m68k/m68k_linux.c @@ -25,6 +25,8 @@ #include <command.h> #include <image.h> #include <zlib.h> +#include <bzlib.h> +#include <environment.h> #include <asm/byteorder.h> DECLARE_GLOBAL_DATA_PTR; @@ -34,103 +36,190 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -extern image_header_t header; /* from cmd_bootm.c */ - -extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); - -static int linux_argc; -static char **linux_argv; - -static char **linux_env; -static char *linux_env_p; -static int linux_env_idx; +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include <status_led.h> +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif -static void linux_params_init (ulong start, char *commandline); -static void linux_env_set (char *env_name, char *env_val); +extern image_header_t header; -void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong * len_ptr, int verify) +void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, + int argc, char *argv[], + ulong addr, ulong * len_ptr, int verify) { - ulong len = 0, checksum; + ulong sp; + ulong len, checksum; ulong initrd_start, initrd_end; + ulong cmd_start, cmd_end; + ulong initrd_high; ulong data; - void (*theKernel) (int, char **, char **, int *); + int initrd_copy_to_ram = 1; + char *cmdline; + char *s; + bd_t *kbd; + void (*kernel) (bd_t *, ulong, ulong, ulong, ulong); image_header_t *hdr = &header; - char *commandline = getenv ("bootargs"); - char env_buf[12]; - theKernel = - (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep); + if ((s = getenv("initrd_high")) != NULL) { + /* a value of "no" or a similar string will act like 0, + * turning the "load high" feature off. This is intentional. + */ + initrd_high = simple_strtoul(s, NULL, 16); + if (initrd_high == ~0) + initrd_copy_to_ram = 0; + } else { /* not set, no restrictions to load high */ + initrd_high = ~0; + } + +#ifdef CONFIG_LOGBUFFER + kbd = gd->bd; + /* Prevent initrd from overwriting logbuffer */ + if (initrd_high < (kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD)) + initrd_high = kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD; + debug("## Logbuffer at 0x%08lX ", kbd->bi_memsize - LOGBUFF_LEN); +#endif + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CFG_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + asm("movel %%a7, %%d0\n" + "movel %%d0, %0\n": "=d"(sp): :"%d0"); + + debug("## Current stack ends at 0x%08lX ", sp); + + sp -= 2048; /* just to be sure */ + if (sp > CFG_BOOTMAPSZ) + sp = CFG_BOOTMAPSZ; + sp &= ~0xF; + + debug("=> set upper limit to 0x%08lX\n", sp); + + cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF); + kbd = (bd_t *) (((ulong) cmdline - sizeof(bd_t)) & ~0xF); + + if ((s = getenv("bootargs")) == NULL) + s = ""; + + strcpy(cmdline, s); + + cmd_start = (ulong) & cmdline[0]; + cmd_end = cmd_start + strlen(cmdline); + + *kbd = *(gd->bd); + +#ifdef DEBUG + printf("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end); + + do_bdinfo(NULL, 0, 0, NULL); +#endif + + if ((s = getenv("clocks_in_mhz")) != NULL) { + /* convert all clock information to MHz */ + kbd->bi_intfreq /= 1000000L; + kbd->bi_busfreq /= 1000000L; + } + + kernel = + (void (*)(bd_t *, ulong, ulong, ulong, ulong))ntohl(hdr->ih_ep); /* * Check if there is an initrd image */ + if (argc >= 3) { - show_boot_progress (9); + debug("Not skipping initrd\n"); + SHOW_BOOT_PROGRESS(9); - addr = simple_strtoul (argv[2], NULL, 16); + addr = simple_strtoul(argv[2], NULL, 16); - printf ("## Loading Ramdisk Image at %08lx ...\n", addr); + printf("## Loading RAMDisk Image at %08lx ...\n", addr); /* Copy header so we can blank CRC field for re-calculation */ - memcpy (&header, (char *) addr, sizeof (image_header_t)); + memmove(&header, (char *)addr, sizeof(image_header_t)); - if (ntohl (hdr->ih_magic) != IH_MAGIC) { - printf ("Bad Magic Number\n"); - show_boot_progress (-10); - do_reset (cmdtp, flag, argc, argv); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS(-10); + do_reset(cmdtp, flag, argc, argv); } data = (ulong) & header; - len = sizeof (image_header_t); + len = sizeof(image_header_t); - checksum = ntohl (hdr->ih_hcrc); + checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; - if (crc32 (0, (char *) data, len) != checksum) { - printf ("Bad Header Checksum\n"); - show_boot_progress (-11); - do_reset (cmdtp, flag, argc, argv); + if (crc32(0, (uchar *) data, len) != checksum) { + puts("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS(-11); + do_reset(cmdtp, flag, argc, argv); } - show_boot_progress (10); + SHOW_BOOT_PROGRESS(10); - print_image_hdr (hdr); + print_image_hdr(hdr); - data = addr + sizeof (image_header_t); - len = ntohl (hdr->ih_size); + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); if (verify) { ulong csum = 0; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + ulong cdata = data, edata = cdata + len; +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ - printf (" Verifying Checksum ... "); - csum = crc32 (0, (char *) data, len); - if (csum != ntohl (hdr->ih_dcrc)) { - printf ("Bad Data CRC\n"); - show_boot_progress (-12); - do_reset (cmdtp, flag, argc, argv); + puts(" Verifying Checksum ... "); + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + + while (cdata < edata) { + ulong chunk = edata - cdata; + + if (chunk > CHUNKSZ) + chunk = CHUNKSZ; + csum = crc32(csum, (uchar *) cdata, chunk); + cdata += chunk; + + WATCHDOG_RESET(); } - printf ("OK\n"); +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + csum = crc32(0, (uchar *) data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + + if (csum != ntohl(hdr->ih_dcrc)) { + puts("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS(-12); + do_reset(cmdtp, flag, argc, argv); + } + puts("OK\n"); } - show_boot_progress (11); + SHOW_BOOT_PROGRESS(11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_M68K) || (hdr->ih_type != IH_TYPE_RAMDISK)) { - printf ("No Linux M68K Ramdisk Image\n"); - show_boot_progress (-13); - do_reset (cmdtp, flag, argc, argv); + puts("No Linux ColdFire Ramdisk Image\n"); + SHOW_BOOT_PROGRESS(-13); + do_reset(cmdtp, flag, argc, argv); } /* * Now check if we have a multifile image */ } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { - ulong tail = ntohl (len_ptr[0]) % 4; + u_long tail = ntohl(len_ptr[0]) % 4; int i; - show_boot_progress (13); + SHOW_BOOT_PROGRESS(13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -138,130 +227,111 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], for (i = 1; len_ptr[i]; ++i) data += 4; /* add kernel length, and align */ - data += ntohl (len_ptr[0]); + data += ntohl(len_ptr[0]); if (tail) { data += 4 - tail; } - len = ntohl (len_ptr[1]); + len = ntohl(len_ptr[1]); } else { /* * no initrd image */ - show_boot_progress (14); + SHOW_BOOT_PROGRESS(14); - data = 0; + len = data = 0; } -#ifdef DEBUG if (!data) { - printf ("No initrd\n"); + debug("No initrd\n"); } -#endif if (data) { - initrd_start = data; - initrd_end = initrd_start + len; - } else { - initrd_start = 0; - initrd_end = 0; - } - - show_boot_progress (15); - -#ifdef DEBUG - printf ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) theKernel); -#endif - - linux_params_init (PHYSADDR (gd->bd->bi_boot_params), commandline); - - sprintf (env_buf, "%lu", gd->ram_size >> 20); - linux_env_set ("memsize", env_buf); - - sprintf (env_buf, "0x%08X", (uint) PHYSADDR (initrd_start)); - linux_env_set ("initrd_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start)); - linux_env_set ("initrd_size", env_buf); - - sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); - linux_env_set ("flash_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); - linux_env_set ("flash_size", env_buf); - - /* we assume that the kernel is in place */ - printf ("\nStarting kernel ...\n\n"); - - theKernel (linux_argc, linux_argv, linux_env, 0); -} - -static void linux_params_init (ulong start, char *line) -{ - char *next, *quote, *argp; - - linux_argc = 1; - linux_argv = (char **) start; - linux_argv[0] = 0; - argp = (char *) (linux_argv + LINUX_MAX_ARGS); - - next = line; - - while (line && *line && linux_argc < LINUX_MAX_ARGS) { - quote = strchr (line, '"'); - next = strchr (line, ' '); - - while (next != NULL && quote != NULL && quote < next) { - /* we found a left quote before the next blank - * now we have to find the matching right quote - */ - next = strchr (quote + 1, '"'); - if (next != NULL) { - quote = strchr (next + 1, '"'); - next = strchr (next + 1, ' '); + if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = (ulong) kbd - len; + initrd_start &= ~(4096 - 1); /* align on page */ + + if (initrd_high) { + ulong nsp; + + /* + * the inital ramdisk does not need to be within + * CFG_BOOTMAPSZ as it is not accessed until after + * the mm system is initialised. + * + * do the stack bottom calculation again and see if + * the initrd will fit just below the monitor stack + * bottom without overwriting the area allocated + * above for command line args and board info. + */ + asm("movel %%a7, %%d0\n" + "movel %%d0, %0\n": "=d"(nsp): :"%d0"); + + nsp -= 2048; /* just to be sure */ + nsp &= ~0xF; + + if (nsp > initrd_high) /* limit as specified */ + nsp = initrd_high; + + nsp -= len; + nsp &= ~(4096 - 1); /* align on page */ + + if (nsp >= sp) + initrd_start = nsp; } - } - if (next == NULL) { - next = line + strlen (line); + SHOW_BOOT_PROGRESS(12); + + debug + ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", + data, data + len - 1, len, len); + + initrd_end = initrd_start + len; + printf(" Loading Ramdisk to %08lx, end %08lx ... ", + initrd_start, initrd_end); +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + { + size_t l = len; + void *to = (void *)initrd_start; + void *from = (void *)data; + + while (l > 0) { + size_t tail = + (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove(to, from, tail); + to += tail; + from += tail; + l -= tail; + } + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove((void *)initrd_start, (void *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + puts("OK\n"); } - - linux_argv[linux_argc] = argp; - memcpy (argp, line, next - line); - argp[next - line] = 0; - - argp += next - line + 1; - linux_argc++; - - if (*next) - next++; - - line = next; + } else { + initrd_start = 0; + initrd_end = 0; } - linux_env = (char **) (((ulong) argp + 15) & ~15); - linux_env[0] = 0; - linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS); - linux_env_idx = 0; -} - -static void linux_env_set (char *env_name, char *env_val) -{ - if (linux_env_idx < LINUX_MAX_ENVS - 1) { - linux_env[linux_env_idx] = linux_env_p; - - strcpy (linux_env_p, env_name); - linux_env_p += strlen (env_name); + debug("## Transferring control to Linux (at address %08lx) ...\n", + (ulong) kernel); - strcpy (linux_env_p, "="); - linux_env_p += 1; + SHOW_BOOT_PROGRESS(15); - strcpy (linux_env_p, env_val); - linux_env_p += strlen (env_val); - - linux_env_p++; - linux_env[++linux_env_idx] = 0; - } + /* + * Linux Kernel Parameters (passing board info data): + * r3: ptr to board info data + * r4: initrd_start or 0 if no initrd + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + */ + (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + /* does not return */ } diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 12e38f0..28d371d 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -25,41 +25,26 @@ #include <common.h> -#include <asm/mcftimer.h> +#include <asm/timer.h> +#include <asm/immap.h> -#ifdef CONFIG_M5271 -#include <asm/m5271.h> -#include <asm/immap_5271.h> -#endif +DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_M5272 -#include <asm/m5272.h> -#include <asm/immap_5272.h> -#endif +static ulong timestamp; -#ifdef CONFIG_M5282 -#include <asm/m5282.h> +#if defined(CONFIG_MCFTMR) +#ifndef CFG_UDELAY_BASE +# error "uDelay base not defined!" #endif -#ifdef CONFIG_M5249 -#include <asm/m5249.h> -#include <asm/immap_5249.h> +#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK) +# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" #endif +extern void dtimer_intr_setup(void); - -static ulong timestamp; -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) -static unsigned short lastinc; -#endif - - -#if defined(CONFIG_M5272) -/* - * We use timer 3 which is running with a period of 1 us - */ void udelay(unsigned long usec) { - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3); + volatile dtmr_t *timerp = (dtmr_t *) (CFG_UDELAY_BASE); uint start, now, tmp; while (usec > 0) { @@ -70,77 +55,84 @@ void udelay(unsigned long usec) usec = usec - tmp; /* Set up TIMER 3 as timebase clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - timerp->timer_tcn = 0; + timerp->tmr = DTIM_DTMR_RST_RST; + timerp->tcn = 0; /* set period to 1 us */ - timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; + timerp->tmr = + CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | + DTIM_DTMR_RST_EN; - start = now = timerp->timer_tcn; + start = now = timerp->tcn; while (now < start + tmp) - now = timerp->timer_tcn; + now = timerp->tcn; } } -void mcf_timer_interrupt (void * not_used){ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); +void dtimer_interrupt(void *not_used) +{ + volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); - /* check for timer 4 interrupts */ - if ((intp->int_isr & 0x01000000) != 0) { + /* check for timer interrupt asserted */ + if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) { + timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); + timestamp++; return; } - - /* reset timer */ - timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; - timestamp ++; } -void timer_init (void) { - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); +void timer_init(void) +{ + volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); timestamp = 0; + timerp->tcn = 0; + timerp->trr = 0; + /* Set up TIMER 4 as clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; + timerp->tmr = DTIM_DTMR_RST_RST; + + /* initialize and enable timer interrupt */ + irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0); - /* initialize and enable timer 4 interrupt */ - irq_install_handler (72, mcf_timer_interrupt, 0); - intp->int_icr1 |= 0x0000000d; + timerp->tcn = 0; + timerp->trr = 1000; /* Interrupt every ms */ + + dtimer_intr_setup(); - timerp->timer_tcn = 0; - timerp->timer_trr = 1000; /* Interrupt every ms */ /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; + timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | + DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN; } -void reset_timer (void) +void reset_timer(void) { timestamp = 0; } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { return (timestamp - base); } -void set_timer (ulong t) +void set_timer(ulong t) { timestamp = t; } +#endif /* CONFIG_MCFTMR */ + +#if defined(CONFIG_MCFPIT) +#if !defined(CFG_PIT_BASE) +# error "CFG_PIT_BASE not defined!" #endif -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) +static unsigned short lastinc; void udelay(unsigned long usec) { - volatile unsigned short *timerp; + volatile pit_t *timerp = (pit_t *) (CFG_UDELAY_BASE); uint tmp; - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3); - while (usec > 0) { if (usec > 65000) tmp = 65000; @@ -149,55 +141,41 @@ void udelay(unsigned long usec) usec = usec - tmp; /* Set up TIMER 3 as timebase clock */ - timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; - timerp[MCFTIMER_PMR] = 0; + timerp->pcsr = PIT_PCSR_OVW; + timerp->pmr = 0; /* set period to 1 us */ - timerp[MCFTIMER_PCSR] = -#ifdef CONFIG_M5271 - (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#else /* !CONFIG_M5271 */ - (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#endif /* CONFIG_M5271 */ - - timerp[MCFTIMER_PMR] = tmp; - while (timerp[MCFTIMER_PCNTR] > 0); + timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN; + + timerp->pmr = tmp; + while (timerp->pcntr > 0) ; } } -void timer_init (void) +void timer_init(void) { - volatile unsigned short *timerp; - - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); timestamp = 0; /* Set up TIMER 4 as poll clock */ - timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; - timerp[MCFTIMER_PMR] = lastinc = 0; - timerp[MCFTIMER_PCSR] = -#ifdef CONFIG_M5271 - (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#else /* !CONFIG_M5271 */ - (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#endif /* CONFIG_M5271 */ + timerp->pcsr = PIT_PCSR_OVW; + timerp->pmr = lastinc = 0; + timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN; } -void set_timer (ulong t) +void set_timer(ulong t) { - volatile unsigned short *timerp; + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); timestamp = 0; - timerp[MCFTIMER_PMR] = lastinc = 0; + timerp->pmr = lastinc = 0; } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { unsigned short now, diff; - volatile unsigned short *timerp; + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); - now = timerp[MCFTIMER_PCNTR]; + now = timerp->pcntr; diff = -(now - lastinc); timestamp += diff; @@ -205,94 +183,12 @@ ulong get_timer (ulong base) return timestamp - base; } -void wait_ticks (unsigned long ticks) +void wait_ticks(unsigned long ticks) { - set_timer (0); - while (get_timer (0) < ticks); + set_timer(0); + while (get_timer(0) < ticks) ; } -#endif - - -#if defined(CONFIG_M5249) -/* - * We use timer 1 which is running with a period of 1 us - */ -void udelay(unsigned long usec) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1); - uint start, now, tmp; - - while (usec > 0) { - if (usec > 65000) - tmp = 65000; - else - tmp = usec; - usec = usec - tmp; - - /* Set up TIMER 1 as timebase clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - timerp->timer_tcn = 0; - /* set period to 1 us */ - /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ - timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; - - start = now = timerp->timer_tcn; - while (now < start + tmp) - now = timerp->timer_tcn; - } -} - -void mcf_timer_interrupt (void * not_used){ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); - - /* check for timer 2 interrupts */ - if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) { - return; - } - - /* reset timer */ - timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; - timestamp ++; -} - -void timer_init (void) { - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); - - timestamp = 0; - - /* Set up TIMER 2 as clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - - /* initialize and enable timer 2 interrupt */ - irq_install_handler (31, mcf_timer_interrupt, 0); - mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3); - - timerp->timer_tcn = 0; - timerp->timer_trr = 1000; /* Interrupt every ms */ - /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ - timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; -} - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} -#endif - +#endif /* CONFIG_MCFPIT */ /* * This function is derived from PowerPC code (read timebase as long long). @@ -307,7 +203,7 @@ unsigned long long get_ticks(void) * This function is derived from PowerPC code (timebase clock frequency). * On M68K it returns the number of timer ticks per second. */ -ulong get_tbclk (void) +ulong get_tbclk(void) { ulong tbclk; tbclk = CFG_HZ; diff --git a/lib_ppc/board.c b/lib_ppc/board.c index c87d46c..9aa67f9 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -209,9 +209,12 @@ static int init_baudrate (void) /***********************************************************************/ -#ifdef CONFIG_ADD_RAM_INFO -void board_add_ram_info(int); -#endif +void __board_add_ram_info(int use_default) +{ + /* please define platform specific board_add_ram_info() */ +} +void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info"))); + static int init_func_ram (void) { @@ -224,9 +227,7 @@ static int init_func_ram (void) if ((gd->ram_size = initdram (board_type)) > 0) { print_size (gd->ram_size, ""); -#ifdef CONFIG_ADD_RAM_INFO board_add_ram_info(0); -#endif putc('\n'); return (0); } diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c index 693bfe4..55fcc41 100644 --- a/libfdt/fdt_rw.c +++ b/libfdt/fdt_rw.c @@ -188,6 +188,32 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, return 0; } +/** + * fdt_find_and_setprop: Find a node and set it's property + * + * @fdt: ptr to device tree + * @node: path of node + * @prop: property name + * @val: ptr to new value + * @len: length of new property value + * @create: flag to create the property if it doesn't exist + * + * Convenience function to directly set a property given the path to the node. + */ +int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, + const void *val, int len, int create) +{ + int nodeoff = fdt_find_node_by_path(fdt, node); + + if (nodeoff < 0) + return nodeoff; + + if ((!create) && (fdt_get_property(fdt, nodeoff, prop, 0) == NULL)) + return 0; /* create flag not set; so exit quietly */ + + return fdt_setprop(fdt, nodeoff, prop, val, len); +} + int fdt_delprop(void *fdt, int nodeoffset, const char *name) { struct fdt_property *prop; @@ -59,6 +59,7 @@ extern int npe_initialize(bd_t *); extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); extern int atstk1000_eth_initialize(bd_t *); +extern int mcffec_initialize(bd_t*); static struct eth_device *eth_devices, *eth_current; @@ -249,6 +250,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_ATSTK1000) atstk1000_eth_initialize(bis); #endif +#if defined(CONFIG_MCFFEC) + mcffec_initialize(bis); +#endif if (!eth_devices) { puts ("No ethernet found.\n"); @@ -178,7 +178,7 @@ TftpSend (void) pkt += strlen((char *)pkt) + 1; /* try for more effic. blk size */ pkt += sprintf((char *)pkt,"blksize%c%d%c", - 0,htons(TftpBlkSizeOption),0); + 0,TftpBlkSizeOption,0); #ifdef CONFIG_MCAST_TFTP /* Check all preconditions before even trying the option */ if (!ProhibitMcast @@ -276,8 +276,12 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) #endif TftpState = STATE_OACK; TftpServerPort = src; - /* Check for 'blksize' option */ - for (i=0;i<len-8;i++) { + /* + * Check for 'blksize' option. + * Careful: "i" is signed, "len" is unsigned, thus + * something like "len-8" may give a *huge* number + */ + for (i=0; i+8<len; i++) { if (strcmp ((char*)pkt+i,"blksize") == 0) { TftpBlkSize = (unsigned short) simple_strtoul((char*)pkt+i+8,NULL,10); @@ -614,4 +618,4 @@ static void parse_multicast_oack(char *pkt, int len) #endif /* Multicast TFTP */ -#endif /* CFG_CMD_NET */ +#endif diff --git a/post/drivers/memory.c b/post/drivers/memory.c index a2c088b..fbc349a 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -461,6 +461,9 @@ int memory_post_test (int flags) unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? 256 << 20 : bd->bi_memsize) - (1 << 20); + /* Limit area to be tested with the board info struct */ + if (CFG_SDRAM_BASE + memsize > (ulong)bd) + memsize = (ulong)bd - CFG_SDRAM_BASE; if (flags & POST_SLOWTEST) { ret = memory_post_tests (CFG_SDRAM_BASE, memsize); diff --git a/rtc/Makefile b/rtc/Makefile index 96c68c0..2e6f3bd 100644 --- a/rtc/Makefile +++ b/rtc/Makefile @@ -31,7 +31,8 @@ COBJS = date.o \ bf5xx_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \ ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \ m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \ - mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o + mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o \ + mcfrtc.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c new file mode 100644 index 0000000..27386e5 --- /dev/null +++ b/rtc/mcfrtc.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE) + +#include <command.h> +#include <rtc.h> +#include <asm/immap.h> +#include <asm/rtc.h> + +#undef RTC_DEBUG + +#ifndef CFG_MCFRTC_BASE +#error RTC_BASE is not defined! +#endif + +#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) +#define STARTOFTIME 1970 + +void rtc_get(struct rtc_time *tmp) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + int rtc_days, rtc_hrs, rtc_mins; + int tim; + + rtc_days = rtc->days; + rtc_hrs = rtc->hourmin >> 8; + rtc_mins = RTC_HOURMIN_MINUTES(rtc->hourmin); + + tim = (rtc_days * 24) + rtc_hrs; + tim = (tim * 60) + rtc_mins; + tim = (tim * 60) + rtc->seconds; + + to_tm(tim, tmp); + + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + +#ifdef RTC_DEBUG + printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif +} + +void rtc_set(struct rtc_time *tmp) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + static int month_days[12] = { + 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 + }; + int days, i, months; + + if (tmp->tm_year > 2037) { + printf("Unable to handle. Exceeding integer limitation!\n"); + tmp->tm_year = 2027; + } +#ifdef RTC_DEBUG + printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + + /* calculate days by years */ + for (i = STARTOFTIME, days = 0; i < tmp->tm_year; i++) { + days += 365 + isleap(i); + } + + /* calculate days by months */ + months = tmp->tm_mon - 1; + for (i = 0; i < months; i++) { + days += month_days[i]; + + if (i == 1) + days += isleap(i); + } + + days += tmp->tm_mday - 1; + + rtc->days = days; + rtc->hourmin = (tmp->tm_hour << 8) | tmp->tm_min; + rtc->seconds = tmp->tm_sec; +} + +void rtc_reset(void) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + if ((rtc->cr & RTC_CR_EN) == 0) { + printf("real-time-clock was stopped. Now starting...\n"); + rtc->cr |= RTC_CR_EN; + } + + rtc->cr |= RTC_CR_SWR; +} + +#endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */ |