IGEP0046: QUAD 1GB DDR3 Micron Supportisee_imx_v2017.03_4.9.11_1.0.0_ga

2 files changed, 319 insertions, 0 deletions

diff --git a/board/isee/igep0046/mx6q_igep0046_4x256_nt.cfg b/board/isee/igep0046/mx6q_igep0046_4x256_nt.cfg
new file mode 100644
index 0000000..cc3915f
--- /dev/null
+++ b/board/isee/igep0046/mx6q_igep0046_4x256_nt.cfg
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * SPDX-License-IdentiFier:	GPL-2.0+
+ *
+ * ReFer docs/README.imxmage For more details about how-to conFigure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one oF
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device ConFiguration Data (DCD)
+ *
+ * Each entry must have the Format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address oF the register
+ *	value	  value to be stored in the register
+ */
+
+//============================================================================,			
+//init script For i.Mx6QP DDR3				
+//============================================================================,			
+// Revision History				
+// v01				
+//============================================================================,			
+				
+//wait = on				
+//============================================================================,			
+// Disable	WDOG			
+//============================================================================,			
+//setmem /16	0x020bc000, 0x30		
+				
+//============================================================================,			
+// Enable all clocks (they are disabled by ROM code)				
+//============================================================================,			
+
+/*
+DATA 4,	0x020c4068, 0xFFFFFFFF		
+DATA 4,	0x020c406c, 0xFFFFFFFF		
+DATA 4,	0x020c4070, 0xFFFFFFFF		
+DATA 4,	0x020c4074, 0xFFFFFFFF		
+DATA 4,	0x020c4078, 0xFFFFFFFF		
+DATA 4,	0x020c407c, 0xFFFFFFFF		
+DATA 4,	0x020c4080, 0xFFFFFFFF	
+*/
+
+//============================================================================,			
+// IOMUX				
+//============================================================================,			
+//DDR IO TYPE:				
+DATA 4,	0x020e0798, 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 	
+DATA 4,	0x020e0758, 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE 	
+				
+//CLOCK:				
+DATA 4,	0x020e0588, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0	
+DATA 4,	0x020e0594, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1	
+				
+//ADDRESS:				
+DATA 4,	0x020e056c, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS	
+DATA 4,	0x020e0578, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS	
+DATA 4,	0x020e074c, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS 	
+				
+//Control:				
+DATA 4,	0x020e057c, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET	
+DATA 4,	0x020e058c, 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be conFigured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS	
+DATA 4,	0x020e059c, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0	
+DATA 4,	0x020e05a0, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1	
+DATA 4,	0x020e078c, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS 	
+				
+//Data Strobes:				
+DATA 4,	0x020e0750, 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 	
+DATA 4,	0x020e05a8, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 	
+DATA 4,	0x020e05b0, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 	
+DATA 4,	0x020e0524, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 	
+DATA 4,	0x020e051c, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 	
+DATA 4,	0x020e0518, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 	
+DATA 4,	0x020e050c, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 	
+DATA 4,	0x020e05b8, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 	
+DATA 4,	0x020e05c0, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 	
+				
+// NONE				
+DATA 4,	0x020e0534, 0x00018200 	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02  (SDQS0_B_TRIM=01, SDQS0_TRIM=10)	
+DATA 4,	0x020e0538, 0x00008000 	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03  (SDQS1_B_TRIM=00, SDQS1_TRIM=00)	
+DATA 4,	0x020e053c, 0x00018200 	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04  (SDQS2_B_TRIM=01, SDQS2_TRIM=10)	
+DATA 4,	0x020e0540, 0x00018200 	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05  (SDQS3_B_TRIM=01, SDQS3_TRIM=10)	
+DATA 4,	0x020e0544, 0x00018200 	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06  (SDQS4_B_TRIM=01, SDQS4_TRIM=10)	
+DATA 4,	0x020e0548, 0x00018200 	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07  (SDQS5_B_TRIM=01, SDQS5_TRIM=10)	
+DATA 4,	0x020e054c, 0x00018200 	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08  (SDQS6_B_TRIM=01, SDQS6_TRIM=10)	
+DATA 4,	0x020e0550, 0x00018200 	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09  (SDQS7_B_TRIM=01, SDQS7_TRIM=10)	
+// - NONE
+				
+/* //Data: */
+DATA 4,	0x020e0774, 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE	
+DATA 4,	0x020e0784, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS 	
+DATA 4,	0x020e0788, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS 	
+DATA 4,	0x020e0794, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B2DS 	
+DATA 4,	0x020e079c, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B3DS 	
+DATA 4,	0x020e07a0, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B4DS 	
+DATA 4,	0x020e07a4, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B5DS 	
+DATA 4,	0x020e07a8, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B6DS 	
+DATA 4,	0x020e0748, 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B7DS 	
+				
+DATA 4,	0x020e05ac, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0	
+DATA 4,	0x020e05b4, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1	
+DATA 4,	0x020e0528, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2	
+DATA 4,	0x020e0520, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3	
+DATA 4,	0x020e0514, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4	
+DATA 4,	0x020e0510, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5	
+DATA 4,	0x020e05bc, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6	
+DATA 4,	0x020e05c4, 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7	
+				
+				
+//============================================================================,			
+// DDR Controller Registers				
+//============================================================================,			
+// ManuFacturer:	Micron			
+// Device Part Number:	MT41K128M16JT-125			
+// Clock Freq.: 	528MHz			
+// Density per CS in Gb: 	8			
+// Chip Selects used:	1			
+// Number oF Banks:	8			
+// Row address:    	14			
+// Column address: 	10			
+// Data bus width	64			
+//============================================================================,			
+//DATA 4,	0x021b001c, 0x00008000	// MMDC0_MDSCR, set the ConFiguration request bit during MMDC set up	
+				
+//============================================================================,			
+// Calibration setup.				
+//============================================================================,			
+DATA 4,	0x021b0800, 0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.	
+				
+// For target board, may need to run write leveling calibration to Fine tune these settings.				
+DATA 4,	0x021b080c, 0x00170016		
+DATA 4,	0x021b0810, 0x001F0017		
+DATA 4,	0x021b480c, 0x00170024		
+DATA 4,	0x021b4810, 0x000F001C		
+				
+////Read DQS Gating calibration				
+DATA 4,	0x021b083c, 0x02400250	// MPDGCTRL0 PHY0	
+DATA 4,	0x021b0840, 0x0244023C	// MPDGCTRL1 PHY0	
+DATA 4,	0x021b483c, 0x02440250	// MPDGCTRL0 PHY1	
+DATA 4,	0x021b4840, 0x02400228	// MPDGCTRL1 PHY1	
+				
+//Read calibration				
+DATA 4,	0x021b0848, 0x3C383A3C	// MPRDDLCTL PHY0	
+DATA 4,	0x021b4848, 0x3A3A3640	// MPRDDLCTL PHY1	
+				
+//Write calibration                     				
+DATA 4,	0x021b0850, 0x34383A38	// MPWRDLCTL PHY0	
+DATA 4,	0x021b4850, 0x3C343E36	// MPWRDLCTL PHY1	
+				
+//read data bit delay: (3 is the reccommended deFault value, although out oF reset value is 0)				
+DATA 4,	0x021b081c, 0x33333333	// DDR_PHY_P0_MPREDQBY0DL3	
+DATA 4,	0x021b0820, 0x33333333	// DDR_PHY_P0_MPREDQBY1DL3	
+DATA 4,	0x021b0824, 0x33333333	// DDR_PHY_P0_MPREDQBY2DL3	
+DATA 4,	0x021b0828, 0x33333333	// DDR_PHY_P0_MPREDQBY3DL3	
+DATA 4,	0x021b481c, 0x33333333	// DDR_PHY_P1_MPREDQBY0DL3	
+DATA 4,	0x021b4820, 0x33333333	// DDR_PHY_P1_MPREDQBY1DL3	
+DATA 4,	0x021b4824, 0x33333333	// DDR_PHY_P1_MPREDQBY2DL3	
+DATA 4,	0x021b4828, 0x33333333	// DDR_PHY_P1_MPREDQBY3DL3	
+				
+//For i.mx6qd parts oF versions A & B (v1.0, v1.1), uncomment the Following lines. For version C (v1.2), keep commented				
+//DATA 4,	0x021b08c0, 0x24912489	// Fine tune SDCLK duty cyc to low - seen to improve measured duty cycle oF i.mx6	
+// DATA 4,	0x021b48c0, 0x24914452		
+				
+// Complete calibration by Forced measurement:                  				
+DATA 4,	0x021b08b8, 0x00000800	// DDR_PHY_P0_MPMUR0, Frc_msr	
+DATA 4,	0x021b48b8, 0x00000800	// DDR_PHY_P0_MPMUR0, Frc_msr	
+//============================================================================,			
+// Calibration setup end				
+//============================================================================,			
+				
+//MMDC init: 				
+DATA 4,	0x021b0004, 0x00020036	// MMDC0_MDPDC	
+DATA 4,	0x021b0008, 0x09444040	// MMDC0_MDOTC	
+DATA 4,	0x021b000c, 0x54597955	// MMDC0_MDCFG0	
+DATA 4,	0x021b0010, 0xFF328F64	// MMDC0_MDCFG1	
+DATA 4,	0x021b0014, 0x01FF00DB	// MMDC0_MDCFG2	
+				
+//MDMISC: RALAT kept to the high level oF 5. 				
+//MDMISC: consider reducing RALAT iF your 528MHz board design allow that. Lower RALAT beneFits: 				
+//a. better operation at low Frequency, For LPDDR2 Freq < 100MHz, change RALAT to 3				
+//b. Small perFormence improvment 				
+DATA 4,	0x021b0018, 0x00011740	// MMDC0_MDMISC	
+DATA 4,	0x021b001c, 0x00008000	// MMDC0_MDSCR, set the ConFiguration request bit during MMDC set up	
+
+DATA 4,	0x021b002c, 0x000026D2	// MMDC0_MDRWD	
+DATA 4,	0x021b0030, 0x00591023	// MMDC0_MDOR	
+DATA 4,	0x021b0040, 0x00000027	// Chan0 CS0_END 	
+				
+//DATA 4,	0x021b0400, 0x14420000	// adopt bypass	
+
+DATA 4,	0x021b0000, 0x831A0000	// MMDC0_MDCTL	
+//DATA 4,	0x021b0890, 0x00400c58	//ZQ OFFset	
+				
+//## add noc DDR conFiguration				
+//DATA 4,	0x00bb0008, 0x00000000	// GPV0_S_A_0_DDRCONF	
+//DATA 4,	0x00bb000c, 0x2891E41A	// GPV0_S_A_0_DDRTIMING accorindt to MMDC0_MDCFG0/1/2	
+//DATA 4,	0x00bb0038, 0x00000564	// GPV0_S_A_0_Activate	
+//DATA 4,	0x00bb0014, 0x00000040      	// Read latency	
+//DATA 4,	0x00bb0028, 0x00000020      	// Aging control For IPU1/PRE0/PRE3	
+//DATA 4,	0x00bb002c, 0x00000020      	// Aging control For IPU2/PRE1/PRE2	
+				
+//Mode register writes                 				
+DATA 4,	0x021b001c, 0x02088032	// MMDC0_MDSCR, MR2 write, CS0	
+DATA 4,	0x021b001c, 0x00008033	// MMDC0_MDSCR, MR3 write, CS0	
+DATA 4,	0x021b001c, 0x00048031	// MMDC0_MDSCR, MR1 write, CS0	
+DATA 4,	0x021b001c, 0x19408030	// MMDC0_MDSCR, MR0write, CS0	
+DATA 4,	0x021b001c, 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0		
+				
+DATA 4,	0x021b0020, 0x00007800	// MMDC0_MDREF	
+				
+DATA 4,	0x021b0818, 0x00022227	// DDR_PHY_P0_MPODTCTRL	
+DATA 4,	0x021b4818, 0x00022227	// DDR_PHY_P1_MPODTCTRL	
+				
+DATA 4,	0x021b0004, 0x00025576	// MMDC0_MDPDC now SDCTL power down enabled	
+				
+DATA 4,	0x021b0404, 0x00011006	// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to selF-reFresh while the number oF idle cycle reached.	
+				
+DATA 4,	0x021b001c, 0x00000000	// MMDC0_MDSCR, clear this register (especially the conFiguration bit as initialization is complete)
+
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, 0x020c4060, 0x000000fb
\ No newline at end of file
diff --git a/configs/igep0046_imx6q_1G_defconfig b/configs/igep0046_imx6q_1G_defconfig
new file mode 100644
index 0000000..32c93aa
--- /dev/null
+++ b/configs/igep0046_imx6q_1G_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_IGEP0046=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0046/mx6q_igep0046_4x256_nt.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=n
+CONFIG_DEFAULT_FDT_FILE="imx6q-igep-base0040rd102.dtb"
+CONFIG_BASE0040=y
+CONFIG_HUSH_PARSER=y
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+#
+# LED Support
+#
+CONFIG_LED=y
+# CONFIG_LED_GPIO is not set
+CONFIG_LED_STATUS=y
+CONFIG_LED_STATUS_OFF=0
+CONFIG_LED_STATUS_BLINKING=1
+CONFIG_LED_STATUS_ON=2
+# CONFIG_LED_STATUS_GPIO is not set
+CONFIG_LED_STATUS_BOARD_SPECIFIC=y
+
+#
+# LEDs parameters
+#
+CONFIG_LED_STATUS0=y
+CONFIG_LED_STATUS_BIT=26
+CONFIG_LED_STATUS_STATE=0
+CONFIG_LED_STATUS_FREQ=2
+CONFIG_LED_STATUS1=y
+CONFIG_LED_STATUS_BIT1=27
+CONFIG_LED_STATUS_STATE1=0
+CONFIG_LED_STATUS_FREQ1=2
+CONFIG_LED_STATUS2=y
+CONFIG_LED_STATUS_BIT2=28
+CONFIG_LED_STATUS_STATE2=0
+CONFIG_LED_STATUS_FREQ2=2
+CONFIG_LED_STATUS3=y
+CONFIG_LED_STATUS_BIT3=400
+CONFIG_LED_STATUS_STATE3=0
+CONFIG_LED_STATUS_FREQ3=2
+# CONFIG_LED_STATUS4 is not set
+# CONFIG_LED_STATUS5 is not set
+# CONFIG_LED_STATUS_BOOT_ENABLE is not set
+# CONFIG_LED_STATUS_RED_ENABLE is not set
+# CONFIG_LED_STATUS_YELLOW_ENABLE is not set
+CONFIG_LED_STATUS_BLUE_ENABLE=y
+CONFIG_LED_STATUS_BLUE=1
+CONFIG_LED_STATUS_GREEN_ENABLE=y
+CONFIG_LED_STATUS_GREEN=1
+CONFIG_LED_STATUS_CMD=y
\ No newline at end of file