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authorMichal Simek <michal.simek@xilinx.com>2014-02-24 11:16:30 +0100
committerTom Rini <trini@ti.com>2014-03-04 09:27:35 -0500
commitf88a6869a10a5a7aea4c4fda52db854a693796b0 (patch)
tree7b57de3dad6d02376fa427ceb69fe8eb93d9f6a4
parent7450a7f7309eb06c5fb5ee7e20c864d266d79866 (diff)
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net: gem: Add OF initialization support
Gem can be directly initialized from DTB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--drivers/net/zynq_gem.c42
-rw-r--r--include/netdev.h1
2 files changed, 43 insertions, 0 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 6d4001b..101489c 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -12,6 +12,8 @@
#include <common.h>
#include <net.h>
#include <config.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
@@ -534,3 +536,43 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
return 1;
}
+
+#ifdef CONFIG_OF_CONTROL
+int zynq_gem_of_init(const void *blob)
+{
+ int offset = 0;
+ u32 ret = 0;
+ u32 reg, phy_reg;
+
+ debug("ZYNQ GEM: Initialization\n");
+
+ do {
+ offset = fdt_node_offset_by_compatible(blob, offset,
+ "xlnx,ps7-ethernet-1.00.a");
+ if (offset != -1) {
+ reg = fdtdec_get_addr(blob, offset, "reg");
+ if (reg != FDT_ADDR_T_NONE) {
+ offset = fdtdec_lookup_phandle(blob, offset,
+ "phy-handle");
+ if (offset != -1)
+ phy_reg = fdtdec_get_addr(blob, offset,
+ "reg");
+ else
+ phy_reg = 0;
+
+ debug("ZYNQ GEM: addr %x, phyaddr %x\n",
+ reg, phy_reg);
+
+ ret |= zynq_gem_initialize(NULL, reg,
+ phy_reg, 0);
+
+ } else {
+ debug("ZYNQ GEM: Can't get base address\n");
+ return -1;
+ }
+ }
+ } while (offset != -1);
+
+ return ret;
+}
+#endif
diff --git a/include/netdev.h b/include/netdev.h
index c684014..32b5073 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -91,6 +91,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
int txpp, int rxpp);
int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
unsigned long ctrl_addr);
+int zynq_gem_of_init(const void *blob);
int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
/*
* As long as the Xilinx xps_ll_temac ethernet driver has not its own interface