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| author | Jagan Teki <jteki@openedev.com> | 2015-08-17 18:27:47 +0530 |
|---|---|---|
| committer | Jagan Teki <jteki@openedev.com> | 2015-10-25 20:17:02 +0530 |
| commit | dda6241a1dc7fafd878e016acff9f1fb019c4f6e (patch) | |
| tree | 32071df4a358b3614ac24de42c0ee15a5ea9bf6a | |
| parent | 46ab8a6a13bdc18f64d745e829d75f61e8625c2c (diff) | |
| download | u-boot-imx-dda6241a1dc7fafd878e016acff9f1fb019c4f6e.zip u-boot-imx-dda6241a1dc7fafd878e016acff9f1fb019c4f6e.tar.gz u-boot-imx-dda6241a1dc7fafd878e016acff9f1fb019c4f6e.tar.bz2 | |
spi: zynq_spi: Rename baudrate divisor mask name
Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK
for more readable.
Signed-off-by: Jagan Teki <jteki@openedev.com>
| -rw-r--r-- | drivers/spi/zynq_spi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 293499c..04d4b71 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ #define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ #define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ -#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ #define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ @@ -270,7 +270,7 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed) baud_rate_val++; plat->speed_hz = speed / (2 << baud_rate_val); } - confr &= ~ZYNQ_SPI_CR_BRD_MASK; + confr &= ~ZYNQ_SPI_CR_BAUD_MASK; confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT); writel(confr, ®s->cr); |