diff options
| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-01-15 17:13:24 +0900 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-16 10:24:39 -0500 |
| commit | d928664f4101e24128c879956d1aa7c76509ea6a (patch) | |
| tree | 053f5991eb524a544cb9eeed765064388684f13a | |
| parent | eb8b3f1edd405504febe6c9797750817b270f543 (diff) | |
| download | u-boot-imx-d928664f4101e24128c879956d1aa7c76509ea6a.zip u-boot-imx-d928664f4101e24128c879956d1aa7c76509ea6a.tar.gz u-boot-imx-d928664f4101e24128c879956d1aa7c76509ea6a.tar.bz2 | |
powerpc: 74xx_7xx: remove 74xx_7xx cpu support
All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
93 files changed, 5 insertions, 18881 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 701ec33..1f77359 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -319,12 +319,6 @@ S: Maintained T: git git://git.denx.de/u-boot-mpc86xx.git F: arch/powerpc/cpu/mpc86xx/ -POWERPC PPC74XX PPC7XX -M: Wolfgang Denk <wd@denx.de> -S: Maintained -T: git git://git.denx.de/u-boot-74xx-7xx.git -F: arch/powerpc/cpu/74xx_7xx/ - POWERPC PPC4XX M: Stefan Roese <sr@denx.de> S: Maintained @@ -316,12 +316,6 @@ LIST_85xx="$(targets_by_cpu mpc85xx)" LIST_86xx="$(targets_by_cpu mpc86xx)" ######################################################################### -## 74xx/7xx Systems -######################################################################### - -LIST_74xx_7xx="$(targets_by_cpu 74xx_7xx)" - -######################################################################### ## PowerPC groups ######################################################################### @@ -342,7 +336,6 @@ LIST_powerpc=" \ ${LIST_85xx} \ ${LIST_86xx} \ ${LIST_4xx} \ - ${LIST_74xx_7xx}\ " # Alias "ppc" -> "powerpc" to not break compatibility with older scripts @@ -182,7 +182,6 @@ Directory Hierarchy: /lib Architecture specific library files /powerpc Files generic to PowerPC architecture /cpu CPU specific files - /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs /mpc5xx Files specific to Freescale MPC5xx CPUs /mpc5xxx Files specific to Freescale MPC5xxx CPUs /mpc8xx Files specific to Freescale MPC8xx CPUs diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 7a50301..8e5a3e2 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -7,9 +7,6 @@ config SYS_ARCH choice prompt "CPU select" -config 74xx_7xx - bool "74xx" - config MPC512X bool "MPC512X" @@ -39,7 +36,6 @@ config 4xx endchoice -source "arch/powerpc/cpu/74xx_7xx/Kconfig" source "arch/powerpc/cpu/mpc512x/Kconfig" source "arch/powerpc/cpu/mpc5xx/Kconfig" source "arch/powerpc/cpu/mpc5xxx/Kconfig" diff --git a/arch/powerpc/cpu/74xx_7xx/Kconfig b/arch/powerpc/cpu/74xx_7xx/Kconfig deleted file mode 100644 index b2f1a59..0000000 --- a/arch/powerpc/cpu/74xx_7xx/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -menu "74xx_7xx CPU" - depends on 74xx_7xx - -config SYS_CPU - default "74xx_7xx" - -choice - prompt "Target select" - -config TARGET_P3G4 - bool "Support P3G4" - -config TARGET_ZUMA - bool "Support ZUMA" - -config TARGET_PPMC7XX - bool "Support ppmc7xx" - -config TARGET_ELPPC - bool "Support ELPPC" - -config TARGET_MPC7448HPC2 - bool "Support mpc7448hpc2" - -endchoice - -source "board/eltec/elppc/Kconfig" -source "board/evb64260/Kconfig" -source "board/freescale/mpc7448hpc2/Kconfig" -source "board/ppmc7xx/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/74xx_7xx/Makefile b/arch/powerpc/cpu/74xx_7xx/Makefile deleted file mode 100644 index f31fe75..0000000 --- a/arch/powerpc/cpu/74xx_7xx/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = cache.o kgdb.o io.o -obj-y += traps.o cpu.o cpu_init.o speed.o interrupts.o diff --git a/arch/powerpc/cpu/74xx_7xx/cache.S b/arch/powerpc/cpu/74xx_7xx/cache.S deleted file mode 100644 index 66c7298..0000000 --- a/arch/powerpc/cpu/74xx_7xx/cache.S +++ /dev/null @@ -1,404 +0,0 @@ -#include <config.h> -#include <74xx_7xx.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#ifndef CACHE_LINE_SIZE -# define CACHE_LINE_SIZE L1_CACHE_BYTES -#endif - -#if CACHE_LINE_SIZE == 128 -#define LG_CACHE_LINE_SIZE 7 -#elif CACHE_LINE_SIZE == 32 -#define LG_CACHE_LINE_SIZE 5 -#elif CACHE_LINE_SIZE == 16 -#define LG_CACHE_LINE_SIZE 4 -#elif CACHE_LINE_SIZE == 8 -#define LG_CACHE_LINE_SIZE 3 -#else -# error "Invalid cache line size!" -#endif - -/* - * Invalidate L1 instruction cache. - */ -_GLOBAL(invalidate_l1_instruction_cache) - mfspr r3,PVR - rlwinm r3,r3,16,16,31 - cmpi 0,r3,1 - beqlr /* for 601, do nothing */ - /* 603/604 processor - use invalidate-all bit in HID0 */ - mfspr r3,HID0 - ori r3,r3,HID0_ICFI - mtspr HID0,r3 - isync - blr - -/* - * Invalidate L1 data cache. - */ -_GLOBAL(invalidate_l1_data_cache) - mfspr r3,HID0 - ori r3,r3,HID0_DCFI - mtspr HID0,r3 - isync - blr - -/* - * Flush data cache. - */ -_GLOBAL(flush_dcache) - lis r3,0 - lis r5,CACHE_LINE_SIZE -flush: - cmp 0,1,r3,r5 - bge done - lwz r5,0(r3) - lis r5,CACHE_LINE_SIZE - addi r3,r3,0x4 - b flush -done: - blr -/* - * Write any modified data cache blocks out to memory - * and invalidate the corresponding instruction cache blocks. - * This is a no-op on the 601. - * - * flush_icache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(flush_icache_range) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CACHE_LINE_SIZE - bdnz 2b - sync /* additional sync needed on g4 */ - isync - blr -/* - * Write any modified data cache blocks out to memory. - * Does not invalidate the corresponding cache lines (especially for - * any corresponding instruction cache). - * - * clean_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(clean_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 /* align r3 down to cache line */ - subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ - add r4,r4,r5 /* r4 += cache_line_size-1 */ - srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ - beqlr /* if r4 == 0 return */ - mtctr r4 /* ctr = r4 */ - - sync -1: dcbst 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - blr - -/* - * Write any modified data cache blocks out to memory - * and invalidate the corresponding instruction cache blocks. - * - * flush_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(flush_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - - sync -1: dcbf 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbf's to get to ram */ - blr - -/* - * Like above, but invalidate the D-cache. This is used by the 8xx - * to invalidate the cache so the PPC core doesn't get stale data - * from the CPM (no cache snooping here :-). - * - * invalidate_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(invalidate_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - - sync -1: dcbi 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbi's to get to ram */ - blr - -/* - * Flush a particular page from the data cache to RAM. - * Note: this is necessary because the instruction cache does *not* - * snoop from the data cache. - * This is a no-op on the 601 which has a unified cache. - * - * void __flush_page_to_ram(void *page) - */ -_GLOBAL(__flush_page_to_ram) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - rlwinm r3,r3,0,0,19 /* Get page base address */ - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ - mtctr r4 - mr r6,r3 -0: dcbst 0,r3 /* Write line to ram */ - addi r3,r3,CACHE_LINE_SIZE - bdnz 0b - sync - mtctr r4 -1: icbi 0,r6 - addi r6,r6,CACHE_LINE_SIZE - bdnz 1b - sync - isync - blr - -/* - * Flush a particular page from the instruction cache. - * Note: this is necessary because the instruction cache does *not* - * snoop from the data cache. - * This is a no-op on the 601 which has a unified cache. - * - * void __flush_icache_page(void *page) - */ -_GLOBAL(__flush_icache_page) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ - mtctr r4 -1: icbi 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync - isync - blr - -/* - * Clear a page using the dcbz instruction, which doesn't cause any - * memory traffic (except to write out any cache lines which get - * displaced). This only works on cacheable memory. - */ -_GLOBAL(clear_page) - li r0,4096/CACHE_LINE_SIZE - mtctr r0 -1: dcbz 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - blr - -/* - * Enable L1 Instruction cache - */ -_GLOBAL(icache_enable) - mfspr r3, HID0 - li r5, HID0_ICFI|HID0_ILOCK - andc r3, r3, r5 - ori r3, r3, HID0_ICE - ori r5, r3, HID0_ICFI - mtspr HID0, r5 - mtspr HID0, r3 - isync - blr - -/* - * Disable L1 Instruction cache - */ -_GLOBAL(icache_disable) - mflr r4 - bl invalidate_l1_instruction_cache /* uses r3 */ - sync - mtlr r4 - mfspr r3, HID0 - li r5, 0 - ori r5, r5, HID0_ICE - andc r3, r3, r5 - mtspr HID0, r3 - isync - blr - -/* - * Is instruction cache enabled? - */ -_GLOBAL(icache_status) - mfspr r3, HID0 - andi. r3, r3, HID0_ICE - blr - - -_GLOBAL(l1dcache_enable) - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ - sync - blr - -/* - * Enable data cache(s) - L1 and optionally L2 - * Calls l2cache_enable. LR saved in r5 - */ -_GLOBAL(dcache_enable) - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ - sync -#ifdef CONFIG_SYS_L2 - mflr r5 - bl l2cache_enable /* uses r3 and r4 */ - sync - mtlr r5 -#endif - blr - - -/* - * Disable data cache(s) - L1 and optionally L2 - * Calls flush_dcache and l2cache_disable_no_flush. - * LR saved in r4 - */ -_GLOBAL(dcache_disable) - mflr r4 /* save link register */ - bl flush_dcache /* uses r3 and r5 */ - sync - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - li r5, HID0_DCE|HID0_DCFI - andc r3, r3, r5 /* no enable, no invalidate */ - mtspr HID0, r3 - sync -#ifdef CONFIG_SYS_L2 - bl l2cache_disable_no_flush /* uses r3 */ -#endif - mtlr r4 /* restore link register */ - blr - -/* - * Is data cache enabled? - */ -_GLOBAL(dcache_status) - mfspr r3, HID0 - andi. r3, r3, HID0_DCE - blr - -/* - * Invalidate L2 cache using L2I and polling L2IP or L2I - */ -_GLOBAL(l2cache_invalidate) - sync - mfspr r3, l2cr - oris r3, r3, L2CR_L2I@h - sync - mtspr l2cr, r3 - sync - mfspr r3, PVR - sync - rlwinm r3, r3, 16,16,31 - cmpli 0,r3,0x8000 /* 7451, 7441 */ - beq 0,inv_7450 - cmpli 0,r3,0x8001 /* 7455, 7445 */ - beq 0,inv_7450 - cmpli 0,r3,0x8002 /* 7457, 7447 */ - beq 0,inv_7450 - cmpli 0,r3,0x8003 /* 7447A */ - beq 0,inv_7450 - cmpli 0,r3,0x8004 /* 7448 */ - beq 0,inv_7450 -invl2: - mfspr r3, l2cr - andi. r3, r3, L2CR_L2IP - bne invl2 - /* turn off the global invalidate bit */ - mfspr r3, l2cr - rlwinm r3, r3, 0, 11, 9 - sync - mtspr l2cr, r3 - sync - blr -inv_7450: - mfspr r3, l2cr - andis. r3, r3, L2CR_L2I@h - bne inv_7450 - blr - -/* - * Enable L2 cache - * Calls l2cache_invalidate. LR is saved in r4 - */ -_GLOBAL(l2cache_enable) - mflr r4 /* save link register */ - bl l2cache_invalidate /* uses r3 */ - sync - lis r3, L2_ENABLE@h - ori r3, r3, L2_ENABLE@l - mtspr l2cr, r3 - isync - mtlr r4 /* restore link register */ - blr - -/* - * Disable L2 cache - * Calls flush_dcache. LR is saved in r4 - */ -_GLOBAL(l2cache_disable) - mflr r4 /* save link register */ - bl flush_dcache /* uses r3 and r5 */ - sync - mtlr r4 /* restore link register */ -l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ - lis r3, L2_INIT@h - ori r3, r3, L2_INIT@l - mtspr l2cr, r3 - isync - blr diff --git a/arch/powerpc/cpu/74xx_7xx/config.mk b/arch/powerpc/cpu/74xx_7xx/config.mk deleted file mode 100644 index 4cd1a26..0000000 --- a/arch/powerpc/cpu/74xx_7xx/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mstring diff --git a/arch/powerpc/cpu/74xx_7xx/cpu.c b/arch/powerpc/cpu/74xx_7xx/cpu.c deleted file mode 100644 index 6cd54bf..0000000 --- a/arch/powerpc/cpu/74xx_7xx/cpu.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * cpu.c - * - * CPU specific code - * - * written or collected and sometimes rewritten by - * Magnus Damm <damm@bitsmart.com> - * - * minor modifications by - * Wolfgang Denk <wd@denx.de> - * - * more modifications by - * Josh Huber <huber@mclx.com> - * added support for the 74xx series of cpus - * added support for the 7xx series of cpus - * made the code a little less hard-coded, and more auto-detectish - */ - -#include <common.h> -#include <command.h> -#include <74xx_7xx.h> -#include <asm/cache.h> - -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -cpu_t -get_cpu_type(void) -{ - uint pvr = get_pvr(); - cpu_t type; - - type = CPU_UNKNOWN; - - switch (PVR_VER(pvr)) { - case 0x000c: - type = CPU_7400; - break; - case 0x0008: - type = CPU_750; - - if (((pvr >> 8) & 0xff) == 0x01) { - type = CPU_750CX; /* old CX (80100 and 8010x?)*/ - } else if (((pvr >> 8) & 0xff) == 0x22) { - type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */ - } else if (((pvr >> 8) & 0xff) == 0x33) { - type = CPU_750CX; /* CXe (83311) */ - } else if (((pvr >> 12) & 0xF) == 0x3) { - type = CPU_755; - } - break; - - case 0x7000: - type = CPU_750FX; - break; - - case 0x7002: - type = CPU_750GX; - break; - - case 0x800C: - type = CPU_7410; - break; - - case 0x8000: - type = CPU_7450; - break; - - case 0x8001: - type = CPU_7455; - break; - - case 0x8002: - type = CPU_7457; - break; - - case 0x8003: - type = CPU_7447A; - break; - - case 0x8004: - type = CPU_7448; - break; - - default: - break; - } - - return type; -} - -/* ------------------------------------------------------------------------- */ - -#if !defined(CONFIG_BAB7xx) -int checkcpu (void) -{ - uint type = get_cpu_type(); - uint pvr = get_pvr(); - ulong clock = gd->cpu_clk; - char buf[32]; - char *str; - - puts ("CPU: "); - - switch (type) { - case CPU_750CX: - printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"", - (pvr>>8) & 0xf, - pvr & 0xf); - goto PR_CLK; - - case CPU_750: - str = "750"; - break; - - case CPU_750FX: - str = "750FX"; - break; - - case CPU_750GX: - str = "750GX"; - break; - - case CPU_755: - str = "755"; - break; - - case CPU_7400: - str = "MPC7400"; - break; - - case CPU_7410: - str = "MPC7410"; - break; - - case CPU_7447A: - str = "MPC7447A"; - break; - - case CPU_7448: - str = "MPC7448"; - break; - - case CPU_7450: - str = "MPC7450"; - break; - - case CPU_7455: - str = "MPC7455"; - break; - - case CPU_7457: - str = "MPC7457"; - break; - - default: - printf("Unknown CPU -- PVR: 0x%08x\n", pvr); - return -1; - } - - printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF); -PR_CLK: - printf (" @ %s MHz\n", strmhz(buf, clock)); - - return (0); -} -#endif -/* these two functions are unimplemented currently [josh] */ - -/* -------------------------------------------------------------------- */ -/* L1 i-cache */ - -int -checkicache(void) -{ - return 0; /* XXX */ -} - -/* -------------------------------------------------------------------- */ -/* L1 d-cache */ - -int -checkdcache(void) -{ - return 0; /* XXX */ -} - -/* -------------------------------------------------------------------- */ - -static inline void -soft_restart(unsigned long addr) -{ - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); - __asm__ __volatile__ ("mtspr 27, 4"); - __asm__ __volatile__ ("rfi"); - - while(1); /* not reached */ -} - - -#if !defined(CONFIG_BAB7xx) && \ - !defined(CONFIG_ELPPC) && \ - !defined(CONFIG_PPMC7XX) -/* no generic way to do board reset. simply call soft_reset. */ -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - /* flush and disable I/D cache */ - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 4"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 5"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on your - * system and assign it to CONFIG_SYS_RESET_ADDRESS. - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - soft_restart(addr); - - /* not reached */ - while(1) - ; - - return 1; -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * For the 7400 the TB clock runs at 1/4 the cpu bus speed. - */ -#ifndef CONFIG_SYS_BUS_CLK -#define CONFIG_SYS_BUS_CLK gd->bus_clk -#endif - -unsigned long get_tbclk(void) -{ - return CONFIG_SYS_BUS_CLK / 4; -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -#if !defined(CONFIG_BAB7xx) -void -watchdog_reset(void) -{ - -} -#endif /* !CONFIG_BAB7xx */ -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_OF_LIBFDT -void ft_cpu_setup(void *blob, bd_t *bd) -{ - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 4, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); - - fdt_fixup_ethernet(blob); -} -#endif -/* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/74xx_7xx/cpu_init.c b/arch/powerpc/cpu/74xx_7xx/cpu_init.c deleted file mode 100644 index a6a8788..0000000 --- a/arch/powerpc/cpu/74xx_7xx/cpu_init.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * cpu_init.c - low level cpu init - * - * there's really nothing going on here yet. future work area? - */ - -#include <common.h> -#include <74xx_7xx.h> - -/* - * Breath some life into the CPU... - * - * there's basically nothing to do here since the memory controller - * isn't on the CPU in this case. - */ -void -cpu_init_f (void) -{ - switch (get_cpu_type()) { - case CPU_7450: - case CPU_7455: - case CPU_7457: - case CPU_7447A: - case CPU_7448: - /* enable the timebase bit in HID0 */ - set_hid0(get_hid0() | 0x4000000); - break; - default: - /* do nothing */ - break; - } -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ - return (0); -} diff --git a/arch/powerpc/cpu/74xx_7xx/interrupts.c b/arch/powerpc/cpu/74xx_7xx/interrupts.c deleted file mode 100644 index a906243..0000000 --- a/arch/powerpc/cpu/74xx_7xx/interrupts.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * interrupts.c - just enough support for the decrementer/timer - */ - -#include <common.h> -#include <mpc8xx.h> -#include <mpc8xx_irq.h> -#include <asm/processor.h> -#include <commproc.h> -#include <command.h> - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - debug("interrupt_init: GT main cause reg: %08x:%08x\n", - GTREGREAD(LOW_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(HIGH_INTERRUPT_CAUSE_REGISTER)); - debug("interrupt_init: ethernet cause regs: %08x %08x %08x\n", - GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(ETHERNET1_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(ETHERNET2_INTERRUPT_CAUSE_REGISTER)); - debug("interrupt_init: ethernet mask regs: %08x %08x %08x\n", - GTREGREAD(ETHERNET0_INTERRUPT_MASK_REGISTER), - GTREGREAD(ETHERNET1_INTERRUPT_MASK_REGISTER), - GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER)); - debug("interrupt_init: setting decrementer_count\n"); - - *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void -external_interrupt(struct pt_regs *regs) -{ - puts("external_interrupt (oops!)\n"); -} - -volatile ulong timestamp = 0; - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * Trivial implementation - no need to be really accurate. - */ -void -timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -/* - * Install and free a interrupt handler. - */ - -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) -{ - -} - -void -irq_free_handler(int vec) -{ - -} - -/****************************************************************************/ - -void -do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[]) -{ - puts("IRQ related functions are unimplemented currently.\n"); -} diff --git a/arch/powerpc/cpu/74xx_7xx/io.S b/arch/powerpc/cpu/74xx_7xx/io.S deleted file mode 100644 index 3b4b08a..0000000 --- a/arch/powerpc/cpu/74xx_7xx/io.S +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel <aheppel@sysgo.de> - * Copyright (C) 2002 Wolfgang Denk <wd@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <ppc_asm.tmpl> - -/* ------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0(3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,0,r3 - sync - blr diff --git a/arch/powerpc/cpu/74xx_7xx/kgdb.S b/arch/powerpc/cpu/74xx_7xx/kgdb.S deleted file mode 100644 index 42b3a76..0000000 --- a/arch/powerpc/cpu/74xx_7xx/kgdb.S +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <command.h> -#include <74xx_7xx.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#if defined(CONFIG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - lis r3,0 - addis r4,r0,0x0040 -kgdb_flush_loop: - lwz r5,0(r3) - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - cmp 0,0,r3,r4 - bne kgdb_flush_loop - SYNC - mfspr r3,1008 - ori r3,r3,0x8800 - mtspr 1008,r3 - sync - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CONFIG_SYS_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CONFIG_SYS_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif diff --git a/arch/powerpc/cpu/74xx_7xx/speed.c b/arch/powerpc/cpu/74xx_7xx/speed.c deleted file mode 100644 index 5ffa41c..0000000 --- a/arch/powerpc/cpu/74xx_7xx/speed.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <74xx_7xx.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern unsigned long get_board_bus_clk (void); - -static const int hid1_multipliers_x_10[] = { - 25, /* 0000 - 2.5x */ - 75, /* 0001 - 7.5x */ - 70, /* 0010 - 7x */ - 10, /* 0011 - bypass */ - 20, /* 0100 - 2x */ - 65, /* 0101 - 6.5x */ - 100, /* 0110 - 10x */ - 45, /* 0111 - 4.5x */ - 30, /* 1000 - 3x */ - 55, /* 1001 - 5.5x */ - 40, /* 1010 - 4x */ - 50, /* 1011 - 5x */ - 80, /* 1100 - 8x */ - 60, /* 1101 - 6x */ - 35, /* 1110 - 3.5x */ - 0 /* 1111 - off */ -}; - -/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */ -static const int hid1_74xx_multipliers_x_10[] = { - 115, /* 00000 - 11.5x */ - 170, /* 00001 - 17x */ - 75, /* 00010 - 7.5x */ - 150, /* 00011 - 15x */ - 70, /* 00100 - 7x */ - 180, /* 00101 - 18x */ - 10, /* 00110 - bypass */ - 200, /* 00111 - 20x */ - 20, /* 01000 - 2x */ - 210, /* 01001 - 21x */ - 65, /* 01010 - 6.5x */ - 130, /* 01011 - 13x */ - 85, /* 01100 - 8.5x */ - 240, /* 01101 - 24x */ - 95, /* 01110 - 9.5x */ - 90, /* 01111 - 9x */ - 30, /* 10000 - 3x */ - 105, /* 10001 - 10.5x */ - 55, /* 10010 - 5.5x */ - 110, /* 10011 - 11x */ - 40, /* 10100 - 4x */ - 100, /* 10101 - 10x */ - 50, /* 10110 - 5x */ - 120, /* 10111 - 12x */ - 80, /* 11000 - 8x */ - 140, /* 11001 - 14x */ - 60, /* 11010 - 6x */ - 160, /* 11011 - 16x */ - 135, /* 11100 - 13.5x */ - 280, /* 11101 - 28x */ - 0, /* 11110 - off */ - 125 /* 11111 - 12.5x */ -}; - -static const int hid1_fx_multipliers_x_10[] = { - 00, /* 0000 - off */ - 00, /* 0001 - off */ - 10, /* 0010 - bypass */ - 10, /* 0011 - bypass */ - 20, /* 0100 - 2x */ - 25, /* 0101 - 2.5x */ - 30, /* 0110 - 3x */ - 35, /* 0111 - 3.5x */ - 40, /* 1000 - 4x */ - 45, /* 1001 - 4.5x */ - 50, /* 1010 - 5x */ - 55, /* 1011 - 5.5x */ - 60, /* 1100 - 6x */ - 65, /* 1101 - 6.5x */ - 70, /* 1110 - 7x */ - 75, /* 1111 - 7.5 */ - 80, /* 10000 - 8x */ - 85, /* 10001 - 8.5x */ - 90, /* 10010 - 9x */ - 95, /* 10011 - 9.5x */ - 100, /* 10100 - 10x */ - 110, /* 10101 - 11x */ - 120, /* 10110 - 12x */ -}; - - -/* ------------------------------------------------------------------------- */ - -/* - * Measure CPU clock speed (core clock GCLK1, GCLK2) - * - * (Approx. GCLK frequency in Hz) - */ - -int get_clocks (void) -{ - ulong clock = 0; - -#ifdef CONFIG_SYS_BUS_CLK - gd->bus_clk = CONFIG_SYS_BUS_CLK; /* bus clock is a fixed frequency */ -#else - gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */ -#endif - - /* calculate the clock frequency based upon the CPU type */ - switch (get_cpu_type()) { - case CPU_7447A: - case CPU_7448: - case CPU_7455: - case CPU_7457: - /* - * Make sure division is done before multiplication to prevent 32-bit - * arithmetic overflows which will cause a negative number - */ - clock = (gd->bus_clk / 10) * - hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; - break; - - case CPU_750GX: - case CPU_750FX: - clock = (gd->bus_clk / 10) * - hid1_fx_multipliers_x_10[get_hid1 () >> 27]; - break; - - case CPU_7450: - case CPU_740: - case CPU_740P: - case CPU_745: - case CPU_750CX: - case CPU_750: - case CPU_750P: - case CPU_755: - case CPU_7400: - case CPU_7410: - /* - * Make sure division is done before multiplication to prevent 32-bit - * arithmetic overflows which will cause a negative number - */ - clock = (gd->bus_clk / 10) * - hid1_multipliers_x_10[get_hid1 () >> 28]; - break; - - case CPU_UNKNOWN: - printf ("get_gclk_freq(): unknown CPU type\n"); - clock = 0; - return (1); - } - - gd->cpu_clk = clock; - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S deleted file mode 100644 index 8393781..0000000 --- a/arch/powerpc/cpu/74xx_7xx/start.S +++ /dev/null @@ -1,829 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> - * Copyright (C) 2001 Josh Huber <huber@mclx.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0xfff00100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - */ -#include <asm-offsets.h> -#include <config.h> -#include <74xx_7xx.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> -#include <asm/u-boot.h> - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_ME | MSR_RI ) - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - b boot_cold - - /* the boot code is located below the exception table */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* - * On the MPC8xx, this is a software emulation interrupt. It - * occurs for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x2000 - -boot_cold: - /* disable everything */ - li r0, 0 - mtspr HID0, r0 - sync - mtmsr 0 - bl invalidate_bats - sync - -#ifdef CONFIG_SYS_L2 - /* init the L2 cache */ - addis r3, r0, L2_INIT@h - ori r3, r3, L2_INIT@l - sync - mtspr l2cr, r3 -#endif -#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx) - .long 0x7e00066c - /* - * dssall instruction, gas doesn't have it yet - * ...for altivec, data stream stop all this probably - * isn't needed unless we warm (software) reboot U-Boot - */ -#endif - -#ifdef CONFIG_SYS_L2 - /* invalidate the L2 cache */ - bl l2cache_invalidate - sync -#endif -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* do early init */ - bl board_asm_init -#endif - - /* - * Calculate absolute address in FLASH and jump there - *------------------------------------------------------*/ - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*------------------------------------------------------*/ - - /* perform low-level init */ - /* sdram init, galileo init, etc */ - /* r3: NHR bit from HID0 */ - - /* setup the bats */ - bl setup_bats - sync - - /* - * Cache must be enabled here for stack-in-cache trick. - * This means we need to enable the BATS. - * This means: - * 1) for the EVB, original gt regs need to be mapped - * 2) need to have an IBAT for the 0xf region, - * we are running there! - * Cache should be turned on after BATs, since by default - * everything is write-through. - * The init-mem BAT can be reused after reloc. The old - * gt-regs BAT can be reused after board_init_f calls - * board_early_init_f (EVB only). - */ -#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx) - /* enable address translation */ - bl enable_addr_trans - sync - - /* enable and invalidate the data cache */ - bl l1dcache_enable - sync -#endif -#ifdef CONFIG_SYS_INIT_RAM_LOCK - bl lock_ram_in_cache - sync -#endif - - /* set up the stack pointer in our newly created - * cache-ram (r1) */ - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - GET_GOT /* initialize GOT access */ - - /* run low-level CPU init code (from Flash) */ - bl cpu_init_f - sync - - /* run 1st part of board init code (from Flash) */ - bl board_init_f - sync - - /* NOTREACHED - board_init_f() does not return */ - - .globl invalidate_bats -invalidate_bats: - /* invalidate BATs */ - mtspr IBAT0U, r0 - mtspr IBAT1U, r0 - mtspr IBAT2U, r0 - mtspr IBAT3U, r0 -#ifdef CONFIG_HIGH_BATS - mtspr IBAT4U, r0 - mtspr IBAT5U, r0 - mtspr IBAT6U, r0 - mtspr IBAT7U, r0 -#endif - isync - mtspr DBAT0U, r0 - mtspr DBAT1U, r0 - mtspr DBAT2U, r0 - mtspr DBAT3U, r0 -#ifdef CONFIG_HIGH_BATS - mtspr DBAT4U, r0 - mtspr DBAT5U, r0 - mtspr DBAT6U, r0 - mtspr DBAT7U, r0 -#endif - isync - sync - blr - - /* setup_bats - set them up to some initial state */ - .globl setup_bats -setup_bats: - addis r0, r0, 0x0000 - - /* IBAT 0 */ - addis r4, r0, CONFIG_SYS_IBAT0L@h - ori r4, r4, CONFIG_SYS_IBAT0L@l - addis r3, r0, CONFIG_SYS_IBAT0U@h - ori r3, r3, CONFIG_SYS_IBAT0U@l - mtspr IBAT0L, r4 - mtspr IBAT0U, r3 - isync - - /* DBAT 0 */ - addis r4, r0, CONFIG_SYS_DBAT0L@h - ori r4, r4, CONFIG_SYS_DBAT0L@l - addis r3, r0, CONFIG_SYS_DBAT0U@h - ori r3, r3, CONFIG_SYS_DBAT0U@l - mtspr DBAT0L, r4 - mtspr DBAT0U, r3 - isync - - /* IBAT 1 */ - addis r4, r0, CONFIG_SYS_IBAT1L@h - ori r4, r4, CONFIG_SYS_IBAT1L@l - addis r3, r0, CONFIG_SYS_IBAT1U@h - ori r3, r3, CONFIG_SYS_IBAT1U@l - mtspr IBAT1L, r4 - mtspr IBAT1U, r3 - isync - - /* DBAT 1 */ - addis r4, r0, CONFIG_SYS_DBAT1L@h - ori r4, r4, CONFIG_SYS_DBAT1L@l - addis r3, r0, CONFIG_SYS_DBAT1U@h - ori r3, r3, CONFIG_SYS_DBAT1U@l - mtspr DBAT1L, r4 - mtspr DBAT1U, r3 - isync - - /* IBAT 2 */ - addis r4, r0, CONFIG_SYS_IBAT2L@h - ori r4, r4, CONFIG_SYS_IBAT2L@l - addis r3, r0, CONFIG_SYS_IBAT2U@h - ori r3, r3, CONFIG_SYS_IBAT2U@l - mtspr IBAT2L, r4 - mtspr IBAT2U, r3 - isync - - /* DBAT 2 */ - addis r4, r0, CONFIG_SYS_DBAT2L@h - ori r4, r4, CONFIG_SYS_DBAT2L@l - addis r3, r0, CONFIG_SYS_DBAT2U@h - ori r3, r3, CONFIG_SYS_DBAT2U@l - mtspr DBAT2L, r4 - mtspr DBAT2U, r3 - isync - - /* IBAT 3 */ - addis r4, r0, CONFIG_SYS_IBAT3L@h - ori r4, r4, CONFIG_SYS_IBAT3L@l - addis r3, r0, CONFIG_SYS_IBAT3U@h - ori r3, r3, CONFIG_SYS_IBAT3U@l - mtspr IBAT3L, r4 - mtspr IBAT3U, r3 - isync - - /* DBAT 3 */ - addis r4, r0, CONFIG_SYS_DBAT3L@h - ori r4, r4, CONFIG_SYS_DBAT3L@l - addis r3, r0, CONFIG_SYS_DBAT3U@h - ori r3, r3, CONFIG_SYS_DBAT3U@l - mtspr DBAT3L, r4 - mtspr DBAT3U, r3 - isync - -#ifdef CONFIG_HIGH_BATS - /* IBAT 4 */ - addis r4, r0, CONFIG_SYS_IBAT4L@h - ori r4, r4, CONFIG_SYS_IBAT4L@l - addis r3, r0, CONFIG_SYS_IBAT4U@h - ori r3, r3, CONFIG_SYS_IBAT4U@l - mtspr IBAT4L, r4 - mtspr IBAT4U, r3 - isync - - /* DBAT 4 */ - addis r4, r0, CONFIG_SYS_DBAT4L@h - ori r4, r4, CONFIG_SYS_DBAT4L@l - addis r3, r0, CONFIG_SYS_DBAT4U@h - ori r3, r3, CONFIG_SYS_DBAT4U@l - mtspr DBAT4L, r4 - mtspr DBAT4U, r3 - isync - - /* IBAT 5 */ - addis r4, r0, CONFIG_SYS_IBAT5L@h - ori r4, r4, CONFIG_SYS_IBAT5L@l - addis r3, r0, CONFIG_SYS_IBAT5U@h - ori r3, r3, CONFIG_SYS_IBAT5U@l - mtspr IBAT5L, r4 - mtspr IBAT5U, r3 - isync - - /* DBAT 5 */ - addis r4, r0, CONFIG_SYS_DBAT5L@h - ori r4, r4, CONFIG_SYS_DBAT5L@l - addis r3, r0, CONFIG_SYS_DBAT5U@h - ori r3, r3, CONFIG_SYS_DBAT5U@l - mtspr DBAT5L, r4 - mtspr DBAT5U, r3 - isync - - /* IBAT 6 */ - addis r4, r0, CONFIG_SYS_IBAT6L@h - ori r4, r4, CONFIG_SYS_IBAT6L@l - addis r3, r0, CONFIG_SYS_IBAT6U@h - ori r3, r3, CONFIG_SYS_IBAT6U@l - mtspr IBAT6L, r4 - mtspr IBAT6U, r3 - isync - - /* DBAT 6 */ - addis r4, r0, CONFIG_SYS_DBAT6L@h - ori r4, r4, CONFIG_SYS_DBAT6L@l - addis r3, r0, CONFIG_SYS_DBAT6U@h - ori r3, r3, CONFIG_SYS_DBAT6U@l - mtspr DBAT6L, r4 - mtspr DBAT6U, r3 - isync - - /* IBAT 7 */ - addis r4, r0, CONFIG_SYS_IBAT7L@h - ori r4, r4, CONFIG_SYS_IBAT7L@l - addis r3, r0, CONFIG_SYS_IBAT7U@h - ori r3, r3, CONFIG_SYS_IBAT7U@l - mtspr IBAT7L, r4 - mtspr IBAT7U, r3 - isync - - /* DBAT 7 */ - addis r4, r0, CONFIG_SYS_DBAT7L@h - ori r4, r4, CONFIG_SYS_DBAT7L@l - addis r3, r0, CONFIG_SYS_DBAT7U@h - ori r3, r3, CONFIG_SYS_DBAT7U@l - mtspr DBAT7L, r4 - mtspr DBAT7U, r3 - isync -#endif - - /* bats are done, now invalidate the TLBs */ - - addis r3, 0, 0x0000 - addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ - - isync - -tlblp: - tlbie r3 - sync - addi r3, r3, 0x1000 - cmp 0, 0, r3, r5 - blt tlblp - - blr - - .globl enable_addr_trans -enable_addr_trans: - /* enable address translation */ - mfmsr r5 - ori r5, r5, (MSR_IR | MSR_DR) - mtmsr r5 - isync - blr - - .globl disable_addr_trans -disable_addr_trans: - /* disable address translation */ - mflr r4 - mfmsr r3 - andi. r0, r3, (MSR_IR | MSR_DR) - beqlr - andc r3, r3, r0 - mtspr SRR0, r4 - mtspr SRR1, r3 - rfi - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - - .globl dc_read -dc_read: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*-----------------------------------------------------------------------*/ -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ -#ifdef CONFIG_ECC - bl board_relocate_rom - sync - mr r3, r10 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ -#else - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b -#endif -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: -#ifdef CONFIG_ECC - bl board_init_ecc -#endif - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -/* clear_bss: */ - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - mr r3, r10 /* Destination Address */ -#if defined(CONFIG_PPMC7XX) - mr r4, r9 /* Use RAM copy of the global data */ -#endif - bl after_reloc - - /* not reached - end relocate_code */ -/*-----------------------------------------------------------------------*/ - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - /* enable execptions from RAM vectors */ - mfmsr r7 - li r8,MSR_IP - andc r7,r7,r8 - mtmsr r7 - - mtlr r4 /* restore link register */ - blr - -#ifdef CONFIG_SYS_INIT_RAM_LOCK -lock_ram_in_cache: - /* Allocate Initial RAM in data cache. - */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r4 -1: - dcbz r0, r3 - addi r3, r3, 32 - bdnz 1b - - /* Lock the data cache */ - mfspr r0, HID0 - ori r0, r0, 0x1000 - sync - mtspr HID0, r0 - sync - blr - -.globl unlock_ram_in_cache -unlock_ram_in_cache: - /* invalidate the INIT_RAM section */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r4 -1: icbi r0, r3 - addi r3, r3, 32 - bdnz 1b - sync /* Wait for all icbi to complete on bus */ - isync - - /* Unlock the data cache and invalidate it */ - mfspr r0, HID0 - li r3,0x1000 - andc r0,r0,r3 - li r3,0x0400 - or r0,r0,r3 - sync - mtspr HID0, r0 - sync - blr -#endif diff --git a/arch/powerpc/cpu/74xx_7xx/traps.c b/arch/powerpc/cpu/74xx_7xx/traps.c deleted file mode 100644 index 111c86c..0000000 --- a/arch/powerpc/cpu/74xx_7xx/traps.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include <common.h> -#include <command.h> -#include <kgdb.h> -#include <asm/processor.h> - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS:" - " %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP:" - " %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ - unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; - int i, j; - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - - p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0); - p -= 32; - for (i = 0; i < 256; i+=16) { - printf("%08x: ", (unsigned int)p+i); - for (j = 0; j < 16; j++) { - printf("%02x ", p[i+j]); - } - printf("\n"); - } - - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds deleted file mode 100644 index c099849..0000000 --- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2010 Wolfgang Denk <wd@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - .text : - { - arch/powerpc/cpu/74xx_7xx/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 4430477..c57d9c0 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -100,9 +100,6 @@ struct arch_global_data { #if defined(CONFIG_4xx) u32 uart_clk; #endif /* CONFIG_4xx */ -#if defined(CONFIG_SYS_GT_6426x) - unsigned int mirror_hack[16]; -#endif #ifdef CONFIG_SYS_FPGA_COUNT unsigned fpga_state[CONFIG_SYS_FPGA_COUNT]; #endif diff --git a/board/eltec/elppc/Kconfig b/board/eltec/elppc/Kconfig deleted file mode 100644 index d4003e5..0000000 --- a/board/eltec/elppc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ELPPC - -config SYS_BOARD - default "elppc" - -config SYS_VENDOR - default "eltec" - -config SYS_CONFIG_NAME - default "ELPPC" - -endif diff --git a/board/eltec/elppc/MAINTAINERS b/board/eltec/elppc/MAINTAINERS deleted file mode 100644 index e3b35f1..0000000 --- a/board/eltec/elppc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ELPPC BOARD -#M: - -S: Maintained -F: board/eltec/elppc/ -F: include/configs/ELPPC.h -F: configs/ELPPC_defconfig diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile deleted file mode 100644 index 791f2fb..0000000 --- a/board/eltec/elppc/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = elppc.o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o -obj-y += asm_init.o diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S deleted file mode 100644 index 10fdfa2..0000000 --- a/board/eltec/elppc/asm_init.S +++ /dev/null @@ -1,862 +0,0 @@ -/* - * (C) Copyright 2001 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * ELTEC ELPPC RAM initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <asm/processor.h> -#include <version.h> -#include <mpc106.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -.globl board_asm_init -board_asm_init: - -/* - * setup pointer to message block - */ - mflr r13 /* save away link register */ - bl get_lnk_reg /* r3=addr of next instruction */ - subi r4, r3, 8 /* r4=board_asm_init addr */ - addi r29, r4, (MessageBlock-board_asm_init) - -/* - * dcache_disable - */ - mfspr r3, HID0 - li r4, HID0_DCE - andc r3, r3, r4 - mr r2, r3 - ori r3, r3, HID0_DCI - sync - mtspr HID0, r3 - mtspr HID0, r2 - isync - sync -/* - * icache_disable - */ - mfspr r3, HID0 - li r4, 0 - ori r4, r4, HID0_ICE - andc r3, r3, r4 - sync - mtspr HID0, r3 -/* - * invalidate caches - */ - ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE) - or r4, r4, r3 - isync - mtspr HID0, r4 - andc r4, r4, r3 - isync - mtspr HID0, r4 - isync -/* - * icache_enable - */ - mfspr r3, HID0 - ori r3, r3, (HID0_ICE | HID0_ICFI) - sync - mtspr HID0, r3 - - -/* - * setup memory controller - */ - lis r1, MPC106_REG_ADDR@h - ori r1, r1, MPC106_REG_ADDR@l - lis r2, MPC106_REG_DATA@h - ori r2, r2, MPC106_REG_DATA@l - - /* Configure PICR1 */ - lis r3, MPC106_REG@h - ori r3, r3, PCI_PICR1 - stwbrx r3, 0, r1 - addis r3, r0, 0xFF14 - ori r3, r3, 0x1CC8 - eieio - stwbrx r3, 0, r2 - - /* Configure PICR2 */ - lis r3, MPC106_REG@h - ori r3, r3, PCI_PICR2 - stwbrx r3, 0, r1 - addis r3, r0, 0x0000 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure EUMBAR */ - lis r3, MPC106_REG@h - ori r3, r3, 0x0078 /* offest of EUMBAR in PCI config space */ - stwbrx r3, 0, r1 - lis r3, MPC107_EUMB_ADDR@h - eieio - stwbrx r3, 0, r2 - - /* Configure Address Map B Option Reg */ - lis r3, MPC106_REG@h - ori r3, r3, 0x00e0 /* offest of AMBOR in PCI config space */ - stwbrx r3, 0, r1 - lis r3, 0 - eieio - stwbrx r3, 0, r2 - - /* Configure I2C Controller */ - lis r14, MPC107_I2C_ADDR@h /* base of I2C controller */ - ori r14, r14, MPC107_I2C_ADDR@l - lis r3, 0x2b10 /* I2C clock = 100MHz/1024 */ - stw r3, 4(r14) - li r3, 0 /* clear arbitration */ - eieio - stw r3, 12(r14) - - /* Configure MCCR1 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR1 - stwbrx r3, 0, r1 - addis r3, r0, 0x0660 /* don't set MEMGO now ! */ - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure MCCR2 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR2 - stwbrx r3, 0, r1 - addis r3, r0, 0x0400 - ori r3, r3, 0x1800 - eieio - stwbrx r3, 0, r2 - - - /* Configure MCCR3 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR3 - stwbrx r3, 0, r1 - addis r3, r0, 0x0230 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure MCCR4 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR4 - stwbrx r3, 0, r1 - addis r3, r0, 0x2532 - ori r3, r3, 0x2220 - eieio - stwbrx r3, 0, r2 - -/* - * configure memory interface (MICRs) - */ - addis r3, r0, 0x8000 /* ADDR_80 */ - ori r3, r3, 0x0080 /* SMEMADD1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0x4000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_84 */ - ori r3, r3, 0x0084 /* SMEMADD2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0xFFFF - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_88 */ - ori r3, r3, 0x0088 /* EXTSMEM1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_8C */ - ori r3, r3, 0x008c /* EXTSMEM2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0303 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_90 */ - ori r3, r3, 0x0090 /* EMEMADD1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0x7F3F - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_94 */ - ori r3, r3, 0x0094 /* EMEMADD2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0xFFFF - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_98 */ - ori r3, r3, 0x0098 /* EXTEMEM1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_9C */ - ori r3, r3, 0x009c /* EXTEMEM2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0303 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_A0 */ - ori r3, r3, 0x00a0 /* MEMBNKEN */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0000 - ori r3, r3, 0x0003 - eieio - stwbrx r3, 0, r2 - -/* - * must wait at least 100us after HRESET to issue a MEMGO - */ - lis r0, 1 - mtctr r0 -memStartWait: - bdnz memStartWait - -/* - * enable RAM Operations through MCCR1 (MEMGO) - */ - lis r3, 0x8000 - ori r3, r3, 0x00f0 - stwbrx r3, r0, r1 - sync - lwbrx r3, 0, r2 - lis r0, 0x0008 - or r3, r0, r3 - stwbrx r3, 0, r2 - sync - -/* - * set LEDs first time - */ - li r3, 0x1 - lis r30, CONFIG_SYS_USR_LED_BASE@h - stb r3, 2(r30) - sync - -/* - * init COM1 for polled output - */ - lis r8, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r8, r8, CONFIG_SYS_NS16550_COM1@l - li r9, 0x00 - stb r9, 1(r8) /* int disabled */ - eieio - li r9, 0x00 - stb r9, 4(r8) /* modem ctrl */ - eieio - li r9, 0x80 - stb r9, 3(r8) /* link ctrl */ - eieio - li r9, (CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) - stb r9, 0(r8) /* baud rate (LSB)*/ - eieio - li r9, ((CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8) - stb r9, 1(r8) /* baud rate (MSB) */ - eieio - li r9, 0x07 - stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ - eieio - li r9, 0x0b - stb r9, 4(r8) /* enable the receiver and transmitter (modem ctrl) */ - eieio -waitEmpty: - lbz r9, 5(r8) /* transmit empty */ - andi. r9, r9, 0x40 - beq waitEmpty - li r9, 0x47 - stb r9, 3(r8) /* send break, 8 data bits, 2 stop bit, no parity */ - eieio - - lis r0, 0x0001 - mtctr r0 -waitCOM1: - lwz r0, 5(r8) /* load from port for delay */ - bdnz waitCOM1 - -waitEmpty1: - lbz r9, 5(r8) /* transmit empty */ - andi. r9, r9, 0x40 - beq waitEmpty1 - li r9, 0x07 - stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ - eieio - -/* - * intro message from message block - */ - addi r3, r29, (MnewLine-MessageBlock) - bl Printf - addi r3, r29, (MinitLogo-MessageBlock) - bl Printf - -/* - * memory cofiguration using SPD information stored on the SODIMMs - */ - addi r3, r29, (Mspd01-MessageBlock) - bl Printf - - li r17, 0 - - li r3, 0x0002 /* get RAM type from spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, -1 /* error ? */ - bne noSpdError - - addi r3, r29, (Mfail-MessageBlock) - bl Printf - - li r6, 0xe /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -noSpdError: - mr r15, r3 /* save r3 */ - - addi r3, r29, (Mok-MessageBlock) - bl Printf - - cmpli 0, 0, r15, 0x0004 /* SDRAM ? */ - beq isSDRAM - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xd /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -isSDRAM: - li r3, 0x0012 /* get supported CAS latencies from byte 18 */ - bl spdRead - mr r15, r3 - li r3, 0x09 - andi. r0, r15, 0x04 - bne maxCLis3 - li r3, 0x17 -maxCLis3: - andi. r0, r15, 0x02 - bne CL2 - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xc /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ -CL2: - bl spdRead - cmpli 0, 0, r3, 0xa1 /* cycle time must be 10ns max. */ - blt speedOk - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xb /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ -speedOk: - lis r20, 0x06e8 /* preset MCR1 value */ - - li r3, 0x0011 /* get number of internal banks from spd for bank0/1 */ - bl spdRead - - cmpli 0, 0, r3, 0x02 - beq SD_2B - cmpli 0, 0, r3, 0x04 - beq SD_4B -memConfErr: - addi r3, r29, (MramConfErr-MessageBlock) - bl Printf - - li r6, 0xa /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -SD_2B: - li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ - bl spdRead - cmpli 0, 0, r3, 0x0b - beq row11x2 - cmpli 0, 0, r3, 0x0c - beq row12x2or13x2 - cmpli 0, 0, r3, 0x0d - beq row12x2or13x2 - b memConfErr -SD_4B: - li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ - bl spdRead - cmpli 0, 0, r3, 0x0b - beq row11x4or12x4 - cmpli 0, 0, r3, 0x0c - beq row11x4or12x4 - cmpli 0, 0, r3, 0x0d - beq row13x4 - b memConfErr -row12x2or13x2: - ori r20, r20, 0x05 - b row11x4or12x4 -row13x4: - ori r20, r20, 0x0a - b row11x4or12x4 -row11x2: - ori r20, r20, 0x0f -row11x4or12x4: - /* get the size of bank 0-1 */ - - li r3, 0x001f /* get bank size from spd for bank0/1 */ - bl spdRead - - rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte (128 MB max.) */ - - li r3, 0x0005 /* get number of banks from spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, 2 /* 2 banks ? */ - bne SDRAMnobank1 - - mr r17, r16 - -SDRAMnobank1: - li r3, 0x000c /* get refresh from spd for bank0/1 */ - bl spdRead - andi. r3, r3, 0x007f /* mask selfrefresh bit */ - li r4, 0x1800 /* refesh cycle 1536 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */ - beq writeRefresh - - li r4, 0x0c00 /* refesh cycle 768 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */ - beq writeRefresh - - li r4, 0x3000 /* refesh cycle 3072 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */ - beq writeRefresh - - li r4, 0x6000 /* refesh cycle 6144 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */ - beq writeRefresh - - li r4, 0 - ori r4, r4, 0xc000 /* refesh cycle 8224 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0005 /* 125 us ? */ - beq writeRefresh - - b memConfErr - -writeRefresh: - lis r21, 0x0400 /* preset MCCR2 value */ - or r21, r21, r4 - - /* Overwrite MCCR1 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR1 - stwbrx r3, 0, r1 - eieio - stwbrx r20, 0, r2 - - /* Overwrite MCCR2 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR2 - stwbrx r3, 0, r1 - eieio - stwbrx r21, 0, r2 - - /* set the memory boundary registers for bank 0-3 */ - li r20, 0 - lis r23, 0x0303 - lis r24, 0x0303 - subi r21, r16, 1 /* calculate end address bank0 */ - li r22, 1 - - cmpi 0, 0, r17, 0 /* bank1 present ? */ - beq nobank1 - - andi. r3, r16, 0x00ff /* calculate start address of bank1 */ - andi. r4, r16, 0x0300 - rlwinm r3, r3, 8, 16, 23 - or r20, r20, r3 - or r23, r23, r4 - - add r16, r16, r17 /* add to total memory size */ - - subi r3, r16, 1 /* calculate end address of bank1 */ - andi. r4, r3, 0x0300 - andi. r3, r3, 0x00ff - rlwinm r3, r3, 8, 16, 23 - or r21, r21, r3 - or r24, r24, r4 - - ori r22, r22, 2 /* enable bank1 */ - b bankOk -nobank1: - ori r23, r23, 0x0300 /* set bank1 start to unused area */ - ori r24, r24, 0x0300 /* set bank1 end to unused area */ -bankOk: - addi r3, r29, (Mactivate-MessageBlock) - bl Printf - mr r3, r16 - bl OutDec - addi r3, r29, (Mact0123e-MessageBlock) - bl Printf - -/* - * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1 - */ - addis r3, r0, 0x8000 /* ADDR_80 */ - ori r3, r3, 0x0080 /* MSAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r20, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_88 */ - ori r3, r3, 0x0088 /* EMSAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r23, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_90 */ - ori r3, r3, 0x0090 /* MEAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r21, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_98 */ - ori r3, r3, 0x0098 /* EMEAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r24, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_A0 */ - ori r3, r3, 0x00a0 /* MBER */ - stwbrx r3, 0, r1 - eieio - stwbrx r22, 0, r2 - -/* - * delay to let SDRAM go through several initialization/refresh cycles - */ - lis r3, 3 - mtctr r3 -memStartWait_1: - bdnz memStartWait_1 - eieio - -/* - * set LEDs end - */ - li r3, 0xf - lis r30, CONFIG_SYS_USR_LED_BASE@h - stb r3, 2(r30) - sync - - mtlr r13 - blr /* EXIT board_asm_init ... */ - -/*----------------------------------------------------------------------------*/ -/* - * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string) - */ - -Printf: - lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CONFIG_SYS_NS16550_COM1@l -WaitChr: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, WaitChr /* wait till empty */ - lbzx r0, r0, r3 /* get char */ - stb r0, 0(r10) /* write to transmit reg */ - eieio - addi r3, r3, 1 /* next char */ - lbzx r0, r0, r3 /* get char */ - cmpwi cr1, r0, 0 /* end of string ? */ - bne cr1, WaitChr - blr - -/* - * print a char to COM1 in polling mode (r10=COM1 port, r3=char) - */ -OutChr: - lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CONFIG_SYS_NS16550_COM1@l -OutChr1: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutChr1 /* wait till empty */ - stb r3, 0(r10) /* write to transmit reg */ - eieio - blr - -/* - * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val) - */ -OutHex2: - li r9, 4 /* shift reg for 2 digits */ - b OHstart -OutHex4: - li r9, 12 /* shift reg for 4 digits */ - b OHstart -OutHex: - li r9, 28 /* shift reg for 8 digits */ -OHstart: - lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CONFIG_SYS_NS16550_COM1@l -OutDig: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDig - sraw r0, r3, r9 - clrlwi r0, r0, 28 - cmpwi cr1, r0, 9 - ble cr1, digIsNum - addic r0, r0, 55 - b nextDig -digIsNum: - addic r0, r0, 48 -nextDig: - stb r0, 0(r10) /* write to transmit reg */ - eieio - addic. r9, r9, -4 - bge OutDig - blr - -/* - * print 3 digits hdec value to COM1 in polling mode - * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch) - */ -OutDec: - li r6, 10 - divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */ - mullw r10, r0, r6 - subf r9, r10, r3 - mr r3, r0 - divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */ - mullw r10, r0, r6 - subf r8, r10, r3 - mr r3, r0 - divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */ - mullw r10, r0, r6 - subf r7, r10, r3 - lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CONFIG_SYS_NS16550_COM1@l - or. r7, r7, r7 - bne noblank1 - li r3, 0x20 - b OutDec4 -noblank1: - addi r3, r7, 48 /* convert to ASCII */ -OutDec4: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec4 - stb r3, 0(r10) /* x00 to transmit */ - eieio - or. r7, r7, r8 - beq OutDec5 - addi r3, r8, 48 /* convert to ASCII */ -OutDec5: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec5 - stb r3, 0(r10) /* x0 to transmit */ - eieio - addi r3, r9, 48 /* convert to ASCII */ -OutDec6: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec6 - stb r3, 0(r10) /* x to transmit */ - eieio - blr - -/* - * hang endless loop - */ -toggleError: /* fail type in r6, r7=0xff, toggle LEDs */ - stb r7, 2(r30) /* r7 to LED */ - li r0, 0 - lis r9, 127 - ori r9, r9, 65535 -toggleError1: - addic r0, r0, 1 - cmpw cr1, r0, r9 - ble cr1, toggleError1 - stb r6, 2(r30) /* r6 to LED */ - li r0, 0 - lis r9, 127 - ori r9, r9, 65535 -toggleError2: - addic r0, r0, 1 - cmpw cr1, r0, r9 - ble cr1, toggleError2 - b toggleError - -/* - * routines to read from ram spd - */ -spdWaitIdle: - lis r0, 0x1 /* timeout for about 100us */ - mtctr r0 -iSpd: - lbz r10, 12(r14) - andi. r10, r10, 0x20 /* mask and test MBB */ - beq idle - bdnz iSpd - orc. r10, r0, r0 /* return -1 to caller */ -idle: - bclr 20, 0 /* return to caller */ - -waitSpd: - lis r0, 0x10 /* timeout for about 1.5ms */ - mtctr r0 -wSpd: - lbz r10, 12(r14) - andi. r10, r10, 0x82 - cmpli 0, 0, r10, 0x82 /* test MCF and MIF set */ - beq wend - bdnz wSpd - orc. r10, r0, r0 /* return -1 to caller */ - bclr 20, 0 /* return to caller */ - -wend: - li r10, 0 - stb r10, 12(r14) /* clear status */ - bclr 20, 0 /* return to caller */ - -/* - * spdread - * in: r3 adr to read - * out: r3 val or -1 for error - * uses r10, assumes that r14 points to I2C controller - */ -spdRead: - mfspr r25, 8 /* save link register */ - - bl spdWaitIdle - bne spdErr - - li r10, 0x80 /* start with MEN */ - stb r10, 8(r14) - eieio - - li r10, 0xb0 /* start as master */ - stb r10, 8(r14) - eieio - - li r10, 0xa0 /* write device 0xA0 */ - stb r10, 16(r14) - eieio - bl waitSpd - bne spdErr - - lbz r10, 12(r14) /* test ACK */ - andi. r10, r10, 0x01 - bne gotNoAck - - stb r3, 16(r14) /* data address */ - eieio - bl waitSpd - bne spdErr - - - li r10, 0xb4 /* switch to read - restart */ - stb r10, 8(r14) - eieio - - li r10, 0xa1 /* read device 0xA0 */ - stb r10, 16(r14) - eieio - bl waitSpd - bne spdErr - - li r10, 0xa8 /* no ACK */ - stb r10, 8(r14) - eieio - - lbz r10, 16(r14) /* trigger read next byte */ - eieio - bl waitSpd - bne spdErr - - li r10, 0x88 /* generate STOP condition */ - stb r10, 8(r14) - eieio - - lbz r3, 16(r14) /* return read byte */ - - mtspr 8, r25 /* restore link register */ - blr - -gotNoAck: - li r10, 0x80 /* generate STOP condition */ - stb r10, 8(r14) - eieio -spdErr: - orc r3, r0, r0 /* return -1 */ - mtspr 8, r25 /* restore link register */ - blr - -get_lnk_reg: - mflr r3 /* return link reg */ - blr - -MessageBlock: - -MinitLogo: - .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012" - .ascii "\015\012Initialising RAM\015\012\000" -Mspd01: - .ascii " Reading SPD of SODIMM ...... \000" -MramTyp: - .ascii "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000" -MramConfErr: - .ascii "\015\012\Unsupported SODIMM Configuration!\015\012\000" -Mactivate: - .ascii " Activating \000" -Mact0123e: - .ascii " MByte.\015\012\000" -Mok: - .ascii "OK \015\012\000" -Mfail: - .ascii "FAILED \015\012\000" -MnewLine: - .ascii "\015\012\000" - .align 4 diff --git a/board/eltec/elppc/eepro100_srom.c b/board/eltec/elppc/eepro100_srom.c deleted file mode 100644 index 05ba9c4..0000000 --- a/board/eltec/elppc/eepro100_srom.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Local network srom writing for first time run - */ - -/* includes */ -#include <common.h> -#include <pci.h> -#include <net.h> -#include "srom.h" - -extern int eepro100_write_eeprom (struct eth_device *dev, - int location, int addr_len, - unsigned short data); - -/*----------------------------------------------------------------------------*/ - -unsigned short eepro100_srom_checksum (unsigned short *sromdata) -{ - unsigned short sum = 0; - unsigned int i; - - for (i = 0; i < (EE_SIZE - 1); i++) { - sum += sromdata[i]; - } - return (EE_CHECKSUM - sum); -} - -/*----------------------------------------------------------------------------*/ - -int eepro100_srom_store (unsigned short *source) -{ - int count; - struct eth_device onboard_dev; - - /* get onboard network iobase */ - pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0, - (unsigned int *) &onboard_dev.iobase); - onboard_dev.iobase &= ~0xf; - - source[63] = eepro100_srom_checksum (source); - - for (count = 0; count < EE_SIZE; count++) { - if (eepro100_write_eeprom ((struct eth_device *) &onboard_dev, - count, EE_ADDR_BITS, - SROM_SHORT (source)) == -1) { - return -1; - } - source++; - } - return 0; -} - -/*----------------------------------------------------------------------------*/ - -#ifdef EEPRO100_SROM_CHECK - -extern int read_eeprom (struct eth_device *dev, int location, int addr_len); - -void eepro100_srom_load (unsigned short *destination) -{ - int count; - struct eth_device onboard_dev; - -#ifdef DEBUG - int lr = 0; - - printf ("eepro100_srom_download:\n"); -#endif - - /* get onboard network iobase */ - pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0, - &onboard_dev.iobase); - onboard_dev.iobase &= ~0xf; - - memset (destination, 0x65, 128); - - for (count = 0; count < 0x40; count++) { - *destination++ = read_eeprom ((struct eth_device *) &onboard_dev, - count, EE_ADDR_BITS); -#ifdef DEBUG - printf ("%04x ", *(destination - 1)); - if (lr++ == 7) { - printf ("\n"); - lr = 0; - } -#endif - } -} -#endif /* EEPRO100_SROM_CHECK */ - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c deleted file mode 100644 index ac814b8..0000000 --- a/board/eltec/elppc/elppc.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <mpc106.h> -#include <video_fb.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -int checkboard (void) -{ - puts ("Board: ELTEC PowerPC\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int checkflash (void) -{ - /* TODO */ - printf ("Test not implemented !\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -static unsigned int mpc106_read_cfg_dword (unsigned int reg) -{ - unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC); - - out32r (MPC106_REG_ADDR, reg_addr); - - return (in32r (MPC106_REG_DATA | (reg & 0x3))); -} - -/* ------------------------------------------------------------------------- */ - -long int dram_size (int board_type) -{ - /* - * No actual initialisation to do - done when setting up - * PICRs MCCRs ME/SARs etc in asm_init.S. - */ - - register unsigned long i, msar1, mear1, memSize; - -#if defined(CONFIG_SYS_MEMTEST) - register unsigned long reg; - - printf ("Testing DRAM\n"); - - /* write each mem addr with it's address */ - for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) - *reg = reg; - - for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) { - if (*reg != reg) - return -1; - } -#endif - - /* - * Since MPC107 memory controller chip has already been set to - * control all memory, just read and interpret its memory boundery register. - */ - memSize = 0; - msar1 = mpc106_read_cfg_dword (MPC106_MSAR1); - mear1 = mpc106_read_cfg_dword (MPC106_MEAR1); - i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf; - - do { - if (i & 0x01) /* is bank enabled ? */ - memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1; - msar1 >>= 8; - mear1 >>= 8; - i >>= 1; - } while (i); - - return (memSize * 0x100000); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - return dram_size (board_type); -} - -/* ------------------------------------------------------------------------- */ - -/* - * The BAB 911 can be reset by writing bit 0 of the Processor Initialization - * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities - * Memory Block). - */ -int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - out8 (MPC107_EUMB_PI, 1); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) - -/* - * Since the 7xx CPUs don't have an internal watchdog, this function is - * board specific. - */ -void watchdog_reset (void) -{ -} -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ - -void after_reloc (ulong dest_addr) -{ - /* - * Jump to the main U-Boot board init code - */ - board_init_r ((gd_t *)gd, dest_addr); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -extern GraphicDevice smi; - -void video_get_info_str (int line_number, char *info) -{ - /* init video info strings for graphic console */ - switch (line_number) { - case 1: - sprintf (info, " MPC7xx V%d.%d at %d / %d MHz", - (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100); - return; - case 2: - sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH", - dram_size (0) / 0x100000, flash_init () / 0x100000); - return; - case 3: - sprintf (info, " %s", smi.modeIdent); - return; - } - - /* no more info lines */ - *info = 0; - return; -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c deleted file mode 100644 index 2b41685..0000000 --- a/board/eltec/elppc/flash.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC). - * fixed monitor protection part - * - * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage - * of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use - * any other. - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/pci_io.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*flash command address offsets*/ - -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - unsigned long size1, size2; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) - { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* initialise 1st flash */ - size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) - { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size1, size1<<20); - } - - /* initialise 2nd flash */ - size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (flash_info[1].flash_id == FLASH_UNKNOWN) - { - printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size2, size2<<20); - } - - /* monitor protection ON by default */ - if (size1 == 512*1024) - { - (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM+monitor_flash_len-1, - &flash_info[0]); - } - if (size2 == 512*1024) - { - (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM, - FLASH_BASE1_PRELIM+monitor_flash_len-1, - &flash_info[1]); - } - if (size2 == 4*1024*1024) - { - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, - &flash_info[1]); - } - - return (size1 + size2); -} - -/*----------------------------------------------------------------------------*/ - -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - flash_init(); - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - case AMD_ID_F032B: - printf ("AM29F032B (32 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------------*/ -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong vendor, devid; - ulong base = (ulong)addr; - volatile unsigned char *caddr = (unsigned char *)addr; - -#ifdef DEBUG - printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr); -#endif - - /* Write auto select command: read Manufacturer ID */ - caddr[0] = 0xF0; /* reset bank */ - udelay(10); - - eieio(); - caddr[0x555] = 0xAA; - udelay(10); - caddr[0x2AA] = 0x55; - udelay(10); - caddr[0x555] = 0x90; - - udelay(10); - - vendor = caddr[0]; - devid = caddr[1]; - -#ifdef DEBUG - printf("Manufacturer: 0x%lx\n", vendor); -#endif - - vendor &= 0xff; - devid &= 0xff; - - /* We accept only two AMD types */ - switch (vendor) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (devid) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id |= AMD_ID_F040B; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F016D: - info->flash_id |= AMD_ID_F016D; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id |= AMD_ID_F032B; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#ifdef DEBUG - printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - caddr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------------*/ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - int rc = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[sect]); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ - } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return rc; -} - -/*----------------------------------------------------------------------------*/ -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------------*/ -/* Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c deleted file mode 100644 index 2acf800..0000000 --- a/board/eltec/elppc/misc.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* includes */ -#include <common.h> -#include <cli.h> -#include <linux/ctype.h> -#include <pci.h> -#include <net.h> -#include "srom.h" - -/* imports */ -extern int l2_cache_enable (int l2control); -extern int eepro100_write_eeprom (struct eth_device *dev, int location, - int addr_len, unsigned short data); -extern int read_eeprom (struct eth_device *dev, int location, int addr_len); - -/*----------------------------------------------------------------------------*/ -/* - * read/write to nvram is only byte access - */ -void *nvram_read (void *dest, const long src, size_t count) -{ - uchar *d = (uchar *) dest; - uchar *s = (uchar *) (CONFIG_ENV_MAP_ADRS + src); - - while (count--) - *d++ = *s++; - - return dest; -} - -void nvram_write (long dest, const void *src, size_t count) -{ - uchar *d = (uchar *) (CONFIG_ENV_MAP_ADRS + dest); - uchar *s = (uchar *) src; - - while (count--) - *d++ = *s++; -} - -/*----------------------------------------------------------------------------*/ -/* - * handle sroms on ELPPC - * fix ether address - * set serial console as default - */ -int misc_init_r (void) -{ - revinfo eerev; - u_char *ptr; - u_int i, l, initSrom, copyNv; - char buf[256]; - char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, - 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 - }; - - /* Clock setting for MPC107 i2c */ - mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b); - - /* Reset the EPIC */ - out32r (MPC107_EUMB_GCR, 0xa0000000); - while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */ - out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */ - while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */ - - /* - * Check/Remake revision info - */ - initSrom = 0; - copyNv = 0; - - /* read out current revision srom contens */ - mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo), - SECOND_DEVICE, FIRST_BLOCK); - - /* read out current nvram shadow image */ - nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE); - - if (strcmp (eerev.magic, "ELTEC") != 0) { - /* srom is not initialized -> create a default revision info */ - for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo); - i++) - *ptr++ = 0x00; - strcpy (eerev.magic, "ELTEC"); - eerev.revrev[0] = 1; - eerev.revrev[1] = 0; - eerev.size = 0x00E0; - eerev.category[0] = 0x01; - - /* node id from dead e128 as default */ - eerev.etheraddr[0] = 0x00; - eerev.etheraddr[1] = 0x00; - eerev.etheraddr[2] = 0x5B; - eerev.etheraddr[3] = 0x00; - eerev.etheraddr[4] = 0x2E; - eerev.etheraddr[5] = 0x4D; - - /* cache config word for ELPPC */ - memset(&eerev.res[0], 0, 4); - - initSrom = 1; /* force dialog */ - copyNv = 1; /* copy to nvram */ - } - - if ((copyNv == 0) - && (el_srom_checksum ((u_char *) & eerev, CONFIG_SYS_SROM_SIZE) != - el_srom_checksum ((u_char *) buf, CONFIG_SYS_SROM_SIZE))) { - printf ("Invalid revision info copy in nvram !\n"); - printf ("Press key:\n <c> to copy current revision info to nvram.\n"); - printf (" <r> to reenter revision info.\n"); - printf ("=> "); - if (0 != cli_readline(NULL)) { - switch ((char) toupper (console_buffer[0])) { - case 'C': - copyNv = 1; - break; - case 'R': - copyNv = 1; - initSrom = 1; - break; - } - } - } - - if (initSrom) { - memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ - printf ("Enter revision number (0-9): %c ", - eerev.revision[0][0]); - if (0 != cli_readline(NULL)) { - eerev.revision[0][0] = - (char) toupper (console_buffer[0]); - memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ - } - - printf ("Enter revision character (A-Z): %c ", - eerev.revision[0][1]); - if (1 == cli_readline(NULL)) { - eerev.revision[0][1] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter board name (V-XXXX-XXXX): %s ", - (char *) &eerev.board); - if (11 == cli_readline(NULL)) { - for (i = 0; i < 11; i++) - eerev.board[i] = - (char) toupper (console_buffer[i]); - eerev.board[11] = '\0'; - } - - printf ("Enter serial number: %s ", (char *) &eerev.serial); - if (6 == cli_readline(NULL)) { - for (i = 0; i < 6; i++) - eerev.serial[i] = console_buffer[i]; - eerev.serial[6] = '\0'; - } - - printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]); - if (12 == cli_readline(NULL)) { - for (i = 0; i < 12; i += 2) - eerev.etheraddr[i >> 1] = - (char) (16 * - hex[toupper - (console_buffer[i]) - - '0'] + - hex[toupper - (console_buffer[i + 1]) - - '0']); - } - - l = strlen ((char *) &eerev.text); - printf ("Add to text section (max 64 chr): %s ", - (char *) &eerev.text); - if (0 != cli_readline(NULL)) { - for (i = l; i < 63; i++) - eerev.text[i] = console_buffer[i - l]; - eerev.text[63] = '\0'; - } - - /* prepare network eeprom */ - memset (buf, 0, 128); - - buf[0] = eerev.etheraddr[1]; - buf[1] = eerev.etheraddr[0]; - buf[2] = eerev.etheraddr[3]; - buf[3] = eerev.etheraddr[2]; - buf[4] = eerev.etheraddr[5]; - buf[5] = eerev.etheraddr[4]; - - buf[20] = 0x48; - buf[21] = 0xB2; - - buf[22] = 0x00; - buf[23] = 0x04; - - buf[24] = 0x14; - buf[25] = 0x33; - - printf ("\nSRom: Writing i82559 info ........ "); - if (eepro100_srom_store ((unsigned short *) buf) == -1) - printf ("FAILED\n"); - else - printf ("OK\n"); - - /* update CRC */ - eerev.crc = - el_srom_checksum ((u_char *) eerev.board, eerev.size); - - /* write new values */ - printf ("\nSRom: Writing revision info ...... "); - if (mpc107_srom_store - ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev, - sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1) - printf ("FAILED\n\n"); - else - printf ("OK\n\n"); - - /* write new values as shadow image to nvram */ - nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev, - CONFIG_SYS_SROM_SIZE); - - } - - /*if (initSrom) */ - /* copy current values as shadow image to nvram */ - if (initSrom == 0 && copyNv == 1) - nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev, - CONFIG_SYS_SROM_SIZE); - - /* update environment */ - sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", - eerev.etheraddr[0], eerev.etheraddr[1], - eerev.etheraddr[2], eerev.etheraddr[3], - eerev.etheraddr[4], eerev.etheraddr[5]); - setenv ("ethaddr", buf); - - /* print actual board identification */ - printf ("Ident: %s Ser %s Rev %c%c\n", - eerev.board, (char *) &eerev.serial, - eerev.revision[0][0], eerev.revision[0][1]); - - return (0); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/mpc107_i2c.c b/board/eltec/elppc/mpc107_i2c.c deleted file mode 100644 index 4f95703..0000000 --- a/board/eltec/elppc/mpc107_i2c.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* includes */ -#include <common.h> -#include "srom.h" - -/* locals */ -static unsigned long mpc107_eumb_addr = 0; - -/*----------------------------------------------------------------------------*/ - -/* - * calculate checksum for ELTEC revision srom - */ -unsigned long el_srom_checksum (ptr, size) -register unsigned char *ptr; -unsigned long size; -{ - u_long f, accu = 0; - u_int i; - u_char byte; - - for (; size; size--) - { - byte = *ptr++; - for (i = 8; i; i--) - { - f = ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0; - accu >>= 1; accu ^= f; - byte >>= 1; - } - } - return(accu); -} - -/*----------------------------------------------------------------------------*/ - -static int mpc107_i2c_wait ( unsigned long timeout ) -{ - unsigned long x; - - while (((x = in32r(MPC107_I2CSR)) & 0x82) != 0x82) - { - if (!timeout--) - return -1; - } - - if (x & 0x10) - { - return -1; - } - out32r(MPC107_I2CSR, 0); - - return 0; -} - -/*----------------------------------------------------------------------------*/ - -static int mpc107_i2c_wait_idle ( unsigned long timeout ) -{ - while (in32r(MPC107_I2CSR) & 0x20) - { - if (!timeout--) - return -1; - } - return 0; -} - - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_read_byte ( - unsigned char device, - unsigned char block, - unsigned char offset ) -{ - unsigned long timeout = MPC107_I2C_TIMEOUT; - int data; - - if (!mpc107_eumb_addr) - return -6; - - mpc107_i2c_wait_idle (timeout); - - /* Start with MEN */ - out32r(MPC107_I2CCR, 0x80); - - /* Start as master */ - out32r(MPC107_I2CCR, 0xB0); - out32r(MPC107_I2CDR, (0xA0 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 1\n"); - return -2; - } - - if (in32r(MPC107_I2CSR)&0x1) - { - /* Generate STOP condition; device busy or not existing */ - out32r(MPC107_I2CCR, 0x80); - return -1; - } - - /* Data address */ - out32r(MPC107_I2CDR, offset); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 2\n"); - return -3; - } - - /* Switch to read - restart */ - out32r(MPC107_I2CCR, 0xB4); - out32r(MPC107_I2CDR, (0xA1 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 3\n"); - return -4; - } - - out32r(MPC107_I2CCR, 0xA8); /* no ACK */ - in32r(MPC107_I2CDR); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 4\n"); - return -5; - } - /* Generate STOP condition */ - out32r(MPC107_I2CCR, 0x88); - - /* read */ - data = in32r(MPC107_I2CDR); - - return (data); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_write_byte ( - unsigned char device, - unsigned char block, - unsigned char offset, - unsigned char val ) -{ - - unsigned long timeout = MPC107_I2C_TIMEOUT; - - if (!mpc107_eumb_addr) - return -6; - - mpc107_i2c_wait_idle(timeout); - - /* Start with MEN */ - out32r(MPC107_I2CCR, 0x80); - - /* Start as master */ - out32r(MPC107_I2CCR, 0xB0); - out32r(MPC107_I2CDR, (0xA0 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 1\n"); - return -1; - } - - /* Data address */ - out32r(MPC107_I2CDR, offset); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 2\n"); - return -1; - } - - /* Write */ - out32r(MPC107_I2CDR, val); - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 3\n"); - return -1; - } - - /* Generate Stop Condition */ - out32r(MPC107_I2CCR, 0x80); - - /* Return ACK or no ACK */ - return (in32r(MPC107_I2CSR) & 0x01); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_srom_load ( - unsigned char addr, - unsigned char *pBuf, - int cnt, - unsigned char device, - unsigned char block ) -{ - register int i; - int val; - int timeout; - - for (i = 0; i < cnt; i++) - { - timeout=100; - do - { - val = mpc107_i2c_read_byte (device, block, addr); - if (val < -1) - { - printf("i2c_read_error %d at dev %x block %x addr %x\n", - val, device, block, addr); - return -1; - } - else if (timeout==0) - { - printf ("i2c_read_error: timeout at dev %x block %x addr %x\n", - device, block, addr); - return -1; - } - timeout--; - } while (val == -1); /* if no ack: try again! */ - - *pBuf++ = (unsigned char)val; - addr++; - - if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */ - { - if (block == FIRST_BLOCK) - block = SECOND_BLOCK; - else - { - printf ("ic2_read_error: read beyond 2. block !\n"); - return -1; - } - } - } - udelay(100000); - return (cnt); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_srom_store ( - unsigned char addr, - unsigned char *pBuf, - int cnt, - unsigned char device, - unsigned char block ) -{ - register int i; - - for (i = 0; i < cnt; i++) - { - while (mpc107_i2c_write_byte (device,block,addr,*pBuf) == 1); - addr++; - pBuf++; - - if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */ - { - if (block == FIRST_BLOCK) - block = SECOND_BLOCK; - else - { - printf ("ic2_write_error: write beyond 2. block !\n"); - return -1; - } - } - } - udelay(100000); - return(cnt); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_init ( unsigned long eumb_addr, unsigned long divider ) -{ - unsigned long x; - - if (eumb_addr) - mpc107_eumb_addr = eumb_addr; - else - return -1; - - /* Set I2C clock */ - x = in32r(MPC107_I2CFDR) & 0xffffff00; - out32r(MPC107_I2CFDR, (x | divider)); - - /* Clear arbitration */ - out32r(MPC107_I2CSR, 0); - - return mpc107_eumb_addr; -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c deleted file mode 100644 index d81a41a..0000000 --- a/board/eltec/elppc/pci.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI initialisation for the MPC10x. - */ - -#include <common.h> -#include <pci.h> -#include <mpc106.h> - -#ifdef CONFIG_PCI - -struct pci_controller local_hose; - -void pci_init_board(void) -{ - struct pci_controller* hose = (struct pci_controller *)&local_hose; - u16 reg16; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI_MEM_BUS, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_ISA_MEM_BUS, - CONFIG_SYS_ISA_MEM_PHYS, - CONFIG_SYS_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CONFIG_SYS_PCI_IO_BUS, - CONFIG_SYS_PCI_IO_PHYS, - CONFIG_SYS_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CONFIG_SYS_ISA_IO_BUS, - CONFIG_SYS_ISA_IO_PHYS, - CONFIG_SYS_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - MPC106_REG_ADDR, - MPC106_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* Initialises the MPC10x PCI Configuration regs. */ - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* Clear non-reserved bits in status register */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); -} - -#endif /* CONFIG_PCI */ diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h deleted file mode 100644 index 662daf8..0000000 --- a/board/eltec/elppc/srom.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* common srom defs */ -#define FIRST_DEVICE 0x00 -#define SECOND_DEVICE 0x04 -#define FIRST_BLOCK 0x00 -#define SECOND_BLOCK 0x02 -#define BLOCK_SIZE 0x100 -#define ERROR (-1) - -#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100 -#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100 - -#define CPU_TYPE_740 0x08 -#define CPU_TYPE_750 0x08 -#define CPU_TYPE ((get_pvr()>>16)&0xffff) - -#define ABS(x) ((x<0)?-x:x) -#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8) - -/* bab7xx ELTEC srom */ -#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220) -#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221) - -/* srom at mpc107 */ -#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */ -#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */ -#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */ -#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */ -#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */ -#define MPC107_I2C_TIMEOUT 10000000 - -/* i82559 */ -#define EE_ADDR_BITS 6 -#define EE_SIZE 0x40 /* 0x40 words */ -#define EE_CHECKSUM 0xBABA - -/* dc21143 */ -#define DEC_SROM_SIZE 128 - - -/* - * structure of revision srom - */ -typedef struct { - char magic[8]; /* 000 - Magic number */ - char revrev[2]; /* 008 - Revision of structure */ - unsigned short size; /* 00A - Size of CRC area */ - unsigned long crc; /* 00C - CRC */ - char board[16]; /* 010 - Board Revision information */ - char option[4][16]; /* 020 - Option Revision information */ - char serial[8]; /* 060 - Board serial number */ - char etheraddr[6]; /* 068 - Ethernet node addresse */ - char reserved[2]; /* 06E - Reserved */ - char revision[7][2]; /* 070 - Revision codes */ - char category[2]; /* 07E - Category codes */ - char text[64]; /* 080 - Text field */ - char res[64]; /* 0C0 - Reserved */ -} revinfo; - -unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size); -int el_srom_load (unsigned char addr, unsigned char *buf, int cnt, - unsigned char device, unsigned char block); -int el_srom_store (unsigned char addr, unsigned char *buf, int cnt, - unsigned char device, unsigned char block); - -int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider); -int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset); -int mpc107_i2c_write_byte (unsigned char device, unsigned char block, - unsigned char offset, unsigned char val); -int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt, - unsigned char device, unsigned char block); -int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt, - unsigned char device, unsigned char block); - -int dc_srom_load (unsigned short *dest); -int dc_srom_store (unsigned short *src); - -unsigned short eepro100_srom_checksum (unsigned short *sromdata); -void eepro100_srom_load (unsigned short *destination); -int eepro100_srom_store (unsigned short *source); diff --git a/board/evb64260/64260.h b/board/evb64260/64260.h deleted file mode 100644 index d106ced..0000000 --- a/board/evb64260/64260.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __64260_H__ -#define __64260_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_AACK_DELAY (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_TA_DELAY (1 << 15) -#define CPU_CONF_RD_OOO (1 << 16) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_FAST_CLK (1 << 23) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) -#define CPU_CONF_CONF_SB_DIS (1 << 28) -#define CPU_CONF_IO_SB_DIS (1 << 29) -#define CPU_CONF_CLK_SYNC (1 << 30) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64260_H__ */ diff --git a/board/evb64260/Kconfig b/board/evb64260/Kconfig deleted file mode 100644 index 933e6d6..0000000 --- a/board/evb64260/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if TARGET_P3G4 - -config SYS_BOARD - default "evb64260" - -config SYS_CONFIG_NAME - default "P3G4" - -endif - -if TARGET_ZUMA - -config SYS_BOARD - default "evb64260" - -config SYS_CONFIG_NAME - default "ZUMA" - -endif diff --git a/board/evb64260/MAINTAINERS b/board/evb64260/MAINTAINERS deleted file mode 100644 index d50dda5..0000000 --- a/board/evb64260/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -EVB64260 BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/evb64260/ -F: include/configs/P3G4.h -F: configs/P3G4_defconfig - -ZUMA BOARD -#M: Nye Liu <nyet@zumanetworks.com> -S: Orphan (since 2014-04) -F: include/configs/ZUMA.h -F: configs/ZUMA_defconfig diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile deleted file mode 100644 index ae2ebed..0000000 --- a/board/evb64260/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = misc.o -obj-y += evb64260.o flash.o serial.o memory.o pci.o \ - eth.o eth_addrtbl.o mpsc.o i2c.o \ - sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o diff --git a/board/evb64260/README b/board/evb64260/README deleted file mode 100644 index 74211de..0000000 --- a/board/evb64260/README +++ /dev/null @@ -1,54 +0,0 @@ -This file contains status information for the port of U-Boot to the -Galileo Evaluation Board. - -Author: Josh Huber <huber@mclx.com> - Mission Critical Linux, Inc. - -The support for the Galileo Evaluation board is fairly minimal now. -It's sufficient to boot Linux, but doesn't provide too much more than -what's required to do this. - -Both DUART channels are supported (to use the second one, you have to -modify the board -- see the schematics for where to solder on the -devices module). The ethernet ports are supported, and the MPSC is -supported as a console driver. (keep in mind that the kernel has no -support for this yet) - -There are still occaisonal lockups with the MPSC console driver due to -(we think!) overrun problems. If you're looking for something stable -to use for Linux development, consider sticking with the DUART console -for now. - -Automatic memory sizing mostly works. We've had problems with some -combinations of memory. Please send us email if you're having trouble -with respect to the memory detection. - -Right now, only the 512k boot flash is supported. Support for the -16MB flash on the devices module is forthcoming. Right now the flash -is stored at the 256k boundry in flash, wasting a whole sector (64k!) -for environment data. This isn't really a big deal since we're not -using the 512k for anything else. (Just U-Boot and the environment) - -Finally, here is a sample output session: - -U-Boot 1.0.0-pre1 (Jun 6 2001 - 12:45:11) - -Initializing... - CPU: MPC7400 (altivec enabled) v2.9 - Board: EVB64260 - DRAM: 256 MB - FLASH: 512 kB - In: serial - Out: serial - Err: serial - -=> - -The default configuration should be correct for the evaluation board, -as it's shipped from Galileo. Keep in mind that the default baudrate -is set to 38400, 8N1. - -Good luck, and make sure to send any bugreports to us (or the -u-boot-users list). - -Josh diff --git a/board/evb64260/README.EVB-64260-750CX b/board/evb64260/README.EVB-64260-750CX deleted file mode 100644 index 5ea38ea..0000000 --- a/board/evb64260/README.EVB-64260-750CX +++ /dev/null @@ -1,7 +0,0 @@ -The EVB-64260-750CX is quite similar to the EVB-64260-BP already -supported except the following differences: -* It has an IBM-750CXe soldiered on board instead of the slot-1 in the - BP. -* It has a single PCI male connector instead of the 4 PCI female - connectors on the BP. It also gets power trough the PCI connector. -* It has only a single DIMM slot instead of the 2 slots in the BP. diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt deleted file mode 100644 index 6cae9ea..0000000 --- a/board/evb64260/bootseq.txt +++ /dev/null @@ -1,94 +0,0 @@ -(cpu/mpc7xxx/start.S) - -start: - b boot_cold - -start_warm: - b boot_warm - - -boot_cold: -boot_warm: - clear bats - init l2 (if enabled) - init altivec (if enabled) - invalidate l2 (if enabled) - setup bats (from defines in config_EVB) - enable_addr_trans: (if MMU enabled) - enable MSR_IR and MSR_DR - jump to in_flash - -in_flash: - enable l1 dcache - gal_low_init: (board/evb64260/sdram_init.S) - config SDRAM (CFG, TIMING, DECODE) - init scratch regs (810 + 814) - - detect DIMM0 (bank 0 only) - config SDRAM_PARA0 to 256/512Mbit - bl sdram_op_mode - detect bank0 width - write scratch reg 810 - config SDRAM_PARA0 with results - config SDRAM_PARA1 with results - - detect DIMM1 (bank 2 only) - config SDRAM_PARA2 to 256/512Mbit - detect bank2 width - write scratch reg 814 - config SDRAM_PARA2 with results - config SDRAM_PARA3 with results - - setup device bus timings/width - setup boot device timings/width - - setup CPU_CONF (0x0) - setup cpu master control register 0x160 - setup PCI0 TIMEOUT - setup PCI1 TIMEOUT - setup PCI0 BAR - setup PCI1 BAR - - setup MPP control 0-3 - setup GPP level control - setup Serial ports multiplex - - setup stack pointer (r1) - setup GOT - call cpu_init_f - debug leds - board_init_f: (common/board.c) - board_early_init_f: - remap gt regs? - map PCI mem/io - map device space - clear out interrupts - init_timebase - env_init - serial_init - console_init_f - display_options - initdram: (board/evb64260/evb64260.c) - detect memory - for each bank: - dram_size() - setup PCI slave memory mappings - setup SCS - setup monitor - alloc board info struct - init bd struct - relocate_code: (cpu/mpc7xxx/start.S) - copy,got,clearbss - board_init_r(bd, dest_addr) (common/board.c) - setup bd function pointers - trap_init - flash_init: (board/evb64260/flash.c) - setup bd flash info - cpu_init_r: (cpu/mpc7xxx/cpu_init.c) - nothing - mem_malloc_init - malloc_bin_reloc - spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) - env_relocated - misc_init_r(bd): (board/evb64260/evb64260.c) - mpsc_init2 diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c deleted file mode 100644 index d7f63bd..0000000 --- a/board/evb64260/eth.c +++ /dev/null @@ -1,805 +0,0 @@ -/************************************************************************** -Etherboot - BOOTP/TFTP Bootstrap Program -Skeleton NIC driver for Etherboot -***************************************************************************/ - -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file is a modified version from the Galileo polled mode - * network driver for the ethernet contained within the GT64260 - * chip. It has been modified to fit into the U-Boot framework, from - * the original (etherboot) setup. Also, additional cleanup and features - * were added. - * - * - Josh Huber <huber@mclx.com> - */ - -#include <common.h> -#include <malloc.h> -#include <galileo/gt64260R.h> -#include <galileo/core.h> -#include <asm/cache.h> -#include <miiphy.h> -#include <net.h> -#include <netdev.h> - -#include "eth.h" -#include "eth_addrtbl.h" - -#if defined(CONFIG_CMD_NET) - -#define GT6426x_ETH_BUF_SIZE 1536 - -/* if you like verbose output, turn this on! */ -#undef DEBUG - -/* Restart autoneg if we detect link is up on phy init. */ - -/* - * The GT doc's say that after Rst is deasserted, and the PHY - * reports autoneg complete, it runs through its autoneg - * procedures. This doesn't seem to be the case for MII - * PHY's. To work around this check for link up && autoneg - * complete when initilizing the port. If they are both set, - * then restart PHY autoneg. Of course, it may be something - * completly different. - */ -#ifdef CONFIG_ETHER_PORT_MII -# define RESTART_AUTONEG -#endif - -/* do this if you dont want to use snooping */ -#define USE_SOFTWARE_CACHE_MANAGEMENT - -#ifdef USE_SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -/* bummer - w/o flush, nothing works, even with snooping - FIXME */ -/* #define FLUSH_DCACHE(a,b) */ -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif -struct eth_dev_s { - eth0_tx_desc_single *eth_tx_desc; - eth0_rx_desc_single *eth_rx_desc; - char *eth_tx_buffer; - char *eth_rx_buffer[NR]; - int tdn, rdn; - int dev; - unsigned int reg_base; -}; - - -#ifdef CONFIG_INTEL_LXT97X -/* for intel LXT972 */ -static const char ether_port_phy_addr[3]={0,1,2}; -#else -static const char ether_port_phy_addr[3]={4,5,6}; -#endif - -/* MII PHY access routines are common for all i/f, use gal_ent0 */ -#define GT6426x_MII_DEVNAME "gal_enet0" - -int gt6426x_miiphy_read(const char *devname, unsigned char phy, - unsigned char reg, unsigned short *val); - -static inline unsigned short -miiphy_read_ret(unsigned short phy, unsigned short reg) -{ - unsigned short val; - gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val); - return val; -} - - -/************************************************************************** -RESET - Reset adapter -***************************************************************************/ -void -gt6426x_eth_reset(void *v) -{ - /* we should do something here... - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = wp->priv; - */ - - printf ("RESET\n"); - /* put the card in its initial state */ -} - -static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) -{ -#ifdef DEBUG - printf("SMI interrupt: "); - - if(icr&0x20000000) { - printf("SMI done\n"); - } -#endif - - if(icr&0x10000000) { -#ifdef DEBUG - unsigned int psr; - - psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); - printf("PHY state change:\n" - " GT:%s:%s:%s:%s\n", - psr & 1 ? "100" : " 10", - psr & 8 ? " Link" : "nLink", - psr & 2 ? "FD" : "HD", - psr & 4 ? " FC" : "nFC"); - -#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ - { - unsigned short mii_11; - mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11); - - printf(" mii:%s:%s:%s:%s %s:%s %s\n", - mii_11 & (1 << 14) ? "100" : " 10", - mii_11 & (1 << 10) ? " Link" : "nLink", - mii_11 & (1 << 9) ? "FD" : "HD", - mii_11 & (1 << 4) ? " FC" : "nFC", - - mii_11 & (1 << 7) ? "ANc" : "ANnc", - mii_11 & (1 << 8) ? "AN" : "Manual", - "" - ); - } -#endif /* CONFIG_INTEL_LXT97X */ -#endif /* DEBUG */ - } -} - -static int -gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr) -{ - int eth_len=0; - char *eth_data; - - eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)]; - - INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); - - if (rx->command_status & 0x80000000) { - return 0; /* No packet received */ - } - - eth_len = (unsigned int) - (rx->buff_size_byte_count) & 0x0000ffff; - eth_data = (char *) p->eth_rx_buffer[p->rdn]; - -#ifdef DEBUG - if (eth_len) { - printf ("%s: Recived %d byte Packet @ 0x%p\n", - __FUNCTION__, eth_len, eth_data); - } -#endif - /* - * packet is now in: - * eth0_rx_buffer[RDN_ETH0]; - */ - - /* let the upper layer handle the packet */ - NetReceive ((uchar *)eth_data, eth_len); - - rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; - - - /* GT96100 Owner */ - rx->command_status = 0x80000000; - - FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); - - p->rdn ++; - if (p->rdn == NR) {p->rdn = 0;} - - sync(); - - /* Start Rx*/ - GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080); - -#ifdef DEBUG - { - int i; - for (i=0;i<12;i++) { - printf(" %02x", eth_data[i]); - } - } - printf(": %d bytes\n", eth_len); -#endif - INVALIDATE_DCACHE((unsigned int)eth_data, - (unsigned int)eth_data+eth_len); - return eth_len; -} - -/************************************************************************** -POLL - look for an rx frame, handle other conditions -***************************************************************************/ -int -gt6426x_eth_poll(void *v) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = wp->priv; - unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base); - - if(icr) { - GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0); -#ifdef DEBUG - printf("poll got ICR %08x\n", icr); -#endif - /* SMI done or PHY state change*/ - if(icr&0x30000000) gt6426x_handle_SMI(p, icr); - } - /* always process. We aren't using RX interrupts */ - return gt6426x_eth_receive(p, icr); -} - -/************************************************************************** -TRANSMIT - Transmit a frame -***************************************************************************/ -int gt6426x_eth_transmit(void *v, char *p, unsigned int s) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv; -#ifdef DEBUG - unsigned int old_command_stat,old_psr; -#endif - eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn]; - - /* wait for tx to be ready */ - INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); - while (tx->command_status & 0x80000000) { - int i; - for(i=0;i<1000;i++); - INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); - } - - GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base, - (unsigned int)tx); - -#ifdef DEBUG - printf("copying to tx_buffer [%p], length %x, desc = %p\n", - dev->eth_tx_buffer, s, dev->eth_tx_desc); -#endif - memcpy(dev->eth_tx_buffer, (char *) p, s); - - tx->buff_pointer = (uchar *)dev->eth_tx_buffer; - tx->bytecount_reserved = ((__u16)s) << 16; - - /* 31 - own - * 22 - gencrc - * 18:16 - pad, last, first */ - tx->command_status = (1<<31) | (1<<22) | (7<<16); -#if 0 - /* FEr #18 */ - tx->next_desc = NULL; -#else - tx->next_desc = - (struct eth0_tx_desc_struct *) - &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved; - - /* cpu owned */ - dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */ -#endif - -#ifdef DEBUG - old_command_stat=tx->command_status, - old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); -#endif - - FLUSH_DCACHE((unsigned int)tx, - (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]); - - FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s); - - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000); - -#ifdef DEBUG - { - unsigned int command_stat=0; - printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr); - /* wait for tx to be ready */ - do { - unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); - command_stat=tx->command_status; - if(command_stat!=old_command_stat || psr !=old_psr) { - printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr); - old_command_stat = command_stat; - old_psr = psr; - } - /* gt6426x_eth0_poll(); */ - } while (command_stat & 0x80000000); - - printf("sent %d byte frame\n", s); - - if((command_stat & (3<<15)) == 3) { - printf("frame had error (stat=%08x)\n", command_stat); - } - } -#endif - return 0; -} - -/************************************************************************** -DISABLE - Turn off ethernet interface -***************************************************************************/ -void -gt6426x_eth_disable(void *v) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; - - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000); -} - -/************************************************************************** -MII utilities - write: write to an MII register via SMI -***************************************************************************/ -int -gt6426x_miiphy_write(const char *devname, unsigned char phy, - unsigned char reg, unsigned short data) -{ - unsigned int temp= (reg<<21) | (phy<<16) | data; - - while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ - - GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); - return 0; -} - -/************************************************************************** -MII utilities - read: read from an MII register via SMI -***************************************************************************/ -int -gt6426x_miiphy_read(const char *devname, unsigned char phy, - unsigned char reg, unsigned short *val) -{ - unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; - - while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ - - GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); - - while(1) { - temp=GTREGREAD(ETHERNET_SMI_REGISTER); - if(temp & (1<<27)) break; /* wait for ReadValid */ - } - *val = temp & 0xffff; - - return 0; -} - -#ifdef DEBUG -/************************************************************************** -MII utilities - dump mii registers -***************************************************************************/ -static void -gt6426x_dump_mii(bd_t *bis, unsigned short phy) -{ - printf("mii reg 0 - 3: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x0), - miiphy_read_ret(phy, 0x1), - miiphy_read_ret(phy, 0x2), - miiphy_read_ret(phy, 0x3) - ); - printf(" 4 - 7: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x4), - miiphy_read_ret(phy, 0x5), - miiphy_read_ret(phy, 0x6), - miiphy_read_ret(phy, 0x7) - ); - printf(" 8: %04x\n", - miiphy_read_ret(phy, 0x8) - ); - printf(" 16-19: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x10), - miiphy_read_ret(phy, 0x11), - miiphy_read_ret(phy, 0x12), - miiphy_read_ret(phy, 0x13) - ); - printf(" 20,30: %04x %04x\n", - miiphy_read_ret(phy, 20), - miiphy_read_ret(phy, 30) - ); -} -#endif - -#ifdef RESTART_AUTONEG - -/* If link is up && autoneg compleate, and if - * GT and PHY disagree about link capabilitys, - * restart autoneg - something screwy with FD/HD - * unless we do this. */ -static void -check_phy_state(struct eth_dev_s *p) -{ - int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR); - int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); - - if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) { - int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) & - miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA); - int want; - - if (nego & LPA_100FULL) { - want = 0x3; - printf("MII: 100Base-TX, Full Duplex\n"); - } else if (nego & LPA_100HALF) { - want = 0x1; - printf("MII: 100Base-TX, Half Duplex\n"); - } else if (nego & LPA_10FULL) { - want = 0x2; - printf("MII: 10Base-T, Full Duplex\n"); - } else if (nego & LPA_10HALF) { - want = 0x0; - printf("MII: 10Base-T, Half Duplex\n"); - } else { - printf("MII: Unknown link-foo! %x\n", nego); - return; - } - - if ((psr & 0x3) != want) { - printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n", - psr & 0x3, want); - miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0, - miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9)); - udelay(10000); /* the EVB's GT takes a while to notice phy - went down and up */ - } - } -} -#endif - -/************************************************************************** -PROBE - Look for an adapter, this routine's visible to the outside -***************************************************************************/ -int -gt6426x_eth_probe(void *v, bd_t *bis) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; - int dev = p->dev; - unsigned int reg_base = p->reg_base; - unsigned long temp; - int i; - - if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS )) - { /* This should never happen */ - printf("%s: Invalid device %d\n", __FUNCTION__, dev ); - return 0; - } - -#ifdef DEBUG - printf ("%s: initializing %s\n", __FUNCTION__, wp->name ); - printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n", - GTREGREAD(COMM_UNIT_ARBITER_CONTROL), - GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER)); -#endif - - /* clear MIB counters */ - for(i=0;i<255; i++) - temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i); - -#ifdef CONFIG_INTEL_LXT97X - /* for intel LXT972 */ - - /* led 1: 0x1=txact - led 2: 0xc=link/rxact - led 3: 0x2=rxact (N/C) - strch: 0,2=30 ms, enable */ - miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22); - - /* 2.7ns port rise time */ - /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */ -#else - /* already set up in mpsc.c */ - /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */ - - /* already set up in sdram_init.S... */ - /* MPSC0, MPSC1, RMII */ - /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */ -#endif - GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER, - ether_port_phy_addr[0] | - (ether_port_phy_addr[1]<<5) | - (ether_port_phy_addr[2]<<10)); /* 2000 */ - - /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes) - * 9 - 1: RIFB - interrupt on frame boundaries only - * 6:7 - 00: big endian rx and tx - * 5:2 - 1111: 15 retries */ - GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base, - (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */ - -#ifndef USE_SOFTWARE_CACHE_MANAGEMENT - /* enable rx/tx desc/buffer cache snoop */ - GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, - &temp); /* f200 */ - temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30); - GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, - temp); -#endif - - /* 31 28 27 24 23 20 19 16 - * 0000 0000 0000 0000 [0004] - * 15 12 11 8 7 4 3 0 - * 1000 1101 0000 0000 [4d00] - * 20 - 0=MII 1=RMII - * 19 - 0=speed autoneg - * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE) - * 11 - no force link pass - * 10 - 1=disable fctl autoneg - * 8 - override prio ?? */ - temp = 0x00004d00; -#ifndef CONFIG_ETHER_PORT_MII - temp |= (1<<20); /* RMII */ -#endif - /* set En */ - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base, - temp); /* 2408 */ - - /* hardcode E1 also? */ - /* -- according to dox, this is safer due to extra pulldowns? */ - if (dev<2) { - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400, - temp); /* 2408 */ - } - - /* wake up MAC */ /* 2400 */ - GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp); - temp |= (1<<7); /* enable port */ -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - temp |= (1<<12); /* hash size 1/2k */ -#else - temp |= 1; /* promisc */ -#endif - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp); - /* 2400 */ - -#ifdef RESTART_AUTONEG - check_phy_state(p); -#endif - - printf("%s: Waiting for link up..\n", wp->name); - temp = 10 * 1000; - /* wait for link back up */ - while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8) - && (--temp > 0)){ - udelay(1000); /* wait 1 ms */ - } - if ( temp == 0) { - printf("%s: Failed!\n", wp->name); - return (0); - } - - printf("%s: OK!\n", wp->name); - - p->tdn = 0; - p->rdn = 0; - p->eth_tx_desc[p->tdn].command_status = 0; - - /* Initialize Rx Side */ - for (temp = 0; temp < NR; temp++) { - p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp]; - p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; - - /* GT96100 Owner */ - p->eth_rx_desc[temp].command_status = 0x80000000; - p->eth_rx_desc[temp].next_desc = - (struct eth0_rx_desc_struct *) - &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count; - } - - FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0], - (unsigned int)&p->eth_tx_desc[NR]); - FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0], - (unsigned int)&p->eth_rx_desc[NR]); - - GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_tx_desc); - GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_rx_desc); - GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_rx_desc); - -#ifdef DEBUG - printf ("\nRx descriptor pointer is %08x %08x\n", - GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base), - GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base)); - printf ("\n\n%08x %08x\n", - (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status); - - printf ("Descriptor dump:\n"); - printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status); - printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count); - printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer); - printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0)); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4)); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8)); - printf ("%08x\n\n", - *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc)); -#endif - -#ifdef DEBUG - gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]); -#endif - -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - { - unsigned int hashtable_base; - u8 *b = (u8 *)(wp->enetaddr); - u32 macH, macL; - - /* twist the MAC up into the way the discovery wants it */ - macH= (b[0]<<8) | b[1]; - macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5]; - - /* mode 0, size 0x800 */ - hashtable_base =initAddressTable(dev,0,1); - - if(!hashtable_base) { - printf("initAddressTable failed\n"); - return 0; - } - - addAddressTableEntry(dev, macH, macL, 1, 0); - GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base, - hashtable_base); - } -#endif - - /* Start Rx*/ - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080); - printf("%s: gt6426x eth device %d init success \n", wp->name, dev ); - return 1; -} - -/* enter all the galileo ethernet devs into MULTI-BOOT */ -void -gt6426x_eth_initialize(bd_t *bis) -{ - struct eth_device *dev; - struct eth_dev_s *p; - int devnum, x, temp; - char *s, *e, buf[64]; - -#ifdef DEBUG - printf( "\n%s\n", __FUNCTION ); -#endif - - for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) { - dev = calloc(sizeof(*dev), 1); - if (!dev) { - printf( "%s: gal_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf(dev->name, "gal_enet%d", devnum); - -#ifdef DEBUG - printf( "Initializing %s\n", dev->name ); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) - { - case 0: s = "ethaddr"; break; -#if (GAL_ETH_DEVS > 1) - case 1: s = "eth1addr"; break; -#endif -#if (GAL_ETH_DEVS > 2) - case 2: s = "eth2addr"; break; -#endif - default: /* this should never happen */ - printf( "%s: Invalid device number %d\n", - __FUNCTION__, devnum ); - return; - } - - temp = getenv_f(s, buf, sizeof(buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s ); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e+1 : e; - } - - dev->init = (void*)gt6426x_eth_probe; - dev->halt = (void*)gt6426x_eth_reset; - dev->send = (void*)gt6426x_eth_transmit; - dev->recv = (void*)gt6426x_eth_poll; - - p = calloc( sizeof(*p), 1 ); - dev->priv = (void*)p; - if (!p) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Private Device Structure"); - free(dev); - return; - } - - p->dev = devnum; - p->tdn=0; - p->rdn=0; - p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS; - - p->eth_tx_desc = - (eth0_tx_desc_single *) - (((unsigned int) malloc(sizeof (eth0_tx_desc_single) * - (NT+1)) & 0xfffffff0) + 0x10); - if (!p) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Tx Descriptor"); - free(dev); - return; - } - - p->eth_rx_desc = - (eth0_rx_desc_single *) - (((unsigned int) malloc(sizeof (eth0_rx_desc_single) * - (NR+1)) & 0xfffffff0) + 0x10); - if (!p->eth_rx_desc) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Rx Descriptor"); - free(dev); - free(p); - return; - } - - p->eth_tx_buffer = - (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); - if (!p->eth_tx_buffer) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Tx Bufffer"); - free(dev); - free(p); - free(p->eth_rx_desc); - return; - } - - for (temp = 0 ; temp < NR ; temp ++) { - p->eth_rx_buffer[temp] = - (char *) - (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); - if (!p->eth_rx_buffer[temp]) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Rx Buffers"); - free(dev); - free(p); - free(p->eth_tx_buffer); - free(p->eth_rx_desc); - free(p->eth_tx_desc); - while (temp >= 0) - free(p->eth_rx_buffer[--temp]); - return; - } - } - - - eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, - gt6426x_miiphy_read, gt6426x_miiphy_write); -#endif - } - -} -#endif diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h deleted file mode 100644 index 99581f0..0000000 --- a/board/evb64260/eth.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __GT6426x_ETH_H__ -#define __GT6426x_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> - -typedef struct eth0_tx_desc_struct { - volatile __u32 bytecount_reserved; - volatile __u32 command_status; - volatile struct eth0_tx_desc_struct * next_desc; - /* Note - the following will not work for 64 bit addressing */ - volatile unsigned char * buff_pointer; -} __attribute__ ((packed)) eth0_tx_desc_single; - -typedef struct eth0_rx_desc_struct { - volatile __u32 buff_size_byte_count; - volatile __u32 command_status; - volatile struct eth0_rx_desc_struct * next_desc; - volatile unsigned char * buff_pointer; -} __attribute__ ((packed)) eth0_rx_desc_single; - -#define NT 20 /* Number of Transmit buffers */ -#define NR 20 /* Number of Receive buffers */ -#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) /* 1600 */ -#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400 - -unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/ -unsigned int EVB64260_ETH0_irq; - -#define CLOSED 0 -#define OPENED 1 - -#define PORT_ETH0 0 - -extern eth0_tx_desc_single *eth0_tx_desc; -extern eth0_rx_desc_single *eth0_rx_desc; -extern char *eth0_tx_buffer; -extern char *eth0_rx_buffer[NR]; -extern char *eth_data; - -extern int gt6426x_eth_poll(void *v); -extern int gt6426x_eth_transmit(void *v, char *p, unsigned int s); -extern void gt6426x_eth_disable(void *v); -extern int gt6426x_eth_probe(void *v, bd_t *bis); - -#endif /* __GT64260x_ETH_H__ */ diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c deleted file mode 100644 index 8c2c17f..0000000 --- a/board/evb64260/eth_addrtbl.c +++ /dev/null @@ -1,218 +0,0 @@ -#include <common.h> -#include <malloc.h> -#include <galileo/gt64260R.h> -#include <galileo/core.h> -#include <asm/cache.h> -#include "eth.h" -#include "eth_addrtbl.h" - -#define PRINTF printf - -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - -static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, }; -static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, }; -static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, }; -static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, }; - -static const u32 hashLength[2] = { - (0x8000), /* 8K * 4 entries */ - (0x8000 / 16), /* 512 * 4 entries */ -}; - -/* Initialize the address table for a port, if needed */ -unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector) -{ - unsigned int tableBase; - - if (port < 0 || port >= GAL_ETH_DEVS) { - printf ("%s: Invalid port number %d\n", __FUNCTION__, port); - return 0; - } - - if (hashMode > 1) { - printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port); - return 0; - } - - if (realAddrTableBase[port] && - (addressTableHashSize[port] != hashSizeSelector)) { - /* we have been here before, - * but now we want a different sized table - */ - free (realAddrTableBase[port]); - realAddrTableBase[port] = 0; - addressTableBase[port] = 0; - - } - - tableBase = (unsigned int) addressTableBase[port]; - /* we get called for every probe, so only do this once */ - if (!tableBase) { - int bytes = - hashLength[hashSizeSelector] * sizeof (addrTblEntry); - - realAddrTableBase[port] = - malloc (bytes + 64); - tableBase = (unsigned int)realAddrTableBase; - - if (!tableBase) { - printf ("%s: alloc memory failed \n", __FUNCTION__); - return 0; - } - - /* align to octal byte */ - if (tableBase & 63) - tableBase = (tableBase + 63) & ~63; - - addressTableHashMode[port] = hashMode; - addressTableHashSize[port] = hashSizeSelector; - addressTableBase[port] = (addrTblEntry *) tableBase; - - memset ((void *) tableBase, 0, bytes); - } - - return tableBase; -} - -/* - * ---------------------------------------------------------------------------- - * This function will calculate the hash function of the address. - * depends on the hash mode and hash size. - * Inputs - * macH - the 2 most significant bytes of the MAC address. - * macL - the 4 least significant bytes of the MAC address. - * hashMode - hash mode 0 or hash mode 1. - * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800) - * Outputs - * return the calculated entry. - */ -u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode) -{ - u32 hashResult; - u32 addrH; - u32 addrL; - u32 addr0; - u32 addr1; - u32 addr2; - u32 addr3; - u32 addrHSwapped; - u32 addrLSwapped; - - - addrH = NIBBLE_SWAPPING_16_BIT (macH); - addrL = NIBBLE_SWAPPING_32_BIT (macL); - - addrHSwapped = FLIP_4_BITS (addrH & 0xf) - + ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4) - + ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8) - + ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12); - - addrLSwapped = FLIP_4_BITS (addrL & 0xf) - + ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4) - + ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8) - + ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12) - + ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16) - + ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20) - + ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24) - + ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28); - - addrH = addrHSwapped; - addrL = addrLSwapped; - - if (hash_mode == 0) { - addr0 = (addrL >> 2) & 0x03f; - addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2; - addr2 = (addrL >> 15) & 0x1ff; - addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8); - } else { - addr0 = FLIP_6_BITS (addrL & 0x03f); - addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff)); - addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff); - addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) | - ((addrH & 0x1) << 8))); - } - - hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); - - if (HashSize == _8K_TABLE) { - hashResult = hashResult & 0xffff; - } else { - hashResult = hashResult & 0x07ff; - } - - return (hashResult); -} - - -/* - * ---------------------------------------------------------------------------- - * This function will add an entry to the address table. - * depends on the hash mode and hash size that was initialized. - * Inputs - * port - ETHERNET port number. - * macH - the 2 most significant bytes of the MAC address. - * macL - the 4 least significant bytes of the MAC address. - * skip - if 1, skip this address. - * rd - the RD field in the address table. - * Outputs - * address table entry is added. - * true if success. - * false if table full - */ -int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip) -{ - addrTblEntry *entry; - u32 newHi; - u32 newLo; - u32 i; - - newLo = (((macH >> 4) & 0xf) << 15) - | (((macH >> 0) & 0xf) << 11) - | (((macH >> 12) & 0xf) << 7) - | (((macH >> 8) & 0xf) << 3) - | (((macL >> 20) & 0x1) << 31) - | (((macL >> 16) & 0xf) << 27) - | (((macL >> 28) & 0xf) << 23) - | (((macL >> 24) & 0xf) << 19) - | (skip << SKIP_BIT) | (rd << 2) | VALID; - - newHi = (((macL >> 4) & 0xf) << 15) - | (((macL >> 0) & 0xf) << 11) - | (((macL >> 12) & 0xf) << 7) - | (((macL >> 8) & 0xf) << 3) - | (((macL >> 21) & 0x7) << 0); - - /* - * Pick the appropriate table, start scanning for free/reusable - * entries at the index obtained by hashing the specified MAC address - */ - entry = addressTableBase[port]; - entry += hashTableFunction (macH, macL, addressTableHashSize[port], - addressTableHashMode[port]); - for (i = 0; i < HOP_NUMBER; i++, entry++) { - if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) { - break; - } else { /* if same address put in same position */ - if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8)) - && (entry->hi == newHi)) { - break; - } - } - } - - if (i == HOP_NUMBER) { - PRINTF ("addGT64260addressTableEntry: table section is full\n"); - return false; - } - - /* - * Update the selected entry - */ - entry->hi = newHi; - entry->lo = newLo; - DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE); - return true; -} - -#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */ diff --git a/board/evb64260/eth_addrtbl.h b/board/evb64260/eth_addrtbl.h deleted file mode 100644 index 5a62c67..0000000 --- a/board/evb64260/eth_addrtbl.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef _ADDRESS_TABLE_H -#define _ADDRESS_TABLE_H 1 - -/* - * ---------------------------------------------------------------------------- - * addressTable.h - this file has all the declarations of the address table - */ - -#define _8K_TABLE 0 -#define ADDRESS_TABLE_ALIGNMENT 8 -#define HASH_DEFAULT_MODE 14 -#define HASH_MODE 13 -#define HASH_SIZE 12 -#define HOP_NUMBER 12 -#define MAC_ADDRESS_STRING_SIZE 12 -#define MAC_ENTRY_SIZE sizeof(addrTblEntry) -#define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000 -#define PROMISCUOUS_MODE 0 -#define SKIP 1<<1 -#define SKIP_BIT 1 -#define VALID 1 - -/* - * ---------------------------------------------------------------------------- - * XXX_MIKE - potential sign-extension bugs lurk here... - */ -#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \ - | (((X) & 0x0f0f0f0f) << 4) ) - -#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \ - | (((X) & 0x00000f0f) << 4) ) - -#define FLIP_4_BITS(X) ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \ - | (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) ) - -#define FLIP_6_BITS(X) ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \ - | (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \ - | (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) ) - -#define FLIP_9_BITS(X) ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \ - | (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \ - | (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \ - | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) ) - -/* - * V: value we're operating on - * O: offset of rightmost bit in field - * W: width of field to shift - * S: distance to shift left - */ -#define MASK( fieldWidth ) ((1 << (fieldWidth)) - 1) -#define leftShiftedBitfield( V,O,W,S) (((V) & (MASK(W) << (O))) << (S)) -#define rightShiftedBitfield(V,O,W,S) (((u32)((V) & (MASK(W) << (O)))) >> (S)) - - -/* - * Push to main memory all cache lines associated with - * the specified range of virtual memory addresses - * - * A: Address of first byte in range to flush - * N: Number of bytes to flush - * Note - flush_dcache_range() does a "sync", does NOT invalidate - */ -#define DCACHE_FLUSH_N_SYNC( A, N ) flush_dcache_range( (A), ((A)+(N)) ) - - -typedef struct addressTableEntryStruct { - u32 hi; - u32 lo; -} addrTblEntry; - -u32 -uncachedPages( u32 pages ); -u32 -hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode ); - -unsigned int -initAddressTable( u32 port, u32 hashMode, u32 hashSize ); - -int -addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip ); - -#endif /* #ifndef _ADDRESS_TABLE_H */ diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c deleted file mode 100644 index 74f8819..0000000 --- a/board/evb64260/evb64260.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * evb64260.c - main board support/init for the Galileo Eval board. - */ - -#include <common.h> -#include <74xx_7xx.h> -#include <galileo/memory.h> -#include <galileo/pci.h> -#include <galileo/gt64260R.h> -#include <net.h> -#include <netdev.h> -#include <linux/compiler.h> - -#include <asm/io.h> -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64260.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_ZUMA_V2 -extern void zuma_mbox_init(void); -#endif - -#undef DEBUG -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void -my_remap_gt_regs(u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -} - -static void -gt_pci_config(void) -{ - /* move PCI stuff out of the way - NTL */ - /* map PCI Host 0 */ - pciMapSpace(PCI_HOST0, PCI_REGION0, CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, CONFIG_SYS_PCI0_MEM_SIZE); - - pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0); - pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0); - pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0); - - pciMapSpace(PCI_HOST0, PCI_IO, CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE); - - /* map PCI Host 1 */ - pciMapSpace(PCI_HOST1, PCI_REGION0, CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, CONFIG_SYS_PCI1_MEM_SIZE); - - pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0); - pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0); - pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0); - - pciMapSpace(PCI_HOST1, PCI_IO, CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE); - - /* PCI interface settings */ - GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff); - GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff); - GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); - GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); - - -} - -/* Setup CPU interface paramaters */ -static void -gt_cpu_config(void) -{ - cpu_t cpu = get_cpu_type(); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD(CPU_CONFIGURATION); - - /* set the AACK delay bit - * see Res#14 */ - tmp |= CPU_CONF_AACK_DELAY; - tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */ - - /* Galileo claims this is necessary for all busses >= 100 MHz */ - tmp |= CPU_CONF_FAST_CLK; - - if (cpu == CPU_750CX) { - tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */ - tmp &= ~CPU_CONF_AP_VALID; - } else { - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - } - - /* this only works with the MPX bus */ - tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */ - tmp |= CPU_CONF_PIPELINE; - tmp |= CPU_CONF_TA_DELAY; - - GT_REG_WRITE(CPU_CONFIGURATION, tmp); - - /* CPU master control register */ - tmp = GTREGREAD(CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || - (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE(CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - my_remap_gt_regs(CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - - gt_pci_config(); - - /* mask all external interrupt sources */ - GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - - /* now, onto the configuration */ - GT_REG_WRITE(SDRAM_CONFIGURATION, CONFIG_SYS_SDRAM_CONFIG); - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM - * 1 - RTC - * 2 - UART - * 3 - Flash - * boot - BootCS - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - /* Zuma has no SRAM */ - sram_boot = 0; -#else - if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CONFIG_SYS_MONITOR_BASE) - sram_boot = 1; -#endif - - memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - - memoryMapDeviceSpace(DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); - memoryMapDeviceSpace(DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); - memoryMapDeviceSpace(DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); - - /* configure device timing */ -#ifdef CONFIG_SYS_DEV0_PAR - if (!sram_boot) - GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); -#endif - -#ifdef CONFIG_SYS_DEV1_PAR - GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); -#endif -#ifdef CONFIG_SYS_DEV2_PAR - GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); -#endif - -#ifdef CONFIG_EVB64260 -#ifdef CONFIG_SYS_32BIT_BOOT_PAR - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); -#endif -#else /* CONFIG_EVB64260 not defined */ - /* We are booting from 16-bit flash. - */ - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_16BIT_BOOT_PAR); -#endif - - gt_cpu_config(); - - /* MPP setup */ - GT_REG_WRITE(MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE(MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE(MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE(MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE(GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CONFIG_SYS_SERIAL_PORT_MUX); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r (void) -{ - icache_enable(); -#ifdef CONFIG_SYS_L2 - l2cache_enable(); -#endif - -#ifdef CONFIG_MPSC - mpsc_init2(); -#endif - -#ifdef CONFIG_ZUMA_V2 - zuma_mbox_init(); -#endif - return (0); -} - -void -after_reloc(ulong dest_addr) -{ - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - - if (memoryGetDeviceBaseAddress(DEVICE0) == CONFIG_SYS_MONITOR_BASE) { - memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace(BOOT_DEVICE, CONFIG_SYS_FLASH_BASE, _1M); - } - - /* now, jump to the main U-Boot board init code */ - board_init_r ((gd_t *)gd, dest_addr); - - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int -checkboard (void) -{ - puts ("Board: " CONFIG_SYS_BOARD_NAME "\n"); - return (0); -} - -/* utility functions */ -void -debug_led(int led, int mode) -{ -#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4) - volatile int *addr = NULL; - __maybe_unused int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x08000); - break; - - case 1: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x0c000); - break; - - case 2: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x14000); - break; - - case 1: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x18000); - break; - - case 2: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x1c000); - break; - } - } - WRITE_CHAR(addr, 0); - dummy = *addr; -#endif /* CONFIG_ZUMA_V2 */ -} - -void -display_mem_map(void) -{ - int i,j; - unsigned int base,size,width; - /* SDRAM */ - printf("SDRAM\n"); - for(i=0;i<=BANK3;i++) { - base = memoryGetBankBaseAddress(i); - size = memoryGetBankSize(i); - if(size !=0) - { - printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20); - } - } - - /* CPU's PCI windows */ - for(i=0;i<=PCI_HOST1;i++) { - printf("\nCPU's PCI %d windows\n", i); - base=pciGetSpaceBase(i,PCI_IO); - size=pciGetSpaceSize(i,PCI_IO); - printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20); - for(j=0;j<=PCI_REGION3;j++) { - base = pciGetSpaceBase(i,j); - size = pciGetSpaceSize(i,j); - printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base, - size>>20); - } - } - - /* Devices */ - printf("\nDEVICES\n"); - for(i=0;i<=DEVICE3;i++) { - base = memoryGetDeviceBaseAddress(i); - size = memoryGetDeviceSize(i); - width= memoryGetDeviceWidth(i) * 8; - printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", - i, base, size>>20, width); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize(BOOT_DEVICE); - width= memoryGetDeviceWidth(BOOT_DEVICE) * 8; - printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", - base, size>>20, width); -} - -int board_eth_init(bd_t *bis) -{ - gt6426x_eth_initialize(bis); - return 0; -} diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c deleted file mode 100644 index f3b0074..0000000 --- a/board/evb64260/flash.c +++ /dev/null @@ -1,837 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * flash.c - flash support for the 512k, 8bit boot flash on the GEVB - * most of this file was based on the existing U-Boot - * flash drivers. - */ - -#include <common.h> -#include <mpc8xx.h> -#include <galileo/gt64260R.h> -#include <galileo/memory.h> -#include "intel_flash.h" - -#define FLASH_ROM 0xFFFD /* unknown flash type */ -#define FLASH_RAM 0xFFFE /* unknown flash type */ -#define FLASH_MAN_UNKNOWN 0xFFFF0000 - -/* #define DEBUG */ -/* #define FLASH_ID_OVERRIDE */ /* Hack to set type to 040B if ROM emulator is installed. - * Can be used to program a ROM in circuit if a programmer - * is not available by swapping the rom out. */ - -/* Intel flash commands */ -int flash_erase_intel(flash_info_t *info, int s_first, int s_last); -int write_word_intel(bank_addr_t addr, bank_word_t value); - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - unsigned int i; - unsigned long size_b0 = 0, size_b1 = 0; - unsigned long base, flash_size; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* the boot flash */ - base = CONFIG_SYS_FLASH_BASE; -#ifndef CONFIG_SYS_BOOT_FLASH_WIDTH -#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 -#endif - size_b0 = flash_get_size(CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *)base, - &flash_info[0]); - -#ifndef CONFIG_P3G4 - printf("["); - print_size (size_b0, ""); - printf("@%08lX] ", base); -#endif - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", - base, size_b0, size_b0<<20); - } - - base = memoryGetDeviceBaseAddress(CONFIG_SYS_EXTRA_FLASH_DEVICE); - for(i=1;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) { - unsigned long size = flash_get_size(CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]); - -#ifndef CONFIG_P3G4 - printf("["); - print_size (size, ""); - printf("@%08lX] ", base); -#endif - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - if(i==1) { - printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", - base, size_b1, size_b1<<20); - } - break; - } - size_b1+=size; - base+=size; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - flash_size = size_b0 + size_b1; - return flash_size; -} - -/*----------------------------------------------------------------------- - */ -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - int sector_size; - - if(!info->sector_count) return; - - /* set up sector start address table */ - switch(info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - case FLASH_28F128J3A: - case FLASH_28F640J3A: - case FLASH_RAM: - /* this chip has uniformly spaced sectors */ - sector_size=info->size/info->sector_count; - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sector_size); - break; - default: - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ - -flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base <= info->start[0] + info->size - 1) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64 Mbit)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128 Mbit)\n"); - break; - case FLASH_ROM: - printf ("ROM\n"); - break; - case FLASH_RAM: - printf ("RAM\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - puts (" Size: "); - print_size (info->size, ""); - printf (" in %d Sectors\n", info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd) -{ - /* supports 1x8, 1x16, and 2x16 */ - /* 2x8 and 4x8 are not supported */ - if(width==4) { - /* assuming chips are in 16 bit mode */ - /* 2x16 */ - unsigned long cmd32=(cmd<<16)|cmd; - *(volatile unsigned long *)(addr+offset*2)=cmd32; - } else if (width == 2) { - /* 1x16 */ - *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd; - } else { - /* 1x8 */ - *(volatile unsigned char *)(addr+offset)=cmd; - } -} - -static ulong -flash_get_size (int portwidth, vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr = (unsigned char *)addr; - volatile unsigned short *saddr = (unsigned short *)addr; - volatile unsigned long *laddr = (unsigned long *)addr; - char old[2], save; - ulong id, manu, base = (ulong)addr; - - info->portwidth=portwidth; - - save = *caddr; - - flash_cmd(portwidth,caddr,0,0xf0); - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - - old[0] = caddr[0]; - old[1] = caddr[1]; - - - if(old[0]!=0xf0) { - flash_cmd(portwidth,caddr,0,0xf0); - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - - if(*caddr==0xf0) { - /* this area is ROM */ - *caddr=save; -#ifndef FLASH_ID_OVERRIDE - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; -#else - info->flash_id = FLASH_MAN_AMD + FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; -#endif - flash_get_offsets(base, info); - return info->size; - } - } else { - *caddr=0; - - udelay(10); - - if(*caddr==0) { - /* this area is RAM */ - *caddr=save; - info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets(base, info); - return info->size; - } - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - } - - /* Write auto select command: read Manufacturer ID */ - flash_cmd(portwidth,caddr,0x555,0xAA); - flash_cmd(portwidth,caddr,0x2AA,0x55); - flash_cmd(portwidth,caddr,0x555,0x90); - - udelay(10); - - if ((caddr[0] == old[0]) && - (caddr[1] == old[1])) { - - /* this area is ROM */ -#ifndef FLASH_ID_OVERRIDE - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; -#else - info->flash_id = FLASH_MAN_AMD + FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; -#endif - flash_get_offsets(base, info); - return info->size; -#ifdef DEBUG - } else { - printf("%px%d: %02x:%02x -> %02x:%02x\n", - caddr, portwidth, old[0], old[1], - caddr[0], caddr[1]); -#endif - } - - switch(portwidth) { - case 1: - manu = caddr[0]; - manu |= manu<<16; - id = caddr[1]; - break; - case 2: - manu = saddr[0]; - manu |= manu<<16; - id = saddr[1]; - id |= id<<16; - break; - case 4: - manu = laddr[0]; - id = laddr[1]; - break; - default: - id = manu = -1; - break; - } - -#ifdef DEBUG - printf("\n%08lx:%08lx:%08lx\n", base, manu, id); - printf("%08lx %08lx %08lx %08lx\n", - laddr[0],laddr[1],laddr[2],laddr[3]); -#endif - - switch (manu) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("Unknown Mfr [%08lx]:%08lx\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (id) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth=1; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth=1; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth=1; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth=1; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth=1; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth=1; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; - break; - - case INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */ - info->chipwidth=2; - if(portwidth==4) info->size*=2; /* 2x16 */ - break; - - case INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */ - info->chipwidth=2; - if(portwidth==4) info->size*=2; /* 2x16 */ - break; - - default: - printf("Unknown id %lx:[%lx]\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->chipwidth=1; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets(base, info); - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_AM040) { - /* this chip has uniformly spaced sectors */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0)=0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - saddr = (volatile unsigned short *)(info->start[i]); - laddr = (volatile unsigned long *)(info->start[i]); - if(portwidth==1) - info->protect[i] = caddr[2] & 1; - else if(portwidth==2) - info->protect[i] = saddr[2] & 1; - else - info->protect[i] = laddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - - flash_cmd(portwidth,caddr,0,0xF0); /* reset bank */ - } - - return (info->size); -} - -/* TODO: 2x16 unsupported */ -int -flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = (uchar *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - /* TODO: 2x16 unsupported */ - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - for (sect = s_first; sect<=s_last; sect++) { - int sector_size=info->size/info->sector_count; - addr = (uchar *)(info->start[sect]); - memset((void *)addr, 0, sector_size); - } - return 0; - } - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL) { - return flash_erase_intel(info, - (unsigned short)s_first, - (unsigned short)s_last); - } - -#if 0 - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } -#endif - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_cmd(info->portwidth,addr,0x555,0xAA); - flash_cmd(info->portwidth,addr,0x2AA,0x55); - flash_cmd(info->portwidth,addr,0x555,0x80); - flash_cmd(info->portwidth,addr,0x555,0xAA); - flash_cmd(info->portwidth,addr,0x2AA,0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (uchar *)(info->start[sect]); - flash_cmd(info->portwidth,addr,0,0x30); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - /* broken for 2x16: TODO */ - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - flash_cmd(info->portwidth,addr,0,0xf0); - flash_cmd(info->portwidth,addr,0,0xf0); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -/* broken for 2x16: TODO */ -int -write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - memcpy((void *)addr, src, cnt); - return 0; - } - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -/* broken for 2x16: TODO */ -static int -write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *addr = (uchar *)(info->start[0]); - ulong start; - int flag, i; - - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - *(unsigned long *)dest=data; - return 0; - } - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - unsigned short low = data & 0xffff; - unsigned short hi = (data >> 16) & 0xffff; - int ret = write_word_intel((bank_addr_t)dest, hi); - - if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low); - - return ret; - } - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* first, perform an unlock bypass command to speed up flash writes */ - addr[0x555] = 0xAA; - addr[0x2AA] = 0x55; - addr[0x555] = 0x20; - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - addr[0] = 0xA0; - *(((char *)dest)+i) = data_ch[i]; - udelay(10); /* XXX */ - } - - /* we're done, now do an unlock bypass reset */ - addr[0] = 0x90; - addr[0] = 0x00; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c deleted file mode 100644 index 8119fce..0000000 --- a/board/evb64260/i2c.c +++ /dev/null @@ -1,310 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <malloc.h> -#include <galileo/gt64260R.h> -#include <galileo/core.h> - -#define MAX_I2C_RETRYS 10 -#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ -#undef DEBUG_I2C - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -static void -i2c_init(int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualn = 0, actualm = 0; - unsigned int control, status; - unsigned int minmargin = 0xffffffff; - unsigned int tclk = 125000000; - - DP(puts("i2c_init\n")); - - for (n = 0 ; n < 8 ; n++) { - for (m = 0 ; m < 16 ; m++) { - power = 2 << n; /* power = 2^(n+1) */ - freq = tclk / (10 * (m + 1) * power); - if (speed > freq) - margin = speed - freq; - else - margin = freq - speed; - if (margin < minmargin) { - minmargin = margin; - actualn = n; - actualm = m; - } - } - } - - DP(puts("setup i2c bus\n")); - - /* Setup bus */ - - GT_REG_WRITE(I2C_SOFT_RESET, 0); - - DP(puts("udelay...\n")); - - udelay(I2C_DELAY); - - DP(puts("set baudrate\n")); - - GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualm << 3) | actualn); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - - udelay(I2C_DELAY * 10); - - DP(puts("read control, baudrate\n")); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - GT_REG_READ(I2C_CONTROL, &control); -} - -static uchar -i2c_start(void) -{ - unsigned int control, status; - int count = 0; - - DP(puts("i2c_start\n")); - - /* Set the start bit */ - - GT_REG_READ(I2C_CONTROL, &control); - control |= (0x1 << 5); - GT_REG_WRITE(I2C_CONTROL, control); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - - count = 0; - while ((status & 0xff) != 0x08) { - udelay(I2C_DELAY); - if (count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return status; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - return 0; -} - -static uchar -i2c_select_device(uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - int count = 0; - - DP(puts("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) - bits = 10; - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE(I2C_DATA, data); - /* assert the address */ - RESET_REG_BITS(I2C_CONTROL, BIT3); - - udelay(I2C_DELAY); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - udelay(I2C_DELAY); - if (count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return status; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - if (bits == 10) { - printf("10 bit I2C addressing not yet implemented\n"); - return 0xff; - } - - return 0; -} - -static uchar -i2c_get_data(uchar *return_data, int len) { - - unsigned int data, status = 0; - int count = 0; - - DP(puts("i2c_get_data\n")); - - while (len) { - - /* Get and return the data */ - - RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); - - udelay(I2C_DELAY * 5); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - udelay(I2C_DELAY); - if (count > 2) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return 0; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ(I2C_DATA, &data); - len--; - *return_data = (uchar)data; - return_data++; - } - RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3); - while ((status & 0xff) != 0x58) { - udelay(I2C_DELAY); - if (count > 200) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return status; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */ - - return 0; -} - -static uchar -i2c_write_data(unsigned int data, int len) -{ - unsigned int status; - int count = 0; - - DP(puts("i2c_write_data\n")); - - if (len > 4) - return -1; - - while (len) { - /* Set and assert the data */ - - GT_REG_WRITE(I2C_DATA, (unsigned int)data); - RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); - - udelay(I2C_DELAY); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay(I2C_DELAY); - if (count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return status; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - } - GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); - - udelay(I2C_DELAY * 10); - - return 0; -} - -static uchar -i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit) -{ - uchar status; - - DP(puts("i2c_set_dev_offset\n")); - - status = i2c_select_device(dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_write_data(offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} - -uchar -i2c_read(uchar dev_addr, unsigned int offset, int len, uchar *data, - int ten_bit) -{ - uchar status = 0; - unsigned int i2cfreq = 400000; - - DP(puts("i2c_read\n")); - - i2c_init(i2cfreq, 0); - - status = i2c_start(); - - if (status) { -#ifdef DEBUG_I2C - printf("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset(dev_addr, 0, 0); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to set offset: 0x%02x\n", status); -#endif - return status; - } - - i2c_init(i2cfreq, 0); - - status = i2c_start(); - if (status) { -#ifdef DEBUG_I2C - printf("Transaction restart failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_select_device(dev_addr, 1, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf("Address not acknowledged: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_get_data(data, len); - if (status) { -#ifdef DEBUG_I2C - printf("Data not received: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} diff --git a/board/evb64260/i2c.h b/board/evb64260/i2c.h deleted file mode 100644 index 9c21992..0000000 --- a/board/evb64260/i2c.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __I2C_H__ -#define __I2C_H__ - -/* function declarations */ -uchar i2c_read(uchar, unsigned int, int, uchar*, int); - -#endif diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c deleted file mode 100644 index 9acc3a0..0000000 --- a/board/evb64260/intel_flash.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00 - */ - -#include <common.h> -#include <mpc8xx.h> -#include <galileo/gt64260R.h> -#include <galileo/memory.h> -#include "intel_flash.h" - - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -static void -bank_reset(flash_info_t *info, int sect) -{ - bank_addr_t addrw, eaddrw; - - addrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(addrw); - - while (addrw < eaddrw) { -#ifdef FLASH_DEBUG - printf(" writing reset cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = BANK_CMD_RST; - addrw++; - } -} - -static void -bank_erase_init(flash_info_t *info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int flag; - -#ifdef FLASH_DEBUG - printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); - printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); - printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); - printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); - printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); - printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); - printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); -#endif - - saddrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(saddrw); - -#ifdef FLASH_DEBUG - printf("erasing sector %d, start addr = 0x%08lx " - "(bank next word addr = 0x%08lx)\n", sect, - (unsigned long)saddrw, (unsigned long)eaddrw); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts(); - - for (addrw = saddrw; addrw < eaddrw; addrw++) { -#ifdef FLASH_DEBUG - printf(" writing erase cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = BANK_CMD_ERASE1; - *addrw = BANK_CMD_ERASE2; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); -} - -static int -bank_erase_poll(flash_info_t *info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int sectdone, haderr; - - saddrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(saddrw); - - sectdone = 1; - haderr = 0; - - for (addrw = saddrw; addrw < eaddrw; addrw++) { - bank_word_t stat = *addrw; - -#ifdef FLASH_DEBUG - printf(" checking status at addr " - "0x%08x [0x%08x]\n", - (unsigned long)addrw, stat); -#endif - if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) - sectdone = 0; - else if ((stat & BANK_STAT_ERR) != 0) { - printf(" failed on sector %d " - "(stat = 0x%08x) at " - "address 0x%p\n", - sect, stat, addrw); - *addrw = BANK_CMD_CLR_STAT; - haderr = 1; - } - } - - if (haderr) - return (-1); - else - return (sectdone); -} - -int -write_word_intel(bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf("flash program failed (stat = 0x%08lx) " - "at address 0x%08lx\n", (ulong)stat, (ulong)addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -int -flash_erase_intel(flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - -#ifdef FLASH_DEBUG - printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info(info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sector%s will not be erased!\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init(info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer(start); - - do { - now = get_timer(start); - - if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll(info, sect); - - if (sectdone < 0) { - haderr = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset(info, sect); - } - } - return haderr; -} diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h deleted file mode 100644 index cc3a339..0000000 --- a/board/evb64260/intel_flash.h +++ /dev/null @@ -1,160 +0,0 @@ -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* - * acceptable chips types are: - * - * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A - */ - -/* register addresses, valid only following an CHIP_CMD_RD_ID command */ -#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ -#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ -#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ -#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ - -/* Commands */ -#define CHIP_CMD_RST 0xFF /* reset flash */ -#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ -#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define CHIP_CMD_PROG 0x40 /* program word command */ -#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ -#define CHIP_STAT_VPPS 0x08 /* VPP Status */ -#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ -#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ - CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) - -/* ID and Lock Configuration */ -#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ -#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID - -/* dimensions */ -#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ -#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ -#define CHIP_NBLOCKS 128 -#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ -#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * The hymod board has 2 x 28F320J5 chips running in - * 16 bit mode, for a 32 bit wide bank. - */ - -typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ -typedef volatile bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ - -#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ -#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ - -#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) -#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) -#define BANK_NBLOCKS CHIP_NBLOCKS -#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) -#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) - -#define MAX_BANKS 1 /* only one bank possible */ - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_WIDTH - 1))) -#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ - (bank_size_t)(s) + (BANK_WIDTH - 1))) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_BLKSZ - 1))) -#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ - (bank_size_t)(s) + (BANK_BLKSZ - 1))) - -/* align bank addresses and sizes to bank boundaries */ -#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_SIZE - 1))) -#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ - (bank_size_t)(s) + (BANK_SIZE - 1))) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o)) - -/* get base address of bank b, given flash base address a */ -#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - (bank_size_t)(b) * BANK_SIZE) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - BANK_WIDTH) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - BANK_BLKSZ) -#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - BANK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - ((bank_size_t)(r) << BANK_WSHIFT)) - -/* make a bank address for each chip register address */ - -#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) -#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) -#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) -#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the bank_word_t type, and take into account the - * chip width and bank layout - */ - -#define BANK_FILL_WORD(o) ((bank_word_t)(o)) - -/* make a bank word value for each chip cmd/stat/rd value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) - -/* ID and Lock Configuration */ -#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) -#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) -#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) diff --git a/board/evb64260/local.h b/board/evb64260/local.h deleted file mode 100644 index 8a3f4b2..0000000 --- a/board/evb64260/local.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * include/local.h - local configuration options, board specific - */ - -#ifndef __LOCAL_H -#define __LOCAL_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* This tells U-Boot that the config options are compiled in */ -/* #undef ENV_IS_EMBEDDED */ -/* Don't touch this! U-Boot figures this out based on other - * magic. */ - -/* Uncomment and define any of the below options */ - -/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ - /* Note: If you defined CONFIG_EVB64260_750CX this */ - /* gets defined automatically. */ - -/* These want string arguments */ -/* #define CONFIG_BOOTARGS */ -/* #define CONFIG_BOOTCOMMAND */ -/* #define CONFIG_RAMBOOTCOMMAND */ -/* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CONFIG_SYS_AUTOLOAD */ -/* #define CONFIG_PREBOOT */ - -/* These don't */ - -/* #define CONFIG_BOOTDELAY */ -/* #define CONFIG_BAUDRATE */ -/* #define CONFIG_LOADS_ECHO */ -/* #define CONFIG_ETHADDR */ -/* #define CONFIG_ETH2ADDR */ -/* #define CONFIG_ETH3ADDR */ -/* #define CONFIG_IPADDR */ -/* #define CONFIG_SERVERIP */ -/* #define CONFIG_ROOTPATH */ -/* #define CONFIG_GATEWAYIP */ -/* #define CONFIG_NETMASK */ -/* #define CONFIG_HOSTNAME */ -/* #define CONFIG_BOOTFILE */ -/* #define CONFIG_LOADADDR */ - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:11:22:33:44:55 - -/* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:11:22:33:44:66 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:11:22:33:44:77 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ diff --git a/board/evb64260/memory.c b/board/evb64260/memory.c deleted file mode 100644 index e339854..0000000 --- a/board/evb64260/memory.c +++ /dev/null @@ -1,457 +0,0 @@ -/* Memory.c - Memory mappings and remapping functions */ - -/* Copyright - Galileo technology. */ - -/* modified by Josh Huber to clean some things up, and - * fit it into the U-Boot framework */ - -#include <galileo/core.h> -#include <galileo/memory.h> - -/******************************************************************** -* memoryGetBankBaseAddress - Gets the base address of a memory bank -* - If the memory bank size is 0 then this base address has no meaning!!! -* -* -* INPUTS: MEMORY_BANK bank - The bank we ask for its base Address. -* OUTPUT: N/A -* RETURNS: Memory bank base address. -*********************************************************************/ -static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank) -{ - switch (bank) - { - case BANK0: - return SCS_0_LOW_DECODE_ADDRESS; - case BANK1: - return SCS_1_LOW_DECODE_ADDRESS; - case BANK2: - return SCS_2_LOW_DECODE_ADDRESS; - case BANK3: - return SCS_3_LOW_DECODE_ADDRESS; - } - return SCS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank) -{ - unsigned int base; - unsigned int regOffset=memoryGetBankRegOffset(bank); - - GT_REG_READ(regOffset,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* memoryGetDeviceBaseAddress - Gets the base address of a device. -* - If the device size is 0 then this base address has no meaning!!! -* -* -* INPUT: DEVICE device - The device we ask for its base address. -* OUTPUT: N/A -* RETURNS: Device base address. -*********************************************************************/ -static unsigned int memoryGetDeviceRegOffset(DEVICE device) -{ - switch (device) - { - case DEVICE0: - return CS_0_LOW_DECODE_ADDRESS; - case DEVICE1: - return CS_1_LOW_DECODE_ADDRESS; - case DEVICE2: - return CS_2_LOW_DECODE_ADDRESS; - case DEVICE3: - return CS_3_LOW_DECODE_ADDRESS; - case BOOT_DEVICE: - return BOOTCS_LOW_DECODE_ADDRESS; - } - return CS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetDeviceBaseAddress(DEVICE device) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset=memoryGetDeviceRegOffset(device); - - GT_REG_READ(regOffset, ®Base); - GT_REG_READ(regOffset+8, ®End); - - if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 20; - return regBase; -} - -/******************************************************************** -* memoryGetBankSize - Returns the size of a memory bank. -* -* -* INPUT: MEMORY_BANK bank - The bank we ask for its size. -* OUTPUT: N/A -* RETURNS: Memory bank size. -*********************************************************************/ -unsigned int memoryGetBankSize(MEMORY_BANK bank) -{ - unsigned int size,base; - unsigned int highValue; - unsigned int highAddress=memoryGetBankRegOffset(bank)+8; - - base = memoryGetBankBaseAddress(bank); - GT_REG_READ(highAddress,&highValue); - highValue = (highValue + 1) << 20; - if(base > highValue) - size=0; - else - size = highValue - base; - return size; -} - -/******************************************************************** -* memoryGetDeviceSize - Returns the size of a device memory space -* -* -* INPUT: DEVICE device - The device we ask for its base address. -* OUTPUT: N/A -* RETURNS: Size of a device memory space. -*********************************************************************/ -unsigned int memoryGetDeviceSize(DEVICE device) -{ - unsigned int size,base; - unsigned int highValue; - unsigned int highAddress=memoryGetDeviceRegOffset(device)+8; - - base = memoryGetDeviceBaseAddress(device); - GT_REG_READ(highAddress,&highValue); - if (highValue == 0xfff) - { - size = (~base) + 1; /* what the heck is this? */ - return size; - } - else - highValue = (highValue + 1) << 20; - - if(base > highValue) - size=0; - else - size = highValue - base; - return size; -} - -/******************************************************************** -* memoryGetDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width. -* The width is determine in registers: 'Device Parameters' -* registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device. -* at bits: [21:20]. -* -* INPUT: DEVICE device - Device number -* OUTPUT: N/A -* RETURNS: Device width in Bytes (1,2,4 or 8), 0 if error had occurred. -*********************************************************************/ -unsigned int memoryGetDeviceWidth(DEVICE device) -{ - unsigned int width; - unsigned int regValue; - - GT_REG_READ(DEVICE_BANK0PARAMETERS + device*4,®Value); - width = (regValue & 0x00300000) >> 20; - switch (width) - { - case 0: - return 1; - case 1: - return 2; - case 2: - return 4; - case 3: - return 8; - default: - return 0; - } -} - -bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength) -{ - unsigned int low=0xfff; - unsigned int high=0x0; - unsigned int regOffset=memoryGetBankRegOffset(bank); - - if(bankLength!=0) { - low = (bankBase >> 20) & 0xffff; - high=((bankBase+bankLength)>>20)-1; - } - -#ifdef DEBUG - { - unsigned int oldLow, oldHigh; - GT_REG_READ(regOffset,&oldLow); - GT_REG_READ(regOffset+8,&oldHigh); - - printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high); - } -#endif - - GT_REG_WRITE(regOffset,low); - GT_REG_WRITE(regOffset+8,high); - - return true; -} -bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength) -{ - /* TODO: what are appropriate "unmapped" values? */ - unsigned int low=0xfff; - unsigned int high=0x0; - unsigned int regOffset=memoryGetDeviceRegOffset(device); - - if(deviceLength != 0) { - low=deviceBase>>20; - high=((deviceBase+deviceLength)>>20)-1; - } else { - /* big problems in here... */ - /* this will HANG */ - } - - GT_REG_WRITE(regOffset,low); - GT_REG_WRITE(regOffset+8,high); - - return true; -} - - -/******************************************************************** -* memoryMapInternalRegistersSpace - Sets new base address for the internals -* registers. -* -* INPUTS: unsigned int internalRegBase - The new base address. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapInternalRegistersSpace(unsigned int internalRegBase) -{ - unsigned int currentValue; - unsigned int internalValue = internalRegBase; - - internalRegBase = (internalRegBase >> 20); - GT_REG_READ(INTERNAL_SPACE_DECODE,¤tValue); - internalRegBase = (currentValue & 0xffff0000) | internalRegBase; - GT_REG_WRITE(INTERNAL_SPACE_DECODE,internalRegBase); - INTERNAL_REG_BASE_ADDR = internalValue; - return true; -} - -/******************************************************************** -* memoryGetInternalRegistersSpace - Gets internal registers Base Address. -* -* INPUTS: unsigned int internalRegBase - The new base address. -* RETURNS: true on success, false on failure -*********************************************************************/ -unsigned int memoryGetInternalRegistersSpace(void) -{ - return INTERNAL_REG_BASE_ADDR; -} - -/******************************************************************** -* memorySetProtectRegion - This function modifys one of the 8 regions with -* one of the three protection mode. -* - Be advised to check the spec before modifying them. -* -* -* Inputs: CPU_PROTECT_REGION - one of the eight regions. -* CPU_ACCESS - general access. -* CPU_WRITE - read only access. -* CPU_CACHE_PROTECT - chache access. -* we defining CPU because there is another protect from the pci SIDE. -* Returns: false if one of the parameters is wrong and true else -*********************************************************************/ -bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memAccess, - MEMORY_ACCESS_WRITE memWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int protectHigh = baseAddress + regionLength; - - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,0x0000ffff); - GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,0); - return true; - } - baseAddress = (baseAddress & 0xfff00000) >> 20; - baseAddress = baseAddress | memAccess << 16 | memWrite << 17 - | cacheProtection << 18; - GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,baseAddress); - protectHigh = (protectHigh & 0xfff00000) >> 20; - GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,protectHigh - 1); - return true; -} - -/******************************************************************** -* memorySetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency. -* -* -* Inputs: SNOOP_REGION region - One of the four regions. -* SNOOP_TYPE snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* unsigned int baseAddress - Base Address of this region. -* unsigned int topAddress - Top Address of this region. -* Returns: false if one of the parameters is wrong and true else -*********************************************************************/ -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) ) - return false; - snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region; - snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region; - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); - GT_REG_WRITE(snoopXtopAddress,0); - return true; - } - baseAddress = baseAddress & 0xffff0000; - data = (baseAddress >> 16) | snoopType << 16; - GT_REG_WRITE(snoopXbaseAddress,data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); - return true; -} - -/******************************************************************** -* memoryRemapAddress - This fubction used for address remapping. -* -* -* Inputs: regOffset: remap register -* remapValue : -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue) -{ - unsigned int valueForReg; - valueForReg = (remapValue & 0xfff00000) >> 20; - GT_REG_WRITE(remapReg, valueForReg); - return true; -} - -/******************************************************************** -* memoryGetDeviceParam - This function used for getting device parameters from -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum) -{ - unsigned int valueOfReg; - unsigned int calcData; - - GT_REG_READ(DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg); - calcData = (0x7 & valueOfReg) + ((0x400000 & valueOfReg) >> 19); - deviceParam -> turnOff = calcData; /* Turn Off */ - - calcData = ((0x78 & valueOfReg) >> 3) + ((0x800000 & valueOfReg) >> 19); - deviceParam -> acc2First = calcData; /* Access To First */ - - calcData = ((0x780 & valueOfReg) >> 7) + ((0x1000000 & valueOfReg) >> 20); - deviceParam -> acc2Next = calcData; /* Access To Next */ - - calcData = ((0x3800 & valueOfReg) >> 11) + ((0x2000000 & valueOfReg) >> 22); - deviceParam -> ale2Wr = calcData; /* Ale To Write */ - - calcData = ((0x1c000 & valueOfReg) >> 14) + ((0x4000000 & valueOfReg) >> 23); - deviceParam -> wrLow = calcData; /* Write Active */ - - calcData = ((0xe0000 & valueOfReg) >> 17) + ((0x8000000 & valueOfReg) >> 24); - deviceParam -> wrHigh = calcData; /* Write High */ - - calcData = ((0x300000 & valueOfReg) >> 20); - switch (calcData) - { - case 0: - deviceParam -> deviceWidth = 1; /* one Byte - 8-bit */ - break; - case 1: - deviceParam -> deviceWidth = 2; /* two Bytes - 16-bit */ - break; - case 2: - deviceParam -> deviceWidth = 4; /* four Bytes - 32-bit */ - break; - case 3: - deviceParam -> deviceWidth = 8; /* eight Bytes - 64-bit */ - break; - default: - deviceParam -> deviceWidth = 1; - break; - } - return true; -} - -/******************************************************************** -* memorySetDeviceParam - This function used for setting device parameters to -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum) -{ - unsigned int valueForReg; - - if((deviceParam -> turnOff >= 0xf) || (deviceParam -> acc2First >= 0x1f) || - (deviceParam -> acc2Next >= 0x1f) || (deviceParam -> ale2Wr >= 0xf) || - (deviceParam -> wrLow >= 0xf) || (deviceParam -> wrHigh >= 0xf)) - return false; - valueForReg = (((deviceParam -> turnOff) & 0x7) | - (((deviceParam -> turnOff) & 0x8) << 19) | - (((deviceParam -> acc2First) & 0xf) << 3) | - (((deviceParam -> acc2First) & 0x10) << 19) | - (((deviceParam -> acc2Next) & 0xf) << 7) | - (((deviceParam -> acc2Next) & 0x10) << 20) | - (((deviceParam -> ale2Wr) & 0x7) << 11) | - (((deviceParam -> ale2Wr) & 0xf) << 22) | - (((deviceParam -> wrLow) & 0x7) << 14) | - (((deviceParam -> wrLow) & 0xf) << 23) | - (((deviceParam -> wrHigh) & 0x7) << 17) | - (((deviceParam -> wrHigh) & 0xf) << 24)); - /* insert the device width: */ - switch(deviceParam->deviceWidth) - { - case 1: - valueForReg = valueForReg | _8BIT; - break; - case 2: - valueForReg = valueForReg | _16BIT; - break; - case 4: - valueForReg = valueForReg | _32BIT; - break; - case 8: - valueForReg = valueForReg | _64BIT; - break; - default: - valueForReg = valueForReg | _8BIT; - break; - } - GT_REG_WRITE(DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg); - return true; -} diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S deleted file mode 100644 index f09528d..0000000 --- a/board/evb64260/misc.S +++ /dev/null @@ -1,182 +0,0 @@ -#include <config.h> -#include <74xx_7xx.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#include <galileo/gt64260R.h> - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CONFIG_SYS_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CONFIG_SYS_MONITOR_LEN@h - ori r8, r8, CONFIG_SYS_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CONFIG_SYS_DFL_GT_REGS@h - ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - rlwinm r7, r4, 12, 16, 31 - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 - stw r18, 0x0(r18) - sync - blr diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c deleted file mode 100644 index c9da57c..0000000 --- a/board/evb64260/mpsc.c +++ /dev/null @@ -1,838 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpsc.c - driver for console over the MPSC. - */ - -#include <common.h> -#include <config.h> -#include <asm/cache.h> - -#include <malloc.h> -#include "mpsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -int (*mpsc_putchar)(char ch) = mpsc_putchar_early; - -static volatile unsigned int *rx_desc_base=NULL; -static unsigned int rx_desc_index=0; -static volatile unsigned int *tx_desc_base=NULL; -static unsigned int tx_desc_index=0; - -/* local function declarations */ -static int galmpsc_connect(int channel, int connect); -static int galmpsc_route_serial(int channel, int connect); -static int galmpsc_route_rx_clock(int channel, int brg); -static int galmpsc_route_tx_clock(int channel, int brg); -static int galmpsc_write_config_regs(int mpsc, int mode); -static int galmpsc_config_channel_regs(int mpsc); -static int galmpsc_set_char_length(int mpsc, int value); -static int galmpsc_set_stop_bit_length(int mpsc, int value); -static int galmpsc_set_parity(int mpsc, int value); -static int galmpsc_enter_hunt(int mpsc); -static int galmpsc_set_brkcnt(int mpsc, int value); -static int galmpsc_set_tcschar(int mpsc, int value); -static int galmpsc_set_snoop(int mpsc, int value); -static int galmpsc_shutdown(int mpsc); - -static int galsdma_set_RFT(int channel); -static int galsdma_set_SFM(int channel); -static int galsdma_set_rxle(int channel); -static int galsdma_set_txle(int channel); -static int galsdma_set_burstsize(int channel, unsigned int value); -static int galsdma_set_RC(int channel, unsigned int value); - -static int galbrg_set_CDV(int channel, int value); -static int galbrg_enable(int channel); -static int galbrg_disable(int channel); -static int galbrg_set_clksrc(int channel, int value); -static int galbrg_set_CUV(int channel, int value); - -static void galsdma_enable_rx(void); - -/* static int galbrg_reset(int channel); */ - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - - -/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */ -#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->arch.mirror_hack[0])) - -#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);} -#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M) - -#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);} -#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i]) - -/* make sure this isn't bigger than 16 long words (u-boot.h) */ -struct _tag_mirror_hack { - unsigned GALMPSC_PROTOCONF_REG_M[2]; /* 8008 */ - unsigned GALMPSC_CHANNELREG_1_M[2]; /* 800c */ - unsigned GALMPSC_CHANNELREG_2_M[2]; /* 8010 */ - unsigned GALBRG_0_CONFREG_M[2]; /* b200 */ - - unsigned GALMPSC_ROUTING_REGISTER_M; /* b400 */ - unsigned GALMPSC_RxC_ROUTE_M; /* b404 */ - unsigned GALMPSC_TxC_ROUTE_M; /* b408 */ - - unsigned int baudrate; /* current baudrate, for tsc delay calc */ -}; - -/* static struct _tag_mirror_hack *mh = NULL; */ - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int -mpsc_putchar_early(char ch) -{ - int mpsc=CHANNEL; - int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - galmpsc_set_tcschar(mpsc,ch); - GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int -mpsc_putchar_sdma(char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset((void *)p, 0, 8 * sizeof(unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int)ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int)&p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int)&p[0]; - p[11] = (unsigned int)&p[12]; -#endif - - FLUSH_DCACHE(&p[0], &p[8]); - - GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&p[0]); - GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&p[0]); - - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE(&p[1], &p[2]); - - while(p[1] & DESC_OWNER) { - udelay(100); - INVALIDATE_DCACHE(&p[1], &p[2]); - } - - return 0; -} - -char mpsc_getchar (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2, - CHANNEL, GALMPSC_REG_GAP); - temp |= (1 << 23); - GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2, CHANNEL, - GALMPSC_REG_GAP, temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - -int -mpsc_test_char(void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index*8]; - - INVALIDATE_DCACHE(&p[1], &p[2]); - - if (p[1] & DESC_OWNER) return 0; - else return 1; -} - -int -mpsc_init(int baud) -{ - memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack)); - MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff; - - /* BRG CONFIG */ - galbrg_set_baudrate(CHANNEL, baud); -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */ -#else - galbrg_set_clksrc(CHANNEL,0); -#endif - galbrg_set_CUV(CHANNEL, 0); - galbrg_enable(CHANNEL); - - /* Set up clock routing */ - galmpsc_connect(CHANNEL, GALMPSC_CONNECT); - galmpsc_route_serial(CHANNEL, GALMPSC_CONNECT); - galmpsc_route_rx_clock(CHANNEL, CHANNEL); - galmpsc_route_tx_clock(CHANNEL, CHANNEL); - - /* reset MPSC state */ - galmpsc_shutdown(CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle(CHANNEL); - galsdma_set_rxle(CHANNEL); - galsdma_set_RC(CHANNEL, 0xf); - galsdma_set_SFM(CHANNEL); - galsdma_set_RFT(CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs(CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs(CHANNEL); - galmpsc_set_char_length(CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - -void -mpsc_init2(void) -{ - int i; - - mpsc_putchar = mpsc_putchar_sdma; - - /* RX descriptors */ - rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) * - sizeof(unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int)rx_desc_base+32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */ - rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */ - rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i*8] = 0x00100000; - } - rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0]; - - FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]); - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) * - sizeof(unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int)tx_desc_base+32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i*8 + 5] = (unsigned int)0x23232323; - tx_desc_base[i*8 + 4] = (unsigned int)0x23232323; - tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4]; - tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8]; - tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i*8] = 0x00010001; - } - tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0]; - - FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]); - - udelay(100); - - galsdma_enable_rx(); - - return; -} - -int -galbrg_set_baudrate(int channel, int rate) -{ - int clock; - - galbrg_disable(channel); - -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - /* from tclk */ - clock = (CONFIG_SYS_BUS_CLK/(16*rate)) - 1; -#else - clock = (3686400/(16*rate)) - 1; -#endif - - galbrg_set_CDV(channel, clock); - - galbrg_enable(channel); - - MIRROR_HACK->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int -galbrg_set_CDV(int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp); - - return 0; -} - -static int -galbrg_enable(int channel) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp |= 0x00010000; - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_disable(int channel) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp &= 0xFFFEFFFF; - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_set_clksrc(int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP); - temp &= 0xFF83FFFF; - temp |= (value << 18); - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_set_CUV(int channel, int value) -{ - GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int -galbrg_reset(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int -galsdma_set_RFT(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_SFM(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_rxle(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_txle(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_RC(int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_burstsize(int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int -galmpsc_connect(int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int -galmpsc_route_serial(int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX); - - if ((channel == 0) && connect) - temp |= 0x00000100; - else if ((channel == 1) && connect) - temp |= 0x00001000; - else if ((channel == 0) && !connect) - temp &= ~0x00000100; - else - temp &= ~0x00001000; - - GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp); - - return 0; -} - -static int -galmpsc_route_rx_clock(int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE); - - if (channel == 0) - temp |= brg; - else - temp |= (brg << 8); - - GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp); - - return 0; -} - -static int -galmpsc_route_tx_clock(int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE); - - if (channel == 0) - temp |= brg; - else - temp |= (brg << 8); - - GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp); - - return 0; -} - -static int -galmpsc_write_config_regs(int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int -galmpsc_config_channel_regs(int mpsc) -{ - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0); - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1); - GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt(mpsc, 0x3); - galmpsc_set_tcschar(mpsc, 0xab); - - return 0; -} - -static int -galmpsc_set_brkcnt(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_tcschar(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_char_length(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_stop_bit_length(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); - temp |= (value << 14); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp); - - return 0; -} - -static int -galmpsc_set_parity(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_enter_hunt(int mpsc) -{ - int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - temp |= 0x80000000; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); - - /* Should Poll on Enter Hunt bit, but the register is write-only */ - /* errata suggests pausing 100 system cycles */ - udelay(100); - - return 0; -} - - -static int -galmpsc_shutdown(int mpsc) -{ -#if 0 - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp); -#endif - - GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, - SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE(GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0); - - udelay(100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF, - 0x000000fc); - - udelay(100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - - udelay(100); - - return 0; -} - -static void -galsdma_enable_rx(void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt(CHANNEL); -} - -static int -galmpsc_set_snoop(int mpsc, int value) -{ - int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW; - int temp=GTREGREAD(reg); - if(value) - temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30); - else - temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30)); - GT_REG_WRITE(reg, temp); - return 0; -} diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h deleted file mode 100644 index 0747477..0000000 --- a/board/evb64260/mpsc.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include <galileo/gt64260R.h> - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_init2(void); -char mpsc_getchar(void); -int mpsc_test_char(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -extern int (*mpsc_putchar)(char ch); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c deleted file mode 100644 index 582f24c..0000000 --- a/board/evb64260/pci.c +++ /dev/null @@ -1,760 +0,0 @@ -/* PCI.c - PCI functions */ - -/* Copyright - Galileo technology. */ - -#include <common.h> -#include <pci.h> - -#include <galileo/pci.h> - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { -#ifdef CONFIG_ZUMA_V2 - {0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0}, - {0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0} -#else /* EVB??? This is a guess */ - {0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0}, - {0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0} -#endif -}; - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static unsigned int local_buses[] = { 0, 0 }; - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = PCI_BUS (pciDevNum); - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = PCI_BUS (pciDevNum); - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - if (pciDevNum == SELF) { /* This board */ - GT_REG_WRITE (pci_configuration_data[host], data); - } else { /* configuration Transaction over the pci. */ - - /* The PCI is working in LE Mode So it swap the Data. */ - GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data)); - } -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - if (pciDevNum == SELF) { /* This board */ - GT_REG_READ (pci_configuration_data[host], &data); - return data; - } else { /* The PCI is working in LE Mode So it swap the Data. */ - - GT_REG_READ (pci_configuration_data[host], &data); - return WORD_SWAP (data); - } -} - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 20) & 0xfff; - high = ((bankBase + bankLength) >> 20) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 20); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xfff) << 20; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - high &= 0xfff; - low &= 0xfff; - if (high <= low) - return 0; - return (high + 1 - low) << 20; -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + 4 * bank, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); -} - - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -/* - * - */ - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), value, - bus); - } - return 0; -} - -/* - * - */ - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - -#ifndef CONFIG_P3G4 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -#ifndef CONFIG_P3G4 - fixup_irq:gt_fixup_irq, -#endif - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -#ifndef CONFIG_P3G4 - fixup_irq:gt_fixup_irq, -#endif - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - -#ifndef CONFIG_P3G4 - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); -#endif - - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci0_hose.current_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - -#ifndef CONFIG_P3G4 - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); -#endif - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); -} diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c deleted file mode 100644 index 12b1308..0000000 --- a/board/evb64260/sdram_init.c +++ /dev/null @@ -1,650 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* sdram_init.c - automatic memory sizing */ - -#include <common.h> -#include <74xx_7xx.h> -#include <galileo/memory.h> -#include <galileo/pci.h> -#include <galileo/gt64260R.h> -#include <net.h> -#include <linux/compiler.h> - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64260.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* #define DEBUG */ -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#define GB (1 << 30) - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; - int size; /* detected size, not from I2C but from dram_size() */ -} sdram_info_t; - -#ifdef DEBUG -void dump_dimm_info (struct sdram_info *d) -{ - static const char *ecc_legend[] = { "", " Parity", " ECC" }; - - printf ("dimm%s %sDRAM: %dMibytes:\n", - ecc_legend[d->ecc], - d->registered ? "R" : "", (d->size >> 20)); - printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n", - d->drb_size, d->tpar, d->tras_clocks, d->burst_len, - d->banks, d->slot); -} -#endif - -static int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - - return 0; -} - -#ifdef MAP_PCI -static int -memory_map_bank_pci (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ - PCI_HOST host; - - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } - return 0; -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -#ifdef CONFIG_ZUMA_V2 -static int check_dimm (uchar slot, sdram_info_t * info) -{ - /* assume 2 dimms, 2 banks each 256M - we dont have an - * dimm i2c so rely on the detection routines later */ - - memset (info, 0, sizeof (*info)); - - info->slot = slot; - info->banks = 2; /* Detect later */ - info->registered = 0; - info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit - but doesn't matter, both do same - thing in setup_sdram() */ - info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -#ifdef CONFIG_ECC - info->ecc = 0; /* Detect later */ -#endif /* CONFIG_ECC */ - return 0; -} - -#elif defined(CONFIG_P3G4) - -static int check_dimm (uchar slot, sdram_info_t * info) -{ - memset (info, 0, sizeof (*info)); - - if (slot) - return 0; - - info->slot = slot; - info->banks = 1; - info->registered = 0; - info->drb_size = 4; - info->tpar = 3; - info->tras_clocks = 6; - info->burst_len = 4; -#ifdef CONFIG_ECC - info->ecc = 2; -#endif - return 0; -} - -#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */ - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -static int check_dimm (uchar slot, sdram_info_t * info) -{ - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - uchar rows, cols, sdram_banks, supp_cal, width, cal_val; - ulong tmemclk; - uchar trp_clocks, trcd_clocks; - uchar data[128]; - - get_clocks (); - - tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */ - -#ifdef CONFIG_EVB64260_750CX - if (0 != slot) { - printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,"); - printf (" called with slot=%d insetad!\n", slot); - return 0; - } -#endif - DP (puts ("before i2c read\n")); - - ret = i2c_read (addr, 0, 128, data, 0); - - DP (puts ("after i2c read\n")); - - /* zero all the values */ - memset (info, 0, sizeof (*info)); - - if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); - return 0; - } - - /* first, do some sanity checks */ - if (data[2] != 0x4) { - printf ("Not SDRAM in slot %d\n", slot); - return 0; - } - - /* get various information */ - rows = data[3]; - cols = data[4]; - info->banks = data[5]; - sdram_banks = data[17]; - width = data[13] & 0x7f; - - DP (printf - ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks)); - - /* check if the memory is registered */ - if (data[21] & (BIT1 | BIT4)) - info->registered = 1; - -#ifdef CONFIG_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - info->ecc = (data[11] & 2) >> 1; -#endif - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (data[18] & 0x6) >> 1; - - /* compute the relevant clock values */ - trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk; - trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk; - info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk; - - DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n", - trp_clocks, trcd_clocks, info->tras_clocks)); - - /* try a CAS latency of 3 first... */ - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - DP (printf ("cal_val = %d\n", cal_val)); - - /* bummer, did't work... */ - if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); - return 0; - } - - /* get the largest delay -- these values need to all be the same - * see Res#6 */ - info->tpar = cal_val; - if (trp_clocks > info->tpar) - info->tpar = trp_clocks; - if (trcd_clocks > info->tpar) - info->tpar = trcd_clocks; - - DP (printf ("tpar set to: %d\n", info->tpar)); - -#ifdef CONFIG_SYS_BROKEN_CL2 - if (info->tpar == 2) { - info->tpar = 3; - DP (printf ("tpar fixed-up to: %d\n", info->tpar)); - } -#endif - /* compute the module DRB size */ - info->drb_size = - (((1 << (rows + cols)) * sdram_banks) * width) / _16M; - - DP (printf ("drb_size set to: %d\n", info->drb_size)); - - /* find the burst len */ - info->burst_len = data[16] & 0xf; - if ((info->burst_len & 8) == 8) { - info->burst_len = 1; - } else if ((info->burst_len & 4) == 4) { - info->burst_len = 0; - } else { - return 0; - } - - info->slot = slot; - return 0; -} -#endif /* ! CONFIG_ZUMA_V2 */ - -static int setup_sdram_common (sdram_info_t info[2]) -{ - ulong tmp; - int tpar = 2, tras_clocks = 5, registered = 1; - __maybe_unused int ecc = 2; - - if (!info[0].banks && !info[1].banks) - return 0; - - if (info[0].banks) { - if (info[0].tpar > tpar) - tpar = info[0].tpar; - if (info[0].tras_clocks > tras_clocks) - tras_clocks = info[0].tras_clocks; - if (!info[0].registered) - registered = 0; - if (info[0].ecc != 2) - ecc = 0; - } - - if (info[1].banks) { - if (info[1].tpar > tpar) - tpar = info[1].tpar; - if (info[1].tras_clocks > tras_clocks) - tras_clocks = info[1].tras_clocks; - if (!info[1].registered) - registered = 0; - if (info[1].ecc != 2) - ecc = 0; - } - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIGURATION); - - /* Turn on physical interleave if both DIMMs - * have even numbers of banks. */ - if ((info[0].banks == 0 || info[0].banks == 2) && - (info[1].banks == 0 || info[1].banks == 2)) { - /* physical interleave on */ - tmp &= ~(1 << 15); - } else { - /* physical interleave off */ - tmp |= (1 << 15); - } - - tmp |= (registered << 17); - - /* Use buffer 1 to return read data to the CPU - * See Res #12 */ - tmp |= (1 << 26); - - GT_REG_WRITE (SDRAM_CONFIGURATION, tmp); - DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION))); - - /* SDRAM timing */ - tmp = (((tpar == 3) ? 2 : 1) | - (((tpar == 3) ? 2 : 1) << 2) | - (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8)); - -#ifdef CONFIG_ECC - /* Setup ECC */ - if (ecc == 2) - tmp |= 1 << 13; -#endif /* CONFIG_ECC */ - - GT_REG_WRITE (SDRAM_TIMING, tmp); - DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n", - GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks)); - - /* SDRAM address decode register */ - /* program this with the default value */ - GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2); - DP (printf ("SDRAM decode: %08x\n", - GTREGREAD (SDRAM_ADDRESS_DECODE))); - - return 0; -} - -/* sets up the GT properly with information passed in */ -static int setup_sdram (sdram_info_t * info) -{ - ulong tmp; - ulong *addr = 0; - __maybe_unused ulong check; - int i; - - /* sanity checking */ - if (!info->banks) - return 0; - - /* ---------------------------- */ - /* Program the GT with the discovered data */ - - /* bank parameters */ - tmp = (0xf << 16); /* leave all virt bank pages open */ - - DP (printf ("drb_size: %d\n", info->drb_size)); - switch (info->drb_size) { - case 1: - tmp |= (1 << 14); - break; - case 4: - case 8: - tmp |= (2 << 14); - break; - case 16: - case 32: - tmp |= (3 << 14); - break; - default: - printf ("Error in dram size calculation\n"); - return 1; - } - - /* SDRAM bank parameters */ - /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ - GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp); - GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp); - DP (printf - ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, - info->slot * 2, (info->slot * 2) + 1, tmp)); - - /* set the SDRAM configuration for each bank */ - for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) { - DP (printf ("*** Running a MRS cycle for bank %d ***\n", i)); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ - GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3); - check = GTREGREAD (SDRAM_OPERATION_MODE); - - /* dummy write */ - *addr = 0; - - /* wait for the command to complete */ - while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0); - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION_MODE, 0); - check = GTREGREAD (SDRAM_OPERATION_MODE); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - DP (printf ("*** MRS cycle for bank %d done ***\n", i)); - } - - return 0; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* U-Boot interface function to SDRAM init - this is where all the - * controlling logic happens */ -phys_size_t initdram (int board_type) -{ - ulong checkbank[4] = {[0 ... 3] = 0 }; - int bank_no; - ulong total; - int nhr; - sdram_info_t dimm_info[2]; - - - /* first, use the SPD to get info about the SDRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SDRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - check_dimm (0, &dimm_info[0]); - - /* DIMM1 */ -#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */ - check_dimm (1, &dimm_info[1]); -#else /* CONFIG_EVB64260_750CX */ - memset (&dimm_info[1], 0, sizeof (sdram_info_t)); -#endif - - /* unmap all banks */ - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* Now, program the GT with the correct values */ - if (setup_sdram_common (dimm_info)) { - printf ("Setup common failed.\n"); - } - - if (setup_sdram (&dimm_info[0])) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (setup_sdram (&dimm_info[1])) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - total = 0; - if (dimm_info[0].banks > 0) - checkbank[0] = 1; - if (dimm_info[0].banks > 1) - checkbank[1] = 1; - if (dimm_info[0].banks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - if (dimm_info[1].banks > 0) - checkbank[2] = 1; - if (dimm_info[1].banks > 1) - checkbank[3] = 1; - if (dimm_info[1].banks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - /* Generic dram sizer: works even if we don't have i2c DIMMs, - * as long as the timing settings are more or less correct */ - - /* - * pass 1: size all the banks, using first bat (0-256M) - * limitation: we only support 256M per bank due to - * us only having 1 BAT for all DRAM - */ - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - DP (printf ("checking bank %d\n", bank_no)); - - memory_map_bank (bank_no, 0, GB / 4); - checkbank[bank_no] = dram_size (NULL, GB / 4); - memory_map_bank (bank_no, 0, 0); - - DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no])); - } - - /* - * pass 2: contiguously map each bank into physical address - * space. - */ - dimm_info[0].banks = dimm_info[1].banks = 0; - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - if (!checkbank[bank_no]) - continue; - - dimm_info[bank_no / 2].banks++; - dimm_info[bank_no / 2].size += checkbank[bank_no]; - - memory_map_bank (bank_no, total, checkbank[bank_no]); -#ifdef MAP_PCI - memory_map_bank_pci (bank_no, total, checkbank[bank_no]); -#endif - total += checkbank[bank_no]; - } - -#ifdef CONFIG_ECC -#ifdef CONFIG_ZUMA_V2 - /* - * We always enable ECC when bank 2 and 3 are unpopulated - * If we 2 or 3 are populated, we CAN'T support ECC. - * (Zuma boards only support ECC in banks 0 and 1; assume that - * in that configuration, ECC chips are mounted, even for stacked - * chips) - */ - if (checkbank[2] == 0 && checkbank[3] == 0) { - dimm_info[0].ecc = 2; - GT_REG_WRITE (SDRAM_TIMING, - GTREGREAD (SDRAM_TIMING) | (1 << 13)); - /* TODO: do we have to run MRS cycles again? */ - } -#endif /* CONFIG_ZUMA_V2 */ - - if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) { - puts ("[ECC] "); - } -#endif /* CONFIG_ECC */ - -#ifdef DEBUG - dump_dimm_info (&dimm_info[0]); - dump_dimm_info (&dimm_info[1]); -#endif - /* TODO: return at MOST 256M? */ - /* return total > GB/4 ? GB/4 : total; */ - return total; -} diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c deleted file mode 100644 index 83a4217..0000000 --- a/board/evb64260/serial.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * serial.c - serial support for the gal ev board - */ - -/* supports both the 16650 duart and the MPSC */ - -#include <common.h> -#include <command.h> -#include <galileo/memory.h> -#include <serial.h> -#include <linux/compiler.h> - -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) -#include <ns16550.h> -#endif - -#include "mpsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) -const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1, - (NS16550_t) CONFIG_SYS_NS16550_COM2 }; -#endif - -#ifdef CONFIG_MPSC - -static int evb64260_serial_init(void) -{ -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; -#endif - - mpsc_init(gd->baudrate); - - /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CONFIG_SYS_INIT_CHAN1 - NS16550_reinit(COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif - return (0); -} - -static void evb64260_serial_putc(const char c) -{ - if (c == '\n') - mpsc_putchar('\r'); - - mpsc_putchar(c); -} - -static int evb64260_serial_getc(void) -{ - return mpsc_getchar(); -} - -static int evb64260_serial_tstc(void) -{ - return mpsc_test_char(); -} - -static void evb64260_serial_setbrg(void) -{ - galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate); -} - -#else /* ! CONFIG_MPSC */ - -static int evb64260_serial_init(void) -{ - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - (void)NS16550_init(COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - (void)NS16550_init(COM_PORTS[1], clock_divisor); -#endif - - return (0); -} - -static void evb64260_serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - - NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c); -} - -static int evb64260_serial_getc(void) -{ - return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -static int evb64260_serial_tstc(void) -{ - return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -static void evb64260_serial_setbrg(void) -{ - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - NS16550_reinit(COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif -} - -#endif /* CONFIG_MPSC */ - -static struct serial_device evb64260_serial_drv = { - .name = "evb64260_serial", - .start = evb64260_serial_init, - .stop = NULL, - .setbrg = evb64260_serial_setbrg, - .putc = evb64260_serial_putc, - .puts = default_serial_puts, - .getc = evb64260_serial_getc, - .tstc = evb64260_serial_tstc, -}; - -void evb64260_serial_initialize(void) -{ - serial_register(&evb64260_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &evb64260_serial_drv; -} - -#if defined(CONFIG_CMD_KGDB) -void -kgdb_serial_init(void) -{ -} - -void -putDebugChar (int c) -{ - serial_putc (c); -} - -void -putDebugStr (const char *str) -{ - serial_puts (str); -} - -int -getDebugChar (void) -{ - return serial_getc(); -} - -void -kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds deleted file mode 100644 index 712df6d..0000000 --- a/board/evb64260/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/74xx_7xx/start.o (.text*) - *(.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c deleted file mode 100644 index aa15fa0..0000000 --- a/board/evb64260/zuma_pbb.c +++ /dev/null @@ -1,220 +0,0 @@ -#include <common.h> -#include <malloc.h> - -#if defined(CONFIG_CMD_BSP) -#include <command.h> -#endif - -#include <pci.h> -#include <galileo/pci.h> -#include "zuma_pbb.h" - -#undef DEBUG - -#define PAT_LO 0x00010203 -#define PAT_HI 0x04050607 - -static PBB_DMA_REG_MAP *zuma_pbb_reg = NULL; -static char test_buf1[2048]; -static char test_buf2[2048]; -void zuma_init_pbb(void); -int zuma_mbox_init(void); -int zuma_test_dma(int cmd, int size); - -int zuma_test_dma (int cmd, int size) -{ - static const char *const test_legend[] = { - "write", "verify", - "copy", "compare", - "write inc", "verify inc" - }; - register int i, j; - unsigned int p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff); - unsigned int p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff); - volatile unsigned int *ps = (unsigned int *) p1; - volatile unsigned int *pd = (unsigned int *) p2; - unsigned int funct, pat_lo = PAT_LO, pat_hi = PAT_HI; - DMA_INT_STATUS stat; - int ret = 0; - - if (!zuma_pbb_reg) { - printf ("not initted\n"); - return -1; - } - - if (cmd < 0 || cmd > 5) { - printf ("inv cmd %d\n", cmd); - return -1; - } - - if (cmd == 2 || cmd == 3) { - /* not implemented */ - return 0; - } - - if (size <= 0 || size > 1024) - size = 1024; - - size &= (~7); /* throw away bottom 3 bits */ - - p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff); - p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff); - - memset ((void *) p1, 0, size); - memset ((void *) p2, 0, size); - - for (i = 0; i < size / 4; i += 2) { - ps[i] = pat_lo; - ps[i + 1] = pat_hi; - if (cmd == 4 || cmd == 5) { - unsigned char *pl = (unsigned char *) &pat_lo; - unsigned char *ph = (unsigned char *) &pat_hi; - - for (j = 0; j < 4; j++) { - pl[j] += 8; - ph[j] += 8; - } - } - } - - funct = (1 << 31) | (cmd << 24) | (size); - - zuma_pbb_reg->int_mask.pci_bits.chan0 = - EOF_RX_FLAG | EOF_TX_FLAG | EOB_TX_FLAG; - - zuma_pbb_reg->debug_57 = PAT_LO; /* patl */ - zuma_pbb_reg->debug_58 = PAT_HI; /* path */ - - zuma_pbb_reg->debug_54 = cpu_to_le32 (p1); /* src 0x01b0 */ - zuma_pbb_reg->debug_55 = cpu_to_le32 (p2); /* dst 0x01b8 */ - zuma_pbb_reg->debug_56 = cpu_to_le32 (funct); /* func, 0x01c0 */ - - /* give DMA time to chew on things.. dont use DRAM or PCI */ - /* if you can avoid it. */ - do { - for (i = 0; i < 1000 * 10; i++); - } while (le32_to_cpu (zuma_pbb_reg->debug_56) & (1 << 31)); - - stat.word = zuma_pbb_reg->status.word; - zuma_pbb_reg->int_mask.word = 0; - - printf ("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0); - - printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56)); - printf ("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2], - ps[3]); - printf ("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2], - pd[3]); - printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56)); - - - if (cmd == 0 || cmd == 4) { - /* this is a write */ - if (!(stat.pci_bits.chan0 & EOF_RX_FLAG) || /* not done */ - (memcmp ((void *) ps, (void *) pd, size) != 0)) { /* cmp error */ - for (i = 0; i < size / 4; i += 2) { - if ((ps[i] != pd[i]) || (ps[i + 1] != pd[i + 1])) { - printf ("s @%p:%08x %08x\n", &ps[i], ps[i], ps[i + 1]); - printf ("d @%p:%08x %08x\n", &pd[i], pd[i], pd[i + 1]); - } - } - ret = -1; - } - } else { - /* this is a verify */ - if (!(stat.pci_bits.chan0 & EOF_TX_FLAG) || /* not done */ - (stat.pci_bits.chan0 & EOB_TX_FLAG)) { /* cmp error */ - printf ("%08x: %08x %08x\n", - le32_to_cpu (zuma_pbb_reg->debug_63), - zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62); - ret = -1; - } - } - - printf ("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size, - (ret == 0) ? "PASSED" : "FAILED"); - return 0; -} - -void zuma_init_pbb (void) -{ - unsigned int iobase; - pci_dev_t dev = - pci_find_device (VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); - - if (dev == -1) { - printf ("no zuma pbb\n"); - return; - } - - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase); - - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - - zuma_pbb_reg = (PBB_DMA_REG_MAP *)iobase; - - - if (!zuma_pbb_reg) { - printf ("zuma pbb bar none! (hah hah, get it?)\n"); - return; - } - - zuma_pbb_reg->int_mask.word = 0; - - printf ("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg, - zuma_pbb_reg->version.pci_bits.rev_major, - zuma_pbb_reg->version.pci_bits.rev_minor, - zuma_pbb_reg->timestamp); - -} - -#if defined(CONFIG_CMD_BSP) - -static int last_cmd = 4; /* write increment */ -static int last_size = 64; - -int -do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - zuma_init_pbb (); - return 0; -} - -int -do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc > 1) { - last_cmd = simple_strtoul (argv[1], NULL, 10); - } - if (argc > 2) { - last_size = simple_strtoul (argv[2], NULL, 10); - } - zuma_test_dma (last_cmd, last_size); - return 0; -} - -int -do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - zuma_mbox_init (); - return 0; -} - -U_BOOT_CMD( - zinit, 1, 0, do_zuma_init_pbb, - "init zuma pbb", - "\n" -); -U_BOOT_CMD( - zdtest, 3, 1, do_zuma_test_dma, - "run dma test", - "[cmd [count]]\n" - " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes" -); -U_BOOT_CMD( - zminit, 1, 0, do_zuma_init_mbox, - "init zuma mbox", - "\n" -); - -#endif diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h deleted file mode 100644 index 300b2fe..0000000 --- a/board/evb64260/zuma_pbb.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef ZUMA_PBB_H -#define ZUMA_PBB_H - -#define MAX_NUM_BUFFER_PER_RING 32 - -#ifdef __BIG_ENDIAN -#define cpu_bits _be_s_bits /* use with le32_to_cpu only */ -#define pci_bits _be_bits /* may contain swapped bytes, - but dont need le32_to_cpu */ -#endif - -#ifdef __LITTLE_ENDIAN -#define cpu_bits _le_bits -#define pci_bits _le_bits -#endif - -#define VENDOR_ID_ZUMA 0x1172 -#define DEVICE_ID_ZUMA_PBB 0x0004 - -#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */ -#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */ -#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */ -#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */ - -#define PBB_DMA_OWN_BIT 0x80000000 -#define PBB_DMA_LAST_BIT 0x40000000 - -#define EOF_RX_FLAG 1 /* bit 0 */ -#define EOB_RX_FLAG 2 /* bit 1 */ -#define EOF_TX_FLAG 4 /* bit 2 */ -#define EOB_TX_FLAG 8 /* bit 3 */ - -#define TX_MODE(m) (((m)&7) << 16) - -#define RX_DESC(i) (cs->rx_desc[i]) -#define TX_DESC(i) (cs->tx_desc[i]) - -#define RX_CONTROL(i) (RX_DESC(i).control.word) -#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size) -#define TX_CONTROL(i) (TX_DESC(i).control.word) - -#define RX_DATA_P(i) (&RX_DESC(i).ptr) -#define TX_DATA_P(i) (&TX_DESC(i).ptr) - -typedef volatile unsigned char V8; -typedef volatile unsigned short V16; -typedef volatile unsigned int V32; - -/* RAM descriptor layout */ -typedef struct _tag_dma_descriptor { - V32 ptr; - union { - struct { - V32 owner:1; - V32 last:1; - V32 reserved0: 10; - V32 tx_mode: 4; - - V32 reserved1: 5; - V32 size: 11; - } tx; - struct { - V32 owner:1; - V32 last:1; - V32 reserved0: 14; - - V32 reserved1: 5; - V32 size: 11; - } rx; - V32 word; - } control; -} DMA_DESCRIPTOR; - -/* - * NOTE: DO NOT USE structure to write non-word values... all registers - * MUST be written 4 bytes at a time in SI version 0. - * Non-word writes will result in "unaccessed" bytes written as zero. - * - * Byte reads are allowed. - * - * V32 pads are because the registers are spaced every 8 bytes (64 bits) - * - */ - -/* NOTE!!! 4 dwords */ -typedef struct _tag_dma_descriptor_ring { - DMA_DESCRIPTOR *base; - V32 pad1; /* skip high dword */ - volatile DMA_DESCRIPTOR *current; - V32 pad3; /* skip high dword */ -} DMA_DESCRIPTOR_RING; - -/* 1 dword */ -typedef union _tag_dma_generic { - struct { /* byte 3 2 1 0 */ - V32 chan7:4; /* bits 31-28 */ - V32 chan6:4; /* bits 27-24 */ - V32 chan5:4; /* bits 23-20 */ - V32 chan4:4; /* bits 19-16 */ - V32 chan3:4; /* bits 15-12 */ - V32 chan2:4; /* bits 11-8 */ - V32 chan1:4; /* bits 7-4 */ - V32 chan0:4; /* bits 3-0 */ - } _be_s_bits; - struct { /* byte 0 1 2 3 */ - V32 chan1:4; /* bits 7-4 */ - V32 chan0:4; /* bits 3-0 */ - V32 chan3:4; /* bits 15-12 */ - V32 chan2:4; /* bits 11-8 */ - V32 chan5:4; /* bits 23-20 */ - V32 chan4:4; /* bits 19-16 */ - V32 chan7:4; /* bits 31-28 */ - V32 chan6:4; /* bits 27-24 */ - } _be_bits; - struct { /* byte 0 1 2 3 */ - V32 chan0:4; /* bits 0-3 */ - V32 chan1:4; /* bits 4-7 */ - V32 chan2:4; /* bits 8-11 */ - V32 chan3:4; /* bits 12-15 */ - V32 chan4:4; /* bits 16-19 */ - V32 chan5:4; /* bits 20-23 */ - V32 chan6:4; /* bits 24-27 */ - V32 chan7:4; /* bits 28-31 */ - } _le_bits; - V8 byte[4]; - V32 word; -} DMA_RXTX_ENABLE, DMA_RX_DELETE, - DMA_INT_STATUS, DMA_INT_MASK, - DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK; - -/* 1 dword */ -typedef union _tag_dma_rx_timer{ - struct { - V32 res0:8; /* bits 32-24 */ - V32 res1:7; /* bits 23-17 */ - V32 enable:1; /* bit 16 */ - V32 value:16; /* bits 15-0 */ - } _be_s_bits; - struct { - /* crosses byte boundary. must use swap. */ - V32 s_value:16; /* bits 7-0,15-8 */ - V32 enable:1; /* bit 16 */ - V32 res1:7; /* bits 23-17 */ - V32 res0:8; /* bits 32-24 */ - } _be_bits; - struct { - V32 value:16; /* bits 0-15 */ - V32 enable:1; /* bit 16 */ - V32 res1:7; /* bits 17-23 */ - V32 res0:8; /* bits 24-32 */ - } _le_bits; - V8 byte[4]; - V32 word; -} DMA_RX_TIMER; - -/* NOTE!!!: 2 dwords */ -typedef struct _tag_dma_desc_level{ - union { - struct { - V32 res1:8; /* bits 31-24 */ - V32 res0:7; /* bits 23-17 */ - V32 write:1; /* bit 16 */ - V32 thresh:8; /* bits 15-8 */ - V32 level:8; /* bits 7-0 */ - } _be_s_bits; - struct { - V32 level:8; /* bits 7-0 */ - V32 thresh:8; /* bits 15-8 */ - V32 res0:7; /* bits 30-17 */ - V32 write:1; /* bit 16 */ - V32 res1:8; /* bits 31-24 */ - } _be_bits; - struct { - V32 level:8; /* bits 0-7 */ - V32 thresh:8; /* bits 8-15 */ - V32 write:1; /* bit 16 */ - V32 res0:7; /* bit 17-30 */ - V32 res1:8; /* bits 24-31 */ - } _le_bits; - V8 byte[4]; - V32 word; - } desc; - V32 pad1; -} DMA_DESC_LEVEL; - -typedef struct _tag_pbb_dma_reg_map { - /* 0-15 (0x000-0x078) */ - DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */ - - /* 16-31 (0x080-0x0f8) */ - DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */ - - /* 32/33 (0x100/0x108) */ - V32 reserved_32; - V32 pad_32; - V32 reserved_33; - V32 pad_33; - - /* 34 (0x110) */ - DMA_RXTX_ENABLE rxtx_enable; - V32 pad_34; - - /* 35 (0x118) */ - DMA_RX_DELETE rx_delete; - V32 pad_35; - - /* 36-38 (0x120-0x130) */ - DMA_INT_STATUS status; - V32 pad_36; - DMA_INT_STATUS last_status; - V32 pad_37; - DMA_INT_MASK int_mask; - V32 pad_38; - - /* 39/40 (0x138/0x140) */ - union { - /* NOTE!! 4 dwords */ - struct { - V32 channel_3:8; - V32 channel_2:8; - V32 channel_1:8; - V32 channel_0:8; - V32 pad1; - V32 channel_7:8; - V32 channel_6:8; - V32 channel_5:8; - V32 channel_4:8; - V32 pad3; - } _be_s_bits; - struct { - V32 channel_0:8; - V32 channel_1:8; - V32 channel_2:8; - V32 channel_3:8; - V32 pad1; - V32 channel_4:8; - V32 channel_5:8; - V32 channel_6:8; - V32 channel_7:8; - V32 pad3; - } _be_bits, _le_bits; - V8 byte[16]; - V32 word[4]; - } rx_size; - - /* 41/42 (0x148/0x150) */ - V32 reserved_41; - V32 pad_41; - V32 reserved_42; - V32 pad_42; - - /* 43/44 (0x158/0x160) */ - DMA_RX_LEVEL_STATUS rx_level_status; - V32 pad_43; - DMA_RX_LEVEL_INT_MASK rx_level_int_mask; - V32 pad_44; - - /* 45 (0x168) */ - DMA_RX_TIMER rx_timer; - V32 pad_45; - - /* 46 (0x170) */ - V32 reserved_46; - V32 pad_46; - - /* 47 (0x178) */ - V32 mbox_status; - V32 pad_47; - - /* 48/49 (0x180/0x188) */ - V32 mbox_out; - V32 pad_48; - V32 mbox_in; - V32 pad_49; - - /* 50 (0x190) */ - V32 config; - V32 pad_50; - - /* 51/52 (0x198/0x1a0) */ - V32 c2a_ctr; - V32 pad_51; - V32 a2c_ctr; - V32 pad_52; - - /* 53 (0x1a8) */ - union { - struct { - V32 rev_major:8; /* bits 31-24 */ - V32 rev_minor:8; /* bits 23-16 */ - V32 reserved:16; /* bits 15-0 */ - } _be_s_bits; - struct { - V32 s_reserved:16; /* bits 7-0, 15-8 */ - V32 rev_minor:8; /* bits 23-16 */ - V32 rev_major:8; /* bits 31-24 */ - } _be_bits; - struct { - V32 reserved:16; /* bits 0-15 */ - V32 rev_minor:8; /* bits 16-23 */ - V32 rev_major:8; /* bits 24-31 */ - } _le_bits; - V8 byte[4]; - V32 word; - } version; - V32 pad_53; - - /* 54-59 (0x1b0-0x1d8) */ - V32 debug_54; - V32 pad_54; - V32 debug_55; - V32 pad_55; - V32 debug_56; - V32 pad_56; - V32 debug_57; - V32 pad_57; - V32 debug_58; - V32 pad_58; - V32 debug_59; - V32 pad_59; - - /* 60 (0x1e0) */ - V32 timestamp; - V32 pad_60; - - /* 61-63 (0x1e8-0x1f8) */ - V32 debug_61; - V32 pad_61; - V32 debug_62; - V32 pad_62; - V32 debug_63; - V32 pad_63; - - /* 64-71 (0x200 - 0x238) */ - DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */ - - /* 72-98 (0x240 - 0x2f8) */ - /* reserved */ - - /* 96-127 (0x300 - 0x3f8) */ - /* mirrors (0x100 - 0x1f8) */ - -} PBB_DMA_REG_MAP; - - -#endif /* ZUMA_PBB_H */ diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c deleted file mode 100644 index 621c64c..0000000 --- a/board/evb64260/zuma_pbb_mbox.c +++ /dev/null @@ -1,208 +0,0 @@ -#include <common.h> -#include <galileo/pci.h> -#include <net.h> -#include <pci.h> - -#include "zuma_pbb.h" -#include "zuma_pbb_mbox.h" - - -struct _zuma_mbox_dev zuma_mbox_dev; - - -static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data) -{ - unsigned int status, count = 0, i; - - status = (volatile int) le32_to_cpu(dev->sip->mbox_status); - - while ((status & OUT_PENDING) && count < 1000) { - count++; - for (i = 0; i < 1000; i++) - ; - status = (volatile int) le32_to_cpu(dev->sip->mbox_status); - } - if (count < 1000) { - /* if SET it means msg pending */ - /* printf("mbox real write %08x\n",data); */ - dev->sip->mbox_out = cpu_to_le32(data); - return 4; - } - - printf("mbox tx timeout\n"); - return 0; -} - -static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data) -{ - unsigned int status, count = 0, i; - - status = (volatile int) le32_to_cpu(dev->sip->mbox_status); - - while (!(status & IN_VALID) && count < 1000) { - count++; - for (i = 0; i < 1000; i++) - ; - status = (volatile int) le32_to_cpu(dev->sip->mbox_status); - } - if (count < 1000) { - /* if SET it means msg pending */ - *data = le32_to_cpu(dev->sip->mbox_in); - /*printf("mbox real read %08x\n", *data); */ - return 4; - } - printf("mbox rx timeout\n"); - return 0; -} - -static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) -{ - int ret; - - ret = zuma_mbox_write(&zuma_mbox_dev, out); - /*printf("write 0x%08x (%d bytes)\n", out, ret); */ - if (ret != 4) - return -1; - ret = zuma_mbox_read(&zuma_mbox_dev, in); - /*printf("read 0x%08x (%d bytes)\n", *in, ret); */ - if (ret != 4) - return -1; - return 0; -} - - -#define RET_IF_FAILED(x) if ((x) == -1) return -1 - -static int zuma_mbox_do_all_mailbox(void) -{ - unsigned int data_in; - unsigned short sdata_in; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); - memcpy(zuma_acc_mac + 2, &data_in, 4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); - sdata_in = data_in & 0xffff; - memcpy(zuma_acc_mac, &sdata_in, 2); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); - zuma_ip = data_in; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); - zuma_slot_bac = data_in >> 3; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); - zuma_console_baud = data_in & 0xffff; - zuma_debug_baud = data_in >> 16; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox - (ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); - memcpy(zuma_prv_mac + 2, &data_in, 4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox - (ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); - sdata_in = data_in & 0xffff; - memcpy(zuma_prv_mac, &sdata_in, 2); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); - - return 0; -} - - -static void zuma_mbox_dump(void) -{ - unsigned short s; - unsigned int i; - - memcpy(&s, &zuma_acc_mac, sizeof(s)); - memcpy(&i, &zuma_acc_mac[2], sizeof(i)); - printf("ACC MAC=%04x%08x\n", s, i); - - memcpy(&s, &zuma_prv_mac, sizeof(s)); - memcpy(&s, &zuma_prv_mac[2], sizeof(i)); - printf("PRV MAC=%04x%08x\n", s, i); - - printf("slot:bac=%d:%d\n", - (zuma_slot_bac >> 2) & 0xf, - zuma_slot_bac & 0x3); - - printf("BAUD1=%d BAUD2=%d\n", - zuma_console_baud, - zuma_debug_baud); -} - - -static void zuma_mbox_setenv(void) -{ - char *data, buf[32]; - unsigned char save = 0; - - data = getenv("baudrate"); - - if (!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { - sprintf(buf, "%6d", zuma_console_baud); - setenv("baudrate", buf); - save = 1; - printf("baudrate doesn't match from mbox\n"); - } - - ip_to_string(zuma_ip, buf); - setenv("ipaddr", buf); - - sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", - zuma_prv_mac[0], - zuma_prv_mac[1], - zuma_prv_mac[2], - zuma_prv_mac[3], zuma_prv_mac[4], zuma_prv_mac[5]); - setenv("ethaddr", buf); - - sprintf(buf, "%02x", zuma_slot_bac); - setenv("bacslot", buf); - - if (save) - saveenv(); -} - -/** - * zuma_mbox_init: - */ - -int zuma_mbox_init(void) -{ - unsigned int iobase; - - memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); - - zuma_mbox_dev.dev = - pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); - - if (zuma_mbox_dev.dev == -1) { - printf("no zuma pbb\n"); - return -1; - } - - pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); - - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - - zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) iobase; - - zuma_mbox_dev.sip->int_mask.word = 0; - - printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, - zuma_mbox_dev.sip->version.pci_bits.rev_major, - zuma_mbox_dev.sip->version.pci_bits.rev_minor, - zuma_mbox_dev.sip->timestamp); - - if (zuma_mbox_do_all_mailbox() == -1) { - printf("mailbox failed.. no ACC?\n"); - return -1; - } - - zuma_mbox_dump(); - - zuma_mbox_setenv(); - - return 0; -} diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h deleted file mode 100644 index b4a4c0c..0000000 --- a/board/evb64260/zuma_pbb_mbox.h +++ /dev/null @@ -1,43 +0,0 @@ -#define IN_VALID 1 -#define OUT_PENDING 2 - -enum { - ZUMA_MBOXMSG_DONE, - ZUMA_MBOXMSG_MACL, - ZUMA_MBOXMSG_MACH, - ZUMA_MBOXMSG_IP, - ZUMA_MBOXMSG_SLOT, - ZUMA_MBOXMSG_RESET, - ZUMA_MBOXMSG_BAUD, - ZUMA_MBOXMSG_START, - ZUMA_MBOXMSG_ENG_PRV_MACL, - ZUMA_MBOXMSG_ENG_PRV_MACH, - - MBOXMSG_LAST -}; - -struct zuma_mailbox_info { - unsigned char acc_mac[6]; - unsigned char prv_mac[6]; - unsigned int ip; - unsigned int slot_bac; - unsigned int console_baud; - unsigned int debug_baud; -}; - -struct _zuma_mbox_dev { - pci_dev_t dev; - PBB_DMA_REG_MAP *sip; - struct zuma_mailbox_info mailbox; -}; - -#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac -#define zuma_acc_mac zuma_mbox_dev.mailbox.acc_mac -#define zuma_ip zuma_mbox_dev.mailbox.ip -#define zuma_slot_bac zuma_mbox_dev.mailbox.slot_bac -#define zuma_console_baud zuma_mbox_dev.mailbox.console_baud -#define zuma_debug_baud zuma_mbox_dev.mailbox.debug_baud - - -extern struct _zuma_mbox_dev zuma_mbox_dev; -extern int zuma_mbox_init (void); diff --git a/board/freescale/mpc7448hpc2/Kconfig b/board/freescale/mpc7448hpc2/Kconfig deleted file mode 100644 index 3e7f6e8..0000000 --- a/board/freescale/mpc7448hpc2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC7448HPC2 - -config SYS_BOARD - default "mpc7448hpc2" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mpc7448hpc2" - -endif diff --git a/board/freescale/mpc7448hpc2/MAINTAINERS b/board/freescale/mpc7448hpc2/MAINTAINERS deleted file mode 100644 index 9966b55..0000000 --- a/board/freescale/mpc7448hpc2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC7448HPC2 BOARD -M: Roy Zang <tie-fei.zang@freescale.com> -S: Maintained -F: board/freescale/mpc7448hpc2/ -F: include/configs/mpc7448hpc2.h -F: configs/mpc7448hpc2_defconfig diff --git a/board/freescale/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile deleted file mode 100644 index 2cc211b..0000000 --- a/board/freescale/mpc7448hpc2/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mpc7448hpc2.o tsi108_init.o -obj-y += asm_init.o diff --git a/board/freescale/mpc7448hpc2/README b/board/freescale/mpc7448hpc2/README deleted file mode 100644 index cbb043e..0000000 --- a/board/freescale/mpc7448hpc2/README +++ /dev/null @@ -1,184 +0,0 @@ -Freescale MPC7448hpc2 (Taiga) board -=================================== - -Created 08/11/2006 Roy Zang --------------------------- -MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference -design, which is optimized for high speed throughput between the processor and -the memory, disk drive and Ethernet port subsystems. - -MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be -used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX -chassis. - -Building U-Boot ------------------- -The mpc7448hpc2 code base is known to compile using: - Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 - - $ make mpc7448hpc2_config - Configuring for mpc7448hpc2 board... - - $ make - -Memory Map ----------- - -The memory map is setup for Linux to operate properly. - -The mapping is: - - Range Start Range End Definition Size - - 0x0000_0000 0x7fff_ffff DDR 2G - 0xe000_0000 0xe7ff_ffff PCI Memory 128M - 0xfa00_0000 0xfaff_ffff PCI IO 16M - 0xfb00_0000 0xfbff_ffff PCI Config 16M - 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M - 0xfe00_0000 0xfeff_ffff PromJet 16M - 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M - 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M - -Using Flash ------------ - -The MPC7448hpc2 board has two "banks" of flash, each 8MB in size -(2^23 = 0x00800000). - -Note: the "bank" here refers to half of the flash. In fact, there is only one -bank of flash, which is divided into low and high half. Each is controlled by -the most significant bit of the address bus. The so called "bank" is only for -convenience. - -There is a switch which allows the "bank" to be selected. The switch -settings for updating flash are given below. - -The u-boot commands for copying the boot-bank into the secondary bank are -as follows: - - erase ff800000 ff880000 - cp.b ff000000 ff800000 80000 - -U-boot commands for downloading an image via tftp and flashing -it into the secondary bank: - - tftp 10000 <u-boot.bin.image> - erase ff000000 ff080000 - cp.b 10000 ff000000 80000 - -After copying the image into the second bank of flash, be sure to toggle -SW3[4] on board before resetting the board in order to set the -secondary bank as the boot-bank. - -Board Switches ----------------------- - -Most switches on the board should not be changed. The most frequent -user-settable switches on the board are used to configure -the flash banks and determining the PCI frequency. - -SW1[1-5]: Processor core voltage - - 12345 Core Voltage - ----- - SW1=01111 1.000V. - SW1=01101 1.100V. - SW1=01011 1.200V. - SW1=01001 1.300V only for MPC7447A. - - -SW2[1-6]: CPU core frequency - - CPU Core Frequency (MHz) - Bus Frequency - 123456 100 133 167 200 Ratio - - ------ - SW2=101100 500 667 833 1000 5x - SW2=100100 550 733 917 1100 5.5x - SW2=110100 600 800 1000 1200 6x - SW2=010100 650 866 1083 1300 6.5x - SW2=001000 700 930 1167 1400 7x - SW2=000100 750 1000 1250 1500 7.5x - SW2=110000 800 1066 1333 1600 8x - SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A - SW2=011110 900 1200 1500 1800 9x - -This table shows only a subset of available frequency options; see the CPU -hardware specifications for more information. - -SW2[7-8]: Bus Protocol and CPU Reset Option - - 7 - - - SW2=0 System bus uses MPX bus protocol - SW2=1 System bus uses 60x bus protocol - - 8 - - - SW2=0 TSI108 can cause CPU reset - SW2=1 TSI108 can not cause CPU reset - -SW3[1-8] system options - - 123 - --- - SW3=xxx Connected to GPIO[0:2] on TSI108 - - 4 - - - SW3=0 CPU boots from low half of flash - SW3=1 CPU boots from high half of flash - - 5 - - - SW3=0 SATA and slot2 connected to PCI bus - SW3=1 Only slot1 connected to PCI bus - - 6 - - - SW3=0 USB connected to PCI bus - SW3=1 USB disconnected from PCI bus - - 7 - - - SW3=0 Flash is write protected - SW3=1 Flash is NOT write protected - - 8 - - - SW3=0 CPU will boot from flash - SW3=1 CPU will boot from PromJet - -SW4[1-3]: System bus frequency - - Bus Frequency (MHz) - --- - SW4=010 183 - SW4=011 100 - SW4=100 133 - SW4=101 166 only for MPC7447A - SW4=110 200 only for MPC7448 - others reserved - -SW4[4-6]: DDR2 SDRAM frequency - - Bus Frequency (MHz) - --- - SW4=000 external clock - SW4=011 system clock - SW4=100 133 - SW4=101 166 - SW4=110 200 - others reserved - -SW4[7-8]: PCI/PCI-X frequency control - 7 - - - SW4=0 PCI/PCI-X bus operates normally - SW4=1 PCI bus forced to PCI-33 mode - - 8 - - - SW4=0 PCI-X mode at 133 MHz allowed - SW4=1 PCI-X mode limited to 100 MHz diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S deleted file mode 100644 index 70315c3..0000000 --- a/board/freescale/mpc7448hpc2/asm_init.S +++ /dev/null @@ -1,905 +0,0 @@ -/* - * (C) Copyright 2004-05; Tundra Semiconductor Corp. - * - * Added automatic detect of SDC settings - * Copyright (c) 2005 Freescale Semiconductor, Inc. - * Maintainer tie-fei.zang@freescale.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * FILENAME: asm_init.s - * - * Originator: Alex Bounine - * - * DESCRIPTION: - * Initialization code for the Tundra Tsi108 bridge chip - * - */ - -#include <config.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/processor.h> - -#include <tsi108.h> - -/* - * Build Configuration Options - */ - -/* #define DISABLE_PBM disables usage of PB Master */ -/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ -/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ - -/* - * Hardcoded SDC settings - */ - -#ifdef SDC_HARDCODED_INIT - -/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ - -#define VAL_SD_REFRESH (0x61A) -#define VAL_SD_TIMING (0x0308336b) -#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ -#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ -#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ -#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ - -#endif /* SDC_HARDCODED_INIT */ - -/* - CPU Configuration: - - CPU Address and Data Parity enables. - -#define CPU_AP -#define CPU_DP -*/ - -/* - * Macros - * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are - * expected to work correctly for the CSR space within 32KB range. - * - * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. - * These macros are absolutely identical except their names. This difference - * is provided intentionally for better readable code. - */ - -#define LOAD_PTR(reg,const32) \ - addis reg,r0,const32@h; ori reg,reg,const32@l - -#define LOAD_U32(reg,const32) \ - addis reg,r0,const32@h; ori reg,reg,const32@l - -/* LOADMEM initializes a register with the contents of a specified 32-bit - * memory location, usually a CSR value. - */ - -#define LOAD_MEM(reg,addr32) \ - addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) - -#ifndef SDC_HARDCODED_INIT -sdc_clk_sync: - /* MHz: 0,0,183,100,133,167,200,233 */ - .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */ -#endif - -/* - * board_asm_init() - early initialization function. Coded to be portable to - * dual-CPU configuration. - * Checks CPU number and performs board HW initialization if called for CPU0. - * Registers used: r3,r4,r5,r6,r19,r29 - * - * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 - * and the rest of the board. Current implementation demonstrates two - * possible ways to identify CPU number: - * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. - * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. - */ - - .globl board_asm_init -board_asm_init: - mflr r19 /* Save LR to be able return later. */ - bl icache_enable /* Enable icache to reduce reads from flash. */ - -/* Initialize pointer to Tsi108 register space */ - - LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ - ori r4,r29,TSI108_PB_REG_OFFSET - -/* Check Processor Version Number */ - - mfspr r3, PVR - rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ - - cmpli 0,0,r3,0x8000 /* MPC74xx */ - bne cont_brd_init - - /* - * For MPC744x/5x enable extended BATs[4-7] - * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 - * to disable prefetch - */ - - mfspr r5, HID0 - oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ - ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ - mtspr HID0, r5 - isync - sync - - /* Adding code to disable external interventions in MPX bus mode */ - mfspr r3, 1014 - oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ - mtspr 1014, r3 - isync - sync - - /* Sri: code to enable FP unit */ - mfmsr r3 - ori r3, r3, 0x2000 - mtmsr r3 - isync - sync - - /* def CONFIG_DUAL_CPU - * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. - */ -#if(1) - mfspr r3,1014 /* read MSSCR0 */ - rlwinm. r3,r3,27,31,31 /* get processor ID number */ - mtspr SPRN_PIR,r3 /* Save CPU ID */ - sync - bne init_done - b do_tsi108_init - -cont_brd_init: - - /* An alternative method of checking the processor number (in addition - * to configuration using MSSCR0[ID] bit on MPC74xx). - * Good for IBM PPC750FX/GX. - */ - - lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ - rlwinm. r3,r3,24,31,31 /* get processor ID number */ - bne init_done -#else - -cont_brd_init: - -#endif /* CONFIG_DUAL_CPU */ - - /* Initialize Tsi108 chip */ - -do_tsi108_init: - - /* - * Adjust HLP/Flash parameters. By default after reset the HLP port is - * set to support slow devices. Better performance can be achived when - * an optimal parameters are used for specific EPROM device. - * NOTE: This should be performed ASAP for the emulation platform - * because it has 5MHz HLP clocking. - */ - -#ifdef CONFIG_TSI108EMU - ori r4,r29,TSI108_HLP_REG_OFFSET - LOAD_U32(r5,0x434422c0) - stw r5,0x08(r4) /* set HLP B0_CTRL0 */ - sync - LOAD_U32(r5,0xd0012000) - stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ - sync -#endif - - /* Initialize PB interface. */ - - ori r4,r29,TSI108_PB_REG_OFFSET - -#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE) - /* Relocate (if required) Tsi108 registers. Set new value for - * PB_REG_BAR: - * Note we are in the 32-bit address mode. - */ - LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ - stw r5,PB_REG_BAR(r4) - andis. r29,r5,0xFFFF - sync - ori r4,r29,TSI108_PB_REG_OFFSET -#endif - - /* Set PB Slave configuration register */ - - LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */ - lwz r3, PB_RSR(r4) /* get PB bus mode */ - xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ - rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ - stw r5,PB_SCR(r4) - sync - - /* Configure PB Arbiter */ - - lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ - li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ -#ifdef DISABLE_PBM - ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ -#endif - andc r5,r5,r3 /* Clear the masked bit fields */ - ori r5,r5,0x0001 /* Set pipeline depth */ - stw r5,PB_ARB_CTRL(r4) - -#if (0) /* currently using the default settings for PBM after reset */ - LOAD_U32(r5,0x) /* value for PB_MCR */ - stw r5,PB_MCR(r4) - sync - - LOAD_U32(r5,0x) /* value for PB_MCMD */ - stw r5,PB_MCMD(r4) - sync -#endif - - /* Disable or enable PVT based on processor bus frequency - * 1. Read CG_PWRUP_STATUS register field bits 18,17,16 - * 2. See if the value is < or > 133mhz (18:16 = 100) - * 3. If > enable PVT - */ - - LOAD_U32(r3,0xC0002234) - lwz r3,0(r3) - rlwinm r3,r3,16,29,31 - - cmpi 0,0,r3,0x0004 - bgt sdc_init - -#ifndef CONFIG_TSI108EMU - /* FIXME: Disable PB calibration control for any real Tsi108 board */ - li r5,0x0101 /* disable calibration control */ - stw r5,PB_PVT_CTRL2(r4) - sync -#endif - - /* Initialize SDRAM controller. */ - -sdc_init: - -#ifndef SDC_HARDCODED_INIT - /* get SDC clock prior doing sdram controller autoconfig */ - ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ - lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ - rlwinm r3,r3,12,29,31 /* r3 - SD clk */ - lis r5,sdc_clk_sync@h - ori r5,r5,sdc_clk_sync@l - /* Sri: At this point check if r3 = 001. If yes, - * the memory frequency should be same as the - * MPX bus frequency - */ - cmpi 0,0,r3,0x0001 - bne get_nsec - lwz r6, CG_PWRUP_STATUS(r4) - rlwinm r6,r6,16,29,31 - mr r3,r6 - -get_nsec: - rlwinm r3,r3,2,0,31 - lwzx r9,r5,r3 /* get SD clk rate in nSec */ - /* ATTN: r9 will be used by SPD routine */ -#endif /* !SDC_HARDCODED_INIT */ - - ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ - - /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ - - LOAD_U32(r5,0x00) - stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ -#ifdef ENABLE_SDRAM_ECC - li r5, 0x01 -#endif /* ENABLE_SDRAM_ECC */ - stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ - sync - -#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ - - /* First read the CG_PWRUP_STATUS register to get the - * memory speed from bits 22,21,20 - */ - - LOAD_U32(r3,0xC0002234) - lwz r3,0(r3) - rlwinm r3,r3,12,29,31 - - /* Now first check for 166, then 200, or default */ - - cmpi 0,0,r3,0x0005 - bne check_for_200mhz - - /* set values for 166 Mhz memory speed - * Set refresh rate and timing parameters - */ - LOAD_U32(r5,0x00000515) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,0x03073368) - stw r5,SD_TIMING(r4) - sync - - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync - - b sdc_init_done - -check_for_200mhz: - - cmpi 0,0,r3,0x0006 - bne set_default_values - - /* set values for 200Mhz memory speed - * Set refresh rate and timing parameters - */ - LOAD_U32(r5,0x0000061a) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,0x03083348) - stw r5,SD_TIMING(r4) - sync - - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync - - b sdc_init_done - -set_default_values: - - /* Set refresh rate and timing parameters */ - LOAD_U32(r5,VAL_SD_REFRESH) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,VAL_SD_TIMING) - stw r5,SD_TIMING(r4) - sync - - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync -#else /* !SDC_HARDCODED_INIT */ - bl tsi108_sdram_spd /* automatically detect SDC settings */ -#endif /* SDC_HARDCODED_INIT */ - -sdc_init_done: - -#ifdef DISABLE_PBM - LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ -#else - LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ -#endif /* DISABLE_PBM */ - -#ifdef CONFIG_TSI108EMU - oris r5,r5,0x0010 /* set EMULATION_MODE bit */ -#endif - - stw r5,SD_CTRL(r4) - eieio - sync - - /* Enable SDRAM access */ - - oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ - stw r5,SD_CTRL(r4) - sync - -wait_init_complete: - lwz r5,SD_STATUS(r4) - andi. r5,r5,0x0001 - /* wait until SDRAM initialization is complete */ - beq wait_init_complete - - /* Map SDRAM into the processor bus address space */ - - ori r4,r29,TSI108_PB_REG_OFFSET - - /* Setup BARs associated with direct path PB<->SDRAM */ - - /* PB_SDRAM_BAR1: - * provides a direct path to the main system memory (cacheable SDRAM) - */ - - /* BA=0,Size=512MB, ENable, No Addr.Translation */ - LOAD_U32(r5, 0x00000011) - stw r5,PB_SDRAM_BAR1(r4) - sync - - /* Make sure that PB_SDRAM_BAR1 decoder is set - * (to allow following immediate read from SDRAM) - */ - lwz r5,PB_SDRAM_BAR1(r4) - sync - - /* PB_SDRAM_BAR2: - * provides non-cacheable alias (via the direct path) to main - * system memory. - * Size = 512MB, ENable, Addr.Translation - ON, - * BA = 0x0_40000000, TA = 0x0_00000000 - */ - - LOAD_U32(r5, 0x40010011) - stw r5,PB_SDRAM_BAR2(r4) - sync - - /* Make sure that PB_SDRAM_BAR2 decoder is set - * (to allow following immediate read from SDRAM) - */ - lwz r5,PB_SDRAM_BAR2(r4) - sync - -init_done: - - /* All done. Restore LR and return. */ - mtlr r19 - blr - -#if (0) - /* - * init_cpu1 - * This routine enables CPU1 on the dual-processor system. - * Now there is only one processor in the system - */ - - .global enable_cpu1 -enable_cpu1: - - lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ - addi r3,r3,Tsi108_Base@l - lwz r3,0(r3) /* R3 = CSR Base Addr */ - ori r4,r3,TSI108_PB_REG_OFFSET - lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ - ori r3,r3,0x0200 /* Set M1_EN bit */ - stw r3,PB_ARB_CTRL(r4) - - blr -#endif - - /* - * enable_EI - * Enable CPU core external interrupt - */ - - .global enable_EI -enable_EI: - mfmsr r3 - ori r3,r3,0x8000 /* set EE bit */ - mtmsr r3 - blr - - /* - * disable_EI - * Disable CPU core external interrupt - */ - - .global disable_EI -disable_EI: - mfmsr r3 - li r4,-32768 /* aka "li r4,0x8000" */ - andc r3,r3,r4 /* clear EE bit */ - mtmsr r3 - blr - -#ifdef ENABLE_SDRAM_ECC - /* enables SDRAM ECC */ - - .global enable_ECC -enable_ECC: - ori r4,r29,TSI108_SD_REG_OFFSET - lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ - ori r3,r3,0x0001 /* Set ECC_EN bit */ - stw r3,SD_ECC_CTRL(r4) - blr - - /* - * clear_ECC_err - * Clears all pending SDRAM ECC errors - * (normally after SDRAM scrubbing/initialization) - */ - - .global clear_ECC_err -clear_ECC_err: - ori r4,r29,TSI108_SD_REG_OFFSET - ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ - stw r3,SD_INT_STATUS(r4) - blr - -#endif /* ENABLE_SDRAM_ECC */ - -#ifndef SDC_HARDCODED_INIT - - /* SDRAM SPD Support */ -#define SD_I2C_CTRL1 (0x400) -#define SD_I2C_CTRL2 (0x404) -#define SD_I2C_RD_DATA (0x408) -#define SD_I2C_WR_DATA (0x40C) - - /* - * SDRAM SPD Support Macros - */ - -#define SPD_DIMM0 (0x00000100) -#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ - -#define SPD_RDIMM (0x01) -#define SPD_UDIMM (0x02) - -#define SPD_CAS_3 0x8 -#define SPD_CAS_4 0x10 -#define SPD_CAS_5 0x20 - -#define ERR_NO_DIMM_FOUND (0xdb0) -#define ERR_TRAS_FAIL (0xdb1) -#define ERR_TRCD_FAIL (0xdb2) -#define ERR_TRP_FAIL (0xdb3) -#define ERR_TWR_FAIL (0xdb4) -#define ERR_UNKNOWN_PART (0xdb5) -#define ERR_NRANK_INVALID (0xdb6) -#define ERR_DIMM_SIZE (0xdb7) -#define ERR_ADDR_MODE (0xdb8) -#define ERR_RFRSH_RATE (0xdb9) -#define ERR_DIMM_TYPE (0xdba) -#define ERR_CL_VALUE (0xdbb) -#define ERR_TRFC_FAIL (0xdbc) - -/* READ_SPD requirements: - * byte - byte address in SPD device (0 - 255) - * r3 = will return data read from I2C Byte location - * r4 - unchanged (SDC base addr) - * r5 - clobbered in routine (I2C status) - * r10 - number of DDR slot where first SPD device is detected - */ - -#define READ_SPD(byte_num) \ - addis r3, 0, byte_num@l; \ - or r3, r3, r10; \ - ori r3, r3, 0x0A; \ - stw r3, SD_I2C_CTRL1(r4); \ - li r3, I2C_CNTRL2_START; \ - stw r3, SD_I2C_CTRL2(r4); \ - eieio; \ - sync; \ - li r3, 0x100; \ -1:; \ - addic. r3, r3, -1; \ - bne 1b; \ -2:; \ - lwz r5, SD_I2C_CTRL2(r4); \ - rlwinm. r3,r5,0,23,23; \ - bne 2b; \ - rlwinm. r3,r5,0,3,3; \ - lwz r3,SD_I2C_RD_DATA(r4) - -#define SPD_MIN_RFRSH (0x80) -#define SPD_MAX_RFRSH (0x85) - -refresh_rates: /* in nSec */ - .long 15625 /* Normal (0x80) */ - .long 3900 /* Reduced 0.25x (0x81) */ - .long 7800 /* Reduced 0.5x (0x82) */ - .long 31300 /* Extended 2x (0x83) */ - .long 62500 /* Extended 4x (0x84) */ - .long 125000 /* Extended 8x (0x85) */ - -/* - * tsi108_sdram_spd - * - * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data - * Uses registers: r4 - SDC base address (not changed) - * r9 - SDC clocking period in nSec - * Changes registers: r3,r5,r6,r7,r8,r10,r11 - */ - -tsi108_sdram_spd: - - li r10,SPD_DIMM0 - xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ - -do_first_dimm: - - /* Program Refresh Rate Register */ - - READ_SPD(12) /* get Refresh Rate */ - beq check_next_slot - li r5, ERR_RFRSH_RATE - cmpi 0,0,r3,SPD_MIN_RFRSH - ble spd_fail - cmpi 0,0,r3,SPD_MAX_RFRSH - bgt spd_fail - addi r3,r3,-SPD_MIN_RFRSH - rlwinm r3,r3,2,0,31 - lis r5,refresh_rates@h - ori r5,r5,refresh_rates@l - lwzx r5,r5,r3 /* get refresh rate in nSec */ - divwu r5,r5,r9 /* calculate # of SDC clocks */ - stw r5,SD_REFRESH(r4) /* Set refresh rate */ - sync - - /* Program SD Timing Register */ - - li r7, 0 /* clear r7 prior parameter collection */ - - READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ - beq spd_read_fail - li r5, ERR_DIMM_TYPE - cmpi 0,0,r3,SPD_UDIMM - beq do_cl - cmpi 0,0,r3,SPD_RDIMM - bne spd_fail - oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ - -do_cl: - READ_SPD(18) /* Get CAS Latency */ - beq spd_read_fail - li r5,ERR_CL_VALUE - andi. r6,r3,SPD_CAS_3 - beq cl_4 - li r6,3 - b set_cl -cl_4: - andi. r6,r3,SPD_CAS_4 - beq cl_5 - li r6,4 - b set_cl -cl_5: - andi. r6,r3,SPD_CAS_5 - beq spd_fail - li r6,5 -set_cl: - rlwimi r7,r6,24,5,7 - - READ_SPD(30) /* Get tRAS */ - beq spd_read_fail - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_tras - addi r6,r6,1 -set_tras: - li r5,ERR_TRAS_FAIL - cmpi 0,0,r6,0x0F /* max supported value */ - bgt spd_fail - rlwimi r7,r6,16,12,15 - - READ_SPD(29) /* Get tRCD */ - beq spd_read_fail - /* right shift tRCD by 2 bits as per DDR2 spec */ - rlwinm r3,r3,30,2,31 - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_trcd - addi r6,r6,1 -set_trcd: - li r5,ERR_TRCD_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,12,17,19 - - READ_SPD(27) /* Get tRP value */ - beq spd_read_fail - rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_trp - addi r6,r6,1 -set_trp: - li r5,ERR_TRP_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,8,21,23 - - READ_SPD(36) /* Get tWR value */ - beq spd_read_fail - rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_twr - addi r6,r6,1 -set_twr: - addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ - li r5,ERR_TWR_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,5,24,26 - - READ_SPD(42) /* Get tRFC */ - beq spd_read_fail - li r5, ERR_TRFC_FAIL - /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ - addi r3,r3,1 - rlwinm. r3,r3,31,1,31 /* divide by 2 */ - beq spd_fail - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_trfc - addi r6,r6,1 -set_trfc: - cmpi 0,0,r6,0x1F /* max supported value */ - bgt spd_fail - rlwimi r7,r6,0,27,31 - - stw r7,SD_TIMING(r4) - sync - - /* - * The following two registers are set on per-DIMM basis. - * The SD_REFRESH and SD_TIMING settings are common for both DIMMS - */ - -do_each_dimm: - - /* Program SDRAM DIMM Control Register */ - - li r7, 0 /* clear r7 prior parameter collection */ - - READ_SPD(13) /* Get Primary SDRAM Width */ - beq spd_read_fail - cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ - beq do_nbank - oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ - -do_nbank: - READ_SPD(17) /* Get Number of banks on SDRAM device */ - beq spd_read_fail - /* Grendel only distinguish betw. 4 or 8-bank memory parts */ - li r5,ERR_UNKNOWN_PART /* non-supported memory part */ - cmpi 0,0,r3,4 - beq do_nrank - cmpi 0,0,r3,8 - bne spd_fail - ori r7,r7,0x1000 - -do_nrank: - READ_SPD(5) /* Get # of Ranks */ - beq spd_read_fail - li r5,ERR_NRANK_INVALID - andi. r6,r3,0x7 /* Use bits [2..0] only */ - beq do_addr_mode - cmpi 0,0,r6,1 - bgt spd_fail - rlwimi r7,r6,8,23,23 - -do_addr_mode: - READ_SPD(4) /* Get # of Column Addresses */ - beq spd_read_fail - li r5, ERR_ADDR_MODE - andi. r3,r3,0x0f /* cut off reserved bits */ - cmpi 0,0,r3,8 - ble spd_fail - cmpi 0,0,r3,15 - bgt spd_fail - addi r6,r3,-8 /* calculate ADDR_MODE parameter */ - rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ - -set_dimm_ctrl: -#ifdef SDC_AUTOPRECH_EN - oris r7,r7,0x0001 /* set auto precharge EN bit */ -#endif - ori r7,r7,1 /* set ENABLE bit */ - cmpi 0,0,r10,SPD_DIMM0 - bne 1f - stw r7,SD_D0_CTRL(r4) - sync - b set_dimm_bar -1: - stw r7,SD_D1_CTRL(r4) - sync - - - /* Program SDRAM DIMMx Base Address Register */ - -set_dimm_bar: - READ_SPD(5) /* get # of Ranks */ - beq spd_read_fail - andi. r7,r3,0x7 - addi r7,r7,1 - READ_SPD(31) /* Read DIMM rank density */ - beq spd_read_fail - rlwinm r5,r3,27,29,31 - rlwinm r6,r3,3,24,28 - or r5,r6,r5 /* r5 = Normalized Rank Density byte */ - lis r8, 0x0080 /* 128MB >> 4 */ - mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ - mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ - neg r7,r8 - rlwinm r7,r7,28,4,31 - or r7,r7,r11 /* set ADDR field */ - rlwinm r8,r8,12,20,31 - add r11,r11,r8 /* set Base Addr for next DIMM */ - - cmpi 0,0,r10,SPD_DIMM0 - bne set_dimm1_size - stw r7,SD_D0_BAR(r4) - sync - li r10,SPD_DIMM1 - READ_SPD(0) - bne do_each_dimm - b spd_done - -set_dimm1_size: - stw r7,SD_D1_BAR(r4) - sync -spd_done: - blr - -check_next_slot: - cmpi 0,0,r10,SPD_DIMM1 - beq spd_read_fail - li r10,SPD_DIMM1 - b do_first_dimm -spd_read_fail: - ori r3,r0,0xdead - b err_hung -spd_fail: - li r3,0x0bad - sync -err_hung: /* hang here for debugging */ - nop - nop - b err_hung - -#endif /* !SDC_HARDCODED_INIT */ diff --git a/board/freescale/mpc7448hpc2/config.mk b/board/freescale/mpc7448hpc2/config.mk deleted file mode 100644 index b2d6f76..0000000 --- a/board/freescale/mpc7448hpc2/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2005 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c deleted file mode 100644 index 11747ca..0000000 --- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2005 Freescale Semiconductor, Inc. - * - * Roy Zang <tie-fei.zang@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the Tsi108 Emul Board by avb@Tundra - */ - -/* - * board support/init functions for the - * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform). - */ - -#include <common.h> -#include <74xx_7xx.h> -#include <fdt_support.h> -#include <netdev.h> - -#undef DEBUG - -DECLARE_GLOBAL_DATA_PTR; - -extern void tsi108_init_f (void); - -int display_mem_map (void); - -void after_reloc (ulong dest_addr) -{ - /* - * Jump to the main U-Boot board init code - */ - board_init_r ((gd_t *) gd, dest_addr); - /* NOTREACHED */ -} - -/* - * Check Board Identity: - * report board type - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); - return (l_type); -} - -/* - * Read Processor ID: - * - * report calling processor number - */ - -int read_pid (void) -{ - return 0; /* we are on single CPU platform for a while */ -} - -long int dram_size (int board_type) -{ - return 0x20000000; /* 256M bytes */ -} - -phys_size_t initdram (int board_type) -{ - return dram_size (board_type); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); - - return 0; -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#if defined(CONFIG_TSI108_ETH) - rc = tsi108_eth_initialize(bis); -#endif - return rc; -} diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c deleted file mode 100644 index 9a1e407..0000000 --- a/board/freescale/mpc7448hpc2/tsi108_init.c +++ /dev/null @@ -1,652 +0,0 @@ -/***************************************************************************** - * (C) Copyright 2003; Tundra Semiconductor Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - *****************************************************************************/ - -/*---------------------------------------------------------------------------- - * FILENAME: tsi108_init.c - * - * Originator: Alex Bounine - * - * DESCRIPTION: - * Initialization code for the Tundra Tsi108 bridge chip - *---------------------------------------------------------------------------*/ - -#include <common.h> -#include <74xx_7xx.h> -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <tsi108.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void mpicInit (int verbose); - -/* - * Configuration Options - */ - -typedef struct { - ulong upper; - ulong lower; -} PB2OCN_LUT_ENTRY; - -PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = { - /* 0 - 7 */ - {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */ - - /* 8 - 15 */ - {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */ - - /* 16 - 23 */ - {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */ - /* 24 - 31 */ - {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap + Translate) */ - {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */ - - {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */ - {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */ - {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */ - {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/ -}; - -#ifdef CONFIG_SYS_CLK_SPREAD -typedef struct { - ulong ctrl0; - ulong ctrl1; -} PLL_CTRL_SET; - -/* - * Clock Generator SPLL0 initialization values - * PLL0 configuration table for various PB_CLKO freq. - * Uses pre-calculated values for Fs = 30 kHz, D = 0.5% - * Fout depends on required PB_CLKO. Based on Fref = 33 MHz - */ - -static PLL_CTRL_SET pll0_config[8] = { - {0x00000000, 0x00000000}, /* 0: bypass */ - {0x00000000, 0x00000000}, /* 1: reserved */ - {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */ - {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */ - {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */ - {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */ - {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */ - {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */ -}; -#endif /* CONFIG_SYS_CLK_SPREAD */ - -/* - * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT - * (based on recommended Tsi108 reference clock 33MHz) - */ -static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 }; - -/* - * get_board_bus_clk () - * - * returns the bus clock in Hz. - */ -unsigned long get_board_bus_clk (void) -{ - ulong i; - - /* Detect PB clock freq. */ - i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); - i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ - - return pb_clk_sel[i] * 1000000; -} - -/* - * board_early_init_f () - * - * board-specific initialization executed from flash - */ - -int board_early_init_f (void) -{ - ulong i; - - gd->mem_clk = 0; - i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + - CG_PWRUP_STATUS); - i = (i >> 20) & 0x07; /* Get GD PLL multiplier */ - switch (i) { - case 0: /* external clock */ - printf ("Using external clock\n"); - break; - case 1: /* system clock */ - gd->mem_clk = gd->bus_clk; - break; - case 4: /* 133 MHz */ - case 5: /* 166 MHz */ - case 6: /* 200 MHz */ - gd->mem_clk = pb_clk_sel[i] * 1000000; - break; - default: - printf ("Invalid DDR2 clock setting\n"); - return -1; - } - printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000); - printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000); - return 0; -} - -/* - * board_early_init_r() - Tsi108 initialization function executed right after - * relocation. Contains code that cannot be executed from flash. - */ - -int board_early_init_r (void) -{ - ulong temp, i; - ulong reg_val; - volatile ulong *reg_ptr; - - reg_ptr = - (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); - - for (i = 0; i < 32; i++) { - *reg_ptr++ = 0x00000201; /* SWAP ENABLED */ - *reg_ptr++ = 0x00; - } - - __asm__ __volatile__ ("eieio"); - __asm__ __volatile__ ("sync"); - - /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, - 0x80000001); - __asm__ __volatile__ ("sync"); - - /* Make sure that OCN_BAR2 decoder is set (to allow following immediate - * read from SDRAM) - */ - - temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); - __asm__ __volatile__ ("sync"); - - /* - * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the - * processor bus address space. Immediately after reset LUT and address - * translation are disabled for this BAR. Now we have to initialize LUT - * and switch from the BOOT mode to the normal operation mode. - * - * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000 - * and covers 512MB of address space. To allow larger aperture we also - * have to relocate register window of Tsi108 - * - * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT - * mode. - * - * initialize pointer to LUT associated with PB_OCN_BAR1 - */ - reg_ptr = - (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); - - for (i = 0; i < 32; i++) { - *reg_ptr++ = pb2ocn_lut1[i].lower; - *reg_ptr++ = pb2ocn_lut1[i].upper; - } - - __asm__ __volatile__ ("sync"); - - /* Base addresses for CS0, CS1, CS2, CS3 */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, - 0x00000000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, - 0x00100000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, - 0x00200000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, - 0x00300000); - __asm__ __volatile__ ("sync"); - - /* Masks for HLP banks */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, - 0xFFF00000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, - 0xFFF00000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, - 0xFFF00000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, - 0xFFF00000); - __asm__ __volatile__ ("sync"); - - /* Set CTRL0 values for banks */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, - 0x7FFC44C2); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, - 0x7FFC44C0); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, - 0x7FFC44C0); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, - 0x7FFC44C2); - __asm__ __volatile__ ("sync"); - - /* Set banks to latched mode, enabled, and other default settings */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, - 0x7C0F2000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, - 0x7C0F2000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, - 0x7C0F2000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, - 0x7C0F2000); - __asm__ __volatile__ ("sync"); - - /* - * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. - * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) - */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, - 0xE0000011); - __asm__ __volatile__ ("sync"); - - /* Make sure that OCN_BAR2 decoder is set (to allow following - * immediate read from SDRAM) - */ - - temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); - __asm__ __volatile__ ("sync"); - - /* - * SRI: At this point we have enabled the HLP banks. That means we can - * now read from the NVRAM and initialize the environment variables. - * We will over-ride the env_init called in board_init_f - * This is really a work-around because, the HLP bank 1 - * where NVRAM resides is not visible during board_init_f - * (arch/powerpc/lib/board.c) - * Alternatively, we could use the I2C EEPROM at start-up to configure - * and enable all HLP banks and not just HLP 0 as is being done for - * Taiga Rev. 2. - */ - - env_init (); - -#ifndef DISABLE_PBM - - /* - * For IBM processors we have to set Address-Only commands generated - * by PBM that are different from ones set after reset. - */ - - temp = get_cpu_type (); - - if ((CPU_750FX == temp) || (CPU_750GX == temp)) - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, - 0x00009955); -#endif /* DISABLE_PBM */ - -#ifdef CONFIG_PCI - /* - * Initialize PCI/X block - */ - - /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + - PCI_PFAB_BAR0_UPPER, 0); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, - 0xFB000001); - __asm__ __volatile__ ("sync"); - - /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ - - temp = in32(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); - - temp &= ~0xFF00; /* Clear the BUS_NUM field */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, - temp); - - /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, - 0); - __asm__ __volatile__ ("sync"); - - /* This register is on the PCI side to interpret the address it receives - * and maps it as a IO address. - */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, - 0x00000001); - __asm__ __volatile__ ("sync"); - - /* - * Map PCI/X Memory Space - * - * Transactions directed from OCM to PCI Memory Space are directed - * from PB to PCI - * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings). - * If address remapping is required the corresponding PCI_PFAB_MEM32 - * and PCI_PFAB_PFMx register groups have to be configured. - * - * Map the path from the PCI/X bus into the system memory - * - * The memory mapped window assotiated with PCI P2O_BAR2 provides - * access to the system memory without address remapping. - * All system memory is opened for accesses initiated by PCI/X bus - * masters. - * - * Initialize LUT associated with PCI P2O_BAR2 - * - * set pointer to LUT associated with PCI P2O_BAR2 - */ - - reg_ptr = - (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); - -#ifdef DISABLE_PBM - - /* In case when PBM is disabled (no HW supported cache snoopng on PB) - * P2O_BAR2 is directly mapped into the system memory without address - * translation. - */ - - reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */ - - for (i = 0; i < 32; i++) { - *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ - *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */ - } - - /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */ - reg_val = 0x00007500; -#else - - reg_val = 0x00000002; /* Destination port = PBM */ - - for (i = 0; i < 32; i++) { - *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ -/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ - *reg_ptr++ = 0x40000000; -/* offset = 16MB, address translation is enabled to allow byte swapping */ - reg_val += 0x01000000; - } - -/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */ - reg_val = 0x00007100; -#endif - - __asm__ __volatile__ ("eieio"); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, - reg_val); - __asm__ __volatile__ ("sync"); - - /* Set 64-bit PCI bus address for system memory - * ( 0 is the best choice for easy mapping) - */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, - 0x00000000); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, - 0x00000000); - __asm__ __volatile__ ("sync"); - -#ifndef DISABLE_PBM - /* - * The memory mapped window assotiated with PCI P2O_BAR3 provides - * access to the system memory using SDRAM OCN port and address - * translation. This is alternative way to access SDRAM from PCI - * required for Tsi108 emulation testing. - * All system memory is opened for accesses initiated by - * PCI/X bus masters. - * - * Initialize LUT associated with PCI P2O_BAR3 - * - * set pointer to LUT associated with PCI P2O_BAR3 - */ - reg_ptr = - (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); - - reg_val = 0x00000004; /* Destination port = SDC */ - - for (i = 0; i < 32; i++) { - *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */ - -/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ - *reg_ptr++ = 0; - -/* offset = 16MB, address translation is enabled to allow byte swapping */ - reg_val += 0x01000000; - } - - __asm__ __volatile__ ("eieio"); - __asm__ __volatile__ ("sync"); - - /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */ - - reg_val = - in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + - PCI_P2O_PAGE_SIZES); - reg_val &= ~0x00FF; - reg_val |= 0x0071; - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, - reg_val); - __asm__ __volatile__ ("sync"); - - /* Set 64-bit base PCI bus address for window (0x20000000) */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, - 0x00000000); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, - 0x20000000); - __asm__ __volatile__ ("sync"); - -#endif /* !DISABLE_PBM */ - -#ifdef ENABLE_PCI_CSR_BAR - /* open if required access to Tsi108 CSRs from the PCI/X bus */ - /* enable BAR0 on the PCI/X bus */ - reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); - reg_val |= 0x02; - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, - reg_val); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, - 0x00000000); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, - CONFIG_SYS_TSI108_CSR_BASE); - __asm__ __volatile__ ("sync"); - -#endif - - /* - * Finally enable PCI/X Bus Master and Memory Space access - */ - - reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); - reg_val |= 0x06; - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); - __asm__ __volatile__ ("sync"); - -#endif /* CONFIG_PCI */ - - /* - * Initialize MPIC outputs (interrupt pins): - * Interrupt routing on the Grendel Emul. Board: - * PB_INT[0] -> INT (CPU0) - * PB_INT[1] -> INT (CPU1) - * PB_INT[2] -> MCP (CPU0) - * PB_INT[3] -> MCP (CPU1) - * Set interrupt controller outputs as Level_Sensitive/Active_Low - */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); - __asm__ __volatile__ ("sync"); - - /* - * Ensure that Machine Check exception is enabled - * We need it to support PCI Bus probing (configuration reads) - */ - - reg_val = mfmsr (); - mtmsr(reg_val | MSR_ME); - - return 0; -} - -/* - * Needed to print out L2 cache info - * used in the misc_init_r function - */ - -unsigned long get_l2cr (void) -{ - unsigned long l2controlreg; - asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):); - return l2controlreg; -} - -/* - * misc_init_r() - * - * various things to do after relocation - * - */ - -int misc_init_r (void) -{ -#ifdef CONFIG_SYS_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ - ulong i; - - /* Ensure that Spread-Spectrum is disabled */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); - - /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK - * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% - */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, - 0x002e0044); /* D = 0.25% */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, - 0x00000039); /* BWADJ */ - - /* Initialize PLL0: CG_PB_CLKO */ - /* Detect PB clock freq. */ - i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); - i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); - out32 (CONFIG_SYS_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); - - /* Wait and set SSEN for both PLL0 and 1 */ - udelay (1000); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, - 0x802e0044); /* D=0.25% */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, - 0x80000000 | pll0_config[i].ctrl0); -#endif /* CONFIG_SYS_CLK_SPREAD */ - -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif - printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000); - printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000); - - /* - * All the information needed to print the cache details is avaiblable - * at this point i.e. above call to l2cache_enable is the very last - * thing done with regards to enabling diabling the cache. - * So this seems like a good place to print all this information - */ - - printf ("CACHE: "); - switch (get_cpu_type()) { - case CPU_7447A: - printf ("L1 Instruction cache - 32KB 8-way"); - (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("L1 Data cache - 32KB 8-way"); - (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("Unified L2 cache - 512KB 8-way"); - (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("\n"); - break; - - case CPU_7448: - printf ("L1 Instruction cache - 32KB 8-way"); - (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("L1 Data cache - 32KB 8-way"); - (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("Unified L2 cache - 1MB 8-way"); - (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - break; - default: - break; - } - return 0; -} diff --git a/board/ppmc7xx/Kconfig b/board/ppmc7xx/Kconfig deleted file mode 100644 index f101940..0000000 --- a/board/ppmc7xx/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PPMC7XX - -config SYS_BOARD - default "ppmc7xx" - -config SYS_CONFIG_NAME - default "ppmc7xx" - -endif diff --git a/board/ppmc7xx/MAINTAINERS b/board/ppmc7xx/MAINTAINERS deleted file mode 100644 index a0c1f44..0000000 --- a/board/ppmc7xx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PPMC7XX BOARD -#M: - -S: Maintained -F: board/ppmc7xx/ -F: include/configs/ppmc7xx.h -F: configs/ppmc7xx_defconfig diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile deleted file mode 100644 index f8957f3..0000000 --- a/board/ppmc7xx/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := init.o -obj-y += ppmc7xx.o pci.o flash.o diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c deleted file mode 100644 index e724227..0000000 --- a/board/ppmc7xx/flash.c +++ /dev/null @@ -1,494 +0,0 @@ -/* - * flash.c - * ------- - * - * Flash programming routines for the Wind River PPMC 74xx/7xx - * based on flash.c from the TQM8260 board. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - */ - -#include <common.h> -#include <asm/processor.h> -#include <74xx_7xx.h> - -#define DWORD unsigned long long - -/* Local function prototypes */ -static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata); -static void write_via_fpu (volatile DWORD* addr, DWORD* data); - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -void flash_reset (void) -{ - unsigned long msr; - DWORD cmd_reset = 0x00F000F000F000F0LL; - - if (flash_info[0].flash_id != FLASH_UNKNOWN) { - msr = get_msr (); - set_msr (msr | MSR_FP); - - write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset ); - - set_msr (msr); - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (ulong baseaddr, flash_info_t * info) -{ - int i; - unsigned long msr; - DWORD flashtest; - DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, - 0x0090009000900090LL }; - - /* Enable FPU */ - msr = get_msr (); - set_msr (msr | MSR_FP); - - /* Write auto-select command sequence */ - write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] ); - write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] ); - write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] ); - - /* Restore FPU */ - set_msr (msr); - - /* Read manufacturer ID */ - flashtest = *(volatile DWORD*)baseaddr; - switch ((int)flashtest) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - /* No, faulty or unknown flash */ - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); - } - - /* Read device ID */ - flashtest = *(volatile DWORD*)(baseaddr + 8); - switch ((long)flashtest) { - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00400000; - break; - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; - break; - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00800000; - break; - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00800000; - break; - case AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x01000000; - break; - case AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x01000000; - break; - case AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x01000000; - break; - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x02000000; - break; - default: - /* Unknown flash type */ - info->flash_id = FLASH_UNKNOWN; - return (0); - } - - if ((long)flashtest == AMD_ID_LV640U) { - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - } else if (info->flash_id & FLASH_BTYPE) { - /* set up sector start adress table (bottom sector type) */ - info->start[0] = baseaddr + 0x00000000; - info->start[1] = baseaddr + 0x00010000; - info->start[2] = baseaddr + 0x00018000; - info->start[3] = baseaddr + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; - } - } else { - /* set up sector start adress table (top sector type) */ - i = info->sector_count - 1; - info->start[i--] = baseaddr + info->size - 0x00010000; - info->start[i--] = baseaddr + info->size - 0x00018000; - info->start[i--] = baseaddr + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = baseaddr + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset (); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* - * protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - printf ("29LV800T (8 M, top sector)\n"); - break; - case FLASH_AM800B: - printf ("29LV800T (8 M, bottom sector)\n"); - break; - case FLASH_AM160T: - printf ("29LV160T (16 M, top sector)\n"); - break; - case FLASH_AM160B: - printf ("29LV160B (16 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: - printf ("29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: - printf ("29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: - printf ("29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: - printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: - printf ("29LV640D (64 M, uniform sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned long msr; - DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, - 0x0080008000800080LL, 0x00AA00AA00AA00AALL, - 0x0055005500550055LL, 0x0030003000300030LL }; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Enable FPU */ - msr = get_msr(); - set_msr ( msr | MSR_FP ); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] ); - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] ); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* Restore FPU */ - set_msr (msr); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL ) - != 0x0080008000800080LL ) - { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++; - if ((rc = write_dword (info, dp, bb)) != 0) { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword (info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : *(char*)(dp + i); - } - return (write_dword (info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) -{ - ulong start; - unsigned long msr; - int flag, i; - DWORD data; - DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, - 0x00A000A000A000A0LL }; - - for (data = 0, i = 0; i < 8; i++) - data = (data << 8) + *pdata++; - - /* Check if Flash is (sufficiently) erased */ - if ((*(DWORD*)dest & data) != data) { - return (2); - } - - /* Enable FPU */ - msr = get_msr(); - set_msr( msr | MSR_FP ); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] ); - write_via_fpu ((DWORD*)dest, &data ); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* Restore FPU */ - set_msr(msr); - - /* data polling for D7 */ - start = get_timer (0); - while (*(volatile DWORD*)dest != data ) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu (volatile DWORD* addr, DWORD* data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); - __asm__ __volatile__ ("eieio"); -} diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S deleted file mode 100644 index 99a818a..0000000 --- a/board/ppmc7xx/init.S +++ /dev/null @@ -1,336 +0,0 @@ -/* - * init.S - * ------ - * - * Wind River PPMC 7xx/74xx init code. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - * - * NOTE: The following code was generated automatically by Workbench - * from the ppmc7400_107.reg register file. - */ - -#include <ppc_asm.tmpl> - - -.globl board_asm_init -board_asm_init: - - lis r4,0xFEC0 - ori r4,r4,0x0000 - lis r5,0xFEE0 - ori r5,r5,0x0000 - lis r3,0x8000 # ADDR_00 - ori r3,r3,0x0000 - stwbrx r3,0,r4 - li r3,0x1057 # VENDOR - li r8, 0x0 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_02 - ori r3,r3,0x0002 - stwbrx r3,0,r4 - li r3,0x0004 # ID - li r8, 0x2 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_04 - ori r3,r3,0x0004 - stwbrx r3,0,r4 - li r3,0x0006 # PCICMD - li r8, 0x0 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_06 - ori r3,r3,0x0006 - stwbrx r3,0,r4 - li r3,0x00A0 # PCISTAT - li r8, 0x2 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_08 - ori r3,r3,0x0008 - stwbrx r3,0,r4 - li r3,0x10 # REVID - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_09 - ori r3,r3,0x0009 - stwbrx r3,0,r4 - li r3,0x00 # PROGIR - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_0A - ori r3,r3,0x000A - stwbrx r3,0,r4 - li r3,0x00 # SUBCCODE - stb r3,0x2(r5) - lis r3,0x8000 # ADDR_0B - ori r3,r3,0x000B - stwbrx r3,0,r4 - li r3,0x06 # PBCCR - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_0C - ori r3,r3,0x000C - stwbrx r3,0,r4 - li r3,0x08 # PCLSR - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_0D - ori r3,r3,0x000D - stwbrx r3,0,r4 - li r3,0x00 # PLTR - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_0E - ori r3,r3,0x000E - stwbrx r3,0,r4 - li r3,0x00 # HEADTYPE - stb r3,0x2(r5) - lis r3,0x8000 # ADDR_0F - ori r3,r3,0x000F - stwbrx r3,0,r4 - li r3,0x00 # BISTCTRL - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_10 - ori r3,r3,0x0010 - stwbrx r3,0,r4 - lis r3,0x0000 # LMBAR - ori r3,r3,0x0008 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_14 - ori r3,r3,0x0014 - stwbrx r3,0,r4 - lis r3,0xF000 # PCSRBAR - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_3C - ori r3,r3,0x003C - stwbrx r3,0,r4 - li r3,0x00 # ILR - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_3D - ori r3,r3,0x003D - stwbrx r3,0,r4 - li r3,0x01 # INTPIN - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_3E - ori r3,r3,0x003E - stwbrx r3,0,r4 - li r3,0x00 # MIN_GNT - stb r3,0x2(r5) - lis r3,0x8000 # ADDR_3F - ori r3,r3,0x003F - stwbrx r3,0,r4 - li r3,0x00 # MAX_LAT - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_40 - ori r3,r3,0x0040 - stwbrx r3,0,r4 - li r3,0x00 # BUSNB - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_41 - ori r3,r3,0x0041 - stwbrx r3,0,r4 - li r3,0x00 # SBUSNB - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_46 - ori r3,r3,0x0046 - stwbrx r3,0,r4 -# li r3,0xE080 # PCIARB - li r3,-0x1F80 # PCIARB - li r8, 0x2 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_70 - ori r3,r3,0x0070 - stwbrx r3,0,r4 - li r3,0x0000 # PMCR1 - li r8, 0x0 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_72 - ori r3,r3,0x0072 - stwbrx r3,0,r4 - li r3,0xC0 # PMCR2 - stb r3,0x2(r5) - lis r3,0x8000 # ADDR_73 - ori r3,r3,0x0073 - stwbrx r3,0,r4 - li r3,0xEF # ODCR - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_74 - ori r3,r3,0x0074 - stwbrx r3,0,r4 - li r3,0x7D00 # CLKDCR - li r8, 0x0 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_76 - ori r3,r3,0x0076 - stwbrx r3,0,r4 - li r3,0x00 # MDCR - stb r3,0x2(r5) - lis r6,0xFCE0 - ori r6,r6,0x0000 # r6 is the EUMBAR Base Address - lis r3,0x8000 # ADDR_78 - ori r3,r3,0x0078 - stwbrx r3,0,r4 - lis r3,0xFCE0 # EUMBBAR - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_80 - ori r3,r3,0x0080 - stwbrx r3,0,r4 - lis r3,0xFFFF # MSADDR1 - ori r3,r3,0x4000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_84 - ori r3,r3,0x0084 - stwbrx r3,0,r4 - lis r3,0xFFFF # MSADDR2 - ori r3,r3,0xFFFF - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_88 - ori r3,r3,0x0088 - stwbrx r3,0,r4 - lis r3,0x0303 # EMSADDR1 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_8C - ori r3,r3,0x008C - stwbrx r3,0,r4 - lis r3,0x0303 # EMSADDR2 - ori r3,r3,0x0303 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_90 - ori r3,r3,0x0090 - stwbrx r3,0,r4 - lis r3,0xFFFF # EMEADDR1 - ori r3,r3,0x7F3F - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_94 - ori r3,r3,0x0094 - stwbrx r3,0,r4 - lis r3,0xFFFF # EMEADDR2 - ori r3,r3,0xFFFF - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_98 - ori r3,r3,0x0098 - stwbrx r3,0,r4 - lis r3,0x0303 # EXTEMEM1 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_9C - ori r3,r3,0x009C - stwbrx r3,0,r4 - lis r3,0x0303 # EXTEMEM2 - ori r3,r3,0x0303 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_A0 - ori r3,r3,0x00A0 - stwbrx r3,0,r4 - li r3,0x03 # MEMBNKEN - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_A3 - ori r3,r3,0x00A3 - stwbrx r3,0,r4 - li r3,0x00 # MEMPMODE - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_B8 - ori r3,r3,0x00B8 - stwbrx r3,0,r4 - li r3,0x00 # ECCCNT - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_B9 - ori r3,r3,0x00B9 - stwbrx r3,0,r4 - li r3,0x00 # ECCTRG - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C0 - ori r3,r3,0x00C0 - stwbrx r3,0,r4 - li r3,0xFF # ERRENR1 - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_C1 - ori r3,r3,0x00C1 - stwbrx r3,0,r4 - li r3,0x00 # ERRDR1 - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C3 - ori r3,r3,0x00C3 - stwbrx r3,0,r4 - li r3,0x50 # IPBESR - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_C4 - ori r3,r3,0x00C4 - stwbrx r3,0,r4 - li r3,0xBF # ERRENR2 - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_C5 - ori r3,r3,0x00C5 - stwbrx r3,0,r4 - li r3,0x00 # ERRDR2 - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C7 - ori r3,r3,0x00C7 - stwbrx r3,0,r4 - li r3,0x00 # PCIBESR - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_C8 - ori r3,r3,0x00C8 - stwbrx r3,0,r4 - lis r3,0x0000 # BERRADDR - ori r3,r3,0xE0FE - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_E0 - ori r3,r3,0x00E0 - stwbrx r3,0,r4 - li r3,0xC0 # AMBOR - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_F4 - ori r3,r3,0x00F4 - stwbrx r3,0,r4 - lis r3,0x0000 # MCCR2 - ori r3,r3,0x020C - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_F8 - ori r3,r3,0x00F8 - stwbrx r3,0,r4 - lis r3,0x0230 # MCCR3 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_FC - ori r3,r3,0x00FC - stwbrx r3,0,r4 - lis r3,0x2532 # MCCR4 - ori r3,r3,0x2220 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_F0 - ori r3,r3,0x00F0 - stwbrx r3,0,r4 - lis r3,0xFFC8 # MCCR1 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_A8 - ori r3,r3,0x00A8 - stwbrx r3,0,r4 - lis r3,0xFF14 # PICR1 - ori r3,r3,0x1CC8 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_AC - ori r3,r3,0x00AC - stwbrx r3,0,r4 - lis r3,0x0000 # PICR2 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - - blr diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c deleted file mode 100644 index d81a41a..0000000 --- a/board/ppmc7xx/pci.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI initialisation for the MPC10x. - */ - -#include <common.h> -#include <pci.h> -#include <mpc106.h> - -#ifdef CONFIG_PCI - -struct pci_controller local_hose; - -void pci_init_board(void) -{ - struct pci_controller* hose = (struct pci_controller *)&local_hose; - u16 reg16; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI_MEM_BUS, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_ISA_MEM_BUS, - CONFIG_SYS_ISA_MEM_PHYS, - CONFIG_SYS_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CONFIG_SYS_PCI_IO_BUS, - CONFIG_SYS_PCI_IO_PHYS, - CONFIG_SYS_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CONFIG_SYS_ISA_IO_BUS, - CONFIG_SYS_ISA_IO_PHYS, - CONFIG_SYS_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - MPC106_REG_ADDR, - MPC106_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* Initialises the MPC10x PCI Configuration regs. */ - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* Clear non-reserved bits in status register */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); -} - -#endif /* CONFIG_PCI */ diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c deleted file mode 100644 index 432d366..0000000 --- a/board/ppmc7xx/ppmc7xx.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * ppmc7xx.c - * --------- - * - * Main board-specific routines for Wind River PPMC 7xx/74xx board. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> - - -/* Define some MPC107 (memory controller) registers */ -#define MPC107_EUMB_GCR 0xfce41020 -#define MPC107_EUMB_IACKR 0xfce600a0 - - -/* Function prototypes */ -extern void _start(void); - - -/* - * initdram() - * - * This function normally initialises the (S)DRAM of the system. For this board - * the SDRAM was already initialised by board_asm_init (see init.S) so we just - * return the size of RAM. - */ -phys_size_t initdram( int board_type ) -{ - return CONFIG_SYS_SDRAM_SIZE; -} - - -/* - * after_reloc() - * - * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives - * us an opportunity to do some additional setup before the rest of the system - * is initialised. We don't need to do anything, so we just call board_init_r() - * which should never return. - */ -void after_reloc( ulong dest_addr, gd_t* gd ) -{ - /* Jump to the main U-Boot board init code */ - board_init_r( gd, dest_addr ); -} - - -/* - * checkboard() - * - * We could do some board level checks here, such as working out what version - * it is, but for this board we simply display it's name (on the console). - */ -int checkboard( void ) -{ - puts( "Board: Wind River PPMC 7xx/74xx\n" ); - return 0; -} - - -/* - * misc_init_r - * - * Used for other setup which needs to be done late in the bring-up phase. - */ -int misc_init_r( void ) -{ - /* Reset the EPIC and clear pending interrupts */ - out32r(MPC107_EUMB_GCR, 0xa0000000); - while( in32r( MPC107_EUMB_GCR ) & 0x80000000 ); - out32r( MPC107_EUMB_GCR, 0x20000000 ); - while( in32r( MPC107_EUMB_IACKR ) != 0xff ); - - /* Enable the I-Cache */ - icache_enable(); - - return 0; -} - - -/* - * do_reset() - * - * Shell command to reset the board. - */ -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf( "Resetting...\n" ); - - /* Disabe and invalidate cache */ - icache_disable(); - dcache_disable(); - - /* Jump to cold reset point (in RAM) */ - _start(); - - /* Should never get here */ - while(1) - ; - - return 1; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/configs/ELPPC_defconfig b/configs/ELPPC_defconfig deleted file mode 100644 index c4694ef..0000000 --- a/configs/ELPPC_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_ELPPC=y diff --git a/configs/P3G4_defconfig b/configs/P3G4_defconfig deleted file mode 100644 index 3d219ef..0000000 --- a/configs/P3G4_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_P3G4=y diff --git a/configs/ZUMA_defconfig b/configs/ZUMA_defconfig deleted file mode 100644 index 536f8bb..0000000 --- a/configs/ZUMA_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_ZUMA=y diff --git a/configs/mpc7448hpc2_defconfig b/configs/mpc7448hpc2_defconfig deleted file mode 100644 index f2777dc..0000000 --- a/configs/mpc7448hpc2_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_MPC7448HPC2=y diff --git a/configs/ppmc7xx_defconfig b/configs/ppmc7xx_defconfig deleted file mode 100644 index feefe49..0000000 --- a/configs/ppmc7xx_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_PPMC7XX=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index e1a81d3..b79c5a4 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,11 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +P3G4 powerpc 74xx_7xx - - Wolfgang Denk <wd@denx.de> +ZUMA powerpc 74xx_7xx - - Nye Liu <nyet@zumanetworks.com> +ppmc7xx powerpc 74xx_7xx - - +ELPPC powerpc 74xx_7xx - - +mpc7448hpc2 powerpc 74xx_7xx - - Roy Zang <tie-fei.zang@freescale.com> CPCI405 ppc4xx 405gp 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu> CPCI405DT ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu> CPCI405AB ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu> diff --git a/doc/git-mailrc b/doc/git-mailrc index d90793a..8ba599c 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -98,8 +98,6 @@ alias mpc83xx uboot, kimphill alias mpc85xx uboot, afleming, galak alias mpc86xx uboot, afleming, galak alias ppc4xx uboot, stroese -alias ppc7xx uboot, wd -alias ppc74xx uboot, wd alias sandbox sjg alias sb sandbox diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 83fd9a0..950a247 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -198,12 +198,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) for (bus = hose->first_busno; bus <= hose->last_busno; bus++) #endif for (bdf = PCI_BDF(bus, 0, 0); -#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX) - bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, - PCI_MAX_PCI_FUNCTIONS - 1); -#else bdf < PCI_BDF(bus + 1, 0, 0); -#endif bdf += PCI_BDF(0, 0, 1)) { if (pci_skip_dev(hose, bdf)) continue; diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h deleted file mode 100644 index 3deeeea..0000000 --- a/include/74xx_7xx.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * 74xx_7xx.h - * - * 74xx/7xx specific definitions - */ - -#ifndef __MPC74XX_H__ -#define __MPC74XX_H__ - -/*---------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/*---------------------------------------------------------------- - * l2cr values - */ -#define l2cr 1017 - -#define L2CR_L2E 0x80000000 /* bit 0 - enable */ -#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ -#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */ -#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */ -#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */ -#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */ -#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */ -#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */ -#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */ -#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */ -#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */ -#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */ -#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */ -#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */ -#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */ -#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ -#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ -#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */ -#define L2CR_TS 0x00040000 /* bit 13 - test support on */ -#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */ -#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */ -#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */ -#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */ -#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ - -#ifndef __ASSEMBLY__ -/* cpu ids we detect */ -typedef enum __cpu_t { - CPU_740, CPU_750, - CPU_740P, CPU_750P, - CPU_745, CPU_755, - CPU_750CX, CPU_750FX, CPU_750GX, - CPU_7400, - CPU_7410, - CPU_7447A, CPU_7448, - CPU_7450, CPU_7455, CPU_7457, - CPU_UNKNOWN} cpu_t; - -extern cpu_t get_cpu_type(void); - -#define l1icache_enable icache_enable - -void l2cache_enable(void); -void l1dcache_enable(void); - -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -static __inline__ unsigned long get_hid0 (void) -{ - unsigned long hid0; - asm volatile("mfspr %0, 1008" : "=r" (hid0) :); - return hid0; -} - -static __inline__ unsigned long get_hid1 (void) -{ - unsigned long hid1; - asm volatile("mfspr %0, 1009" : "=r" (hid1) :); - return hid1; -} - -static __inline__ void set_hid0 (unsigned long hid0) -{ - asm volatile("mtspr 1008, %0" : : "r" (hid0)); -} - -static __inline__ void set_hid1 (unsigned long hid1) -{ - asm volatile("mtspr 1009, %0" : : "r" (hid1)); -} - -#endif /* __ASSEMBLY__ */ -#endif /* __MPC74XX_H__ */ diff --git a/include/common.h b/include/common.h index 29350e4..4b3e0d3 100644 --- a/include/common.h +++ b/include/common.h @@ -435,13 +435,6 @@ extern ssize_t spi_read (uchar *, int, uchar *, int); extern ssize_t spi_write (uchar *, int, uchar *, int); #endif -#ifdef CONFIG_EVB64260 -void evb64260_init(void); -void debug_led(int, int); -void display_mem_map(void); -void perform_soft_reset(void); -#endif - /* $(BOARD)/$(BOARD).c */ int board_early_init_f (void); int board_late_init (void); @@ -486,10 +479,6 @@ ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \ defined (CONFIG_MPC5xxx) || \ - defined (CONFIG_74xx_7xx) || \ - defined (CONFIG_74x) || \ - defined (CONFIG_75x) || \ - defined (CONFIG_74xx) || \ defined (CONFIG_MPC85xx) || \ defined (CONFIG_MPC86xx) || \ defined (CONFIG_MPC83xx) diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h deleted file mode 100644 index debfc36..0000000 --- a/include/configs/ELPPC.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define GTREGREAD(x) 0xffffffff /* needed for debug */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#define CONFIG_IPADDR 192.168.0.105 -#define CONFIG_SERVERIP 192.168.0.100 - -#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate */ - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp 1000000; " \ - "setenv bootargs root=ramfs console=ttyS00,9600 " \ - "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ - "${netmask}:${hostname}:eth0:none; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_JFFS2 - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -/* - * choose between COM1 and COM2 as serial console - */ -#define CONFIG_CONS_INDEX 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CONFIG_SYS_BOARD_ASM_INIT -#define CONFIG_MISC_INIT_R - -/* - * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP) - */ -#undef CONFIG_SYS_ADDRESS_MAP_A - -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000 - -#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000 - -#define CONFIG_SYS_ISA_MEM_BUS 0x00000000 -#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000 -#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000 - -#define CONFIG_SYS_PCI_IO_BUS 0x00800000 -#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000 -#define CONFIG_SYS_PCI_IO_SIZE 0x00400000 - -#define CONFIG_SYS_ISA_IO_BUS 0x00000000 -#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000 -#define CONFIG_SYS_ISA_IO_SIZE 0x00800000 - -/* driver defines FDC,IDE,... */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_USR_LED_BASE 0x78000000 -#define CONFIG_SYS_NVRAM_BASE 0xff000000 -#define CONFIG_SYS_UART_BASE 0xff400000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define MPC107_EUMB_ADDR 0xfce00000 -#define MPC107_EUMB_PI 0xfce41090 -#define MPC107_EUMB_GCR 0xfce41020 -#define MPC107_EUMB_IACKR 0xfce600a0 -#define MPC107_I2C_ADDR 0xfce03000 - -/* - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Flash mapping/organization on the MPC10x. - */ -#define FLASH_BASE0_PRELIM 0xff800000 -#define FLASH_BASE1_PRELIM 0xffc00000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1" -#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)" -*/ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ -#undef CONFIG_SYS_MEMTEST - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */ -#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ -#define CONFIG_ENV_ADDR 0x0 -#define CONFIG_ENV_MAP_ADRS 0xff000000 -#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */ -#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ - -/* - * Serial devices - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 24000000 -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8) - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO -#undef CONFIG_PCI_SCAN_SHOW - -/* - * Optional Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10)) -#define VIDEO_TSTC_FCT serial_stub_tstc -#define VIDEO_GETC_FCT serial_stub_getc - -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO - -/* - * Initial BATs - */ -#if 1 - -#define CONFIG_SYS_IBAT0L 0 -#define CONFIG_SYS_IBAT0U 0 -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U - -#define CONFIG_SYS_IBAT1L 0 -#define CONFIG_SYS_IBAT1U 0 -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -#define CONFIG_SYS_IBAT2L 0 -#define CONFIG_SYS_IBAT2U 0 -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -#define CONFIG_SYS_IBAT3L 0 -#define CONFIG_SYS_IBAT3U 0 -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#else - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U - -/* address range for flashes */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* ISA IO space */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* ISA memory space */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#endif - -/* - * Speed settings are board specific - */ -#define CONFIG_SYS_BUS_CLK 100000000 -#define CONFIG_SYS_CPU_CLK 400000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#if 1 -#define L2_INIT 0 /* cpu 750 CXe*/ -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#endif /* __CONFIG_H */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h deleted file mode 100644 index ac75d3e..0000000 --- a/include/configs/P3G4.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -#include "../board/evb64260/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_P3G4 1 /* this is a P3G4 board */ -#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ - -#undef CONFIG_ECC /* enable ECC support */ -/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CONFIG_SYS_BOARD_NAME "P3G4" - -#undef CONFIG_SYS_HUSH_PARSER - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3g4\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_74xx\0" \ - "bootfile=/tftpboot/p3g4/uImage\0" \ - "kernel_addr=ff000000\0" \ - "ramdisk_addr=ff010000\0" \ - "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_UNIVERSE -#define CONFIG_CMD_BSP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 1 -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CONFIG_SYS_GT_REGS 0xf8000000 -#define CONFIG_SYS_DEV_BASE 0xff000000 - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) - -#define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */ -#define CONFIG_SYS_DEV1_SIZE 0 /* unused */ -#define CONFIG_SYS_DEV2_SIZE 0 /* unused */ -#define CONFIG_SYS_DEV3_SIZE 0 /* unused */ - -#define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c -#define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR - -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ - /* DMAAck[1:0] GNT0[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ - /* REQ0[1:0] GNT0[1:0] */ -#endif -#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ - /* DMAReq[4] DMAAck[4] WDNMI WDE */ -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ - /* DMAAck[1:0] GNT1[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ - /* GPP[22] (RS232IntB or PCI1Int) */ - /* GPP[21] (RS323IntA) */ - /* BClkIn */ - /* REQ1[1:0] GNT1[1:0] */ -#endif - -#if 0 /* Wrong?? NTL */ -# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ - /* GPP[27:26] Int[1:0] */ -#else -# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ -#endif - -#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ - -#if 0 /* Wrong?? - NTL */ -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6 -#else -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ - /* gpp[27:26] */ - /* gpp[22:21] */ - -# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 0 - pci use buffer 1,1 - cpu use buffer 0 - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 110110 00 111 0 0 00 1 */ - /* refresh_count=0x200 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ -#endif - -#if 0 -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#endif -#undef CONFIG_SYS_INIT_CHAN1 -#undef CONFIG_SYS_INIT_CHAN2 -#if 0 -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ -#endif - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) - -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C speed and slave address (for compatability) defaults */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* I2C addresses for the two DIMM SPD chips */ -#ifndef CONFIG_EVB64260_750CX -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 -#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ -#define DIMM0_I2C_ADDR 0x54 -#define DIMM1_I2C_ADDR 0x54 -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR 0xFFFE0000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h deleted file mode 100644 index cac6a67..0000000 --- a/include/configs/ZUMA.h +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_ETHER_PORT_MII /* use two MII ports */ -#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */ - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -#include "../board/evb64260/local.h" - -#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */ - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ - -#define CONFIG_ECC /* enable ECC support */ - -#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SYS_BOARD_ASM_INIT - -#define CONFIG_SYS_BOARD_NAME "Zuma APv2" - -#define CONFIG_SYS_HUSH_PARSER - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC - -#define CONFIG_MPSC_PORT 0 - - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND \ - "tftpboot && " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none panic=5 && bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MII /* enable MII commands */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" -#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" -*/ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ - -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CONFIG_SYS_GT_REGS 0xf8000000 /* later mapped GT_REGS */ -#define CONFIG_SYS_DEV_BASE 0xf0000000 -#define CONFIG_SYS_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ -#define CONFIG_SYS_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */ -#define CONFIG_SYS_DEV2_SIZE _8M /* unused */ -#define CONFIG_SYS_DEV3_SIZE _8M /* unused */ - -#define CONFIG_SYS_DEV0_PAR 0xc498243c - /* c 4 9 8 2 4 3 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */ - /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */ - -#define CONFIG_SYS_DEV1_PAR 0xc01b6ac5 - /* c 0 1 b 6 a c 5 */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */ - /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ - - -#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c - -#define CONFIG_SYS_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ -#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ -#define CONFIG_SYS_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ -#define CONFIG_SYS_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */ - /* GPP[27:24] (27 is int4, rest are GPP) */ - -#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */ - -#define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 1 - pci use buffer 0,0 (pci1->0 pci0->0) - cpu use buffer 1 (R*18) - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 111001 00 111 0 0 00 1 */ - - /* refresh count=0x200 - phy interleave disable (by default, - set later by dram config..) - virt interleave enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) - -/*----------------------------------------------------------------------- - * PCI stuff - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -#define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#ifdef CONFIG_750CX -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*------------------------------------------------------------------------ - * Real time clock - */ -#define CONFIG_RTC_DS1302 - - -/*------------------------------------------------------------------------ - * Galileo I2C driver - */ -#define CONFIG_GT_I2C - -#endif /* __CONFIG_H */ diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h deleted file mode 100644 index 0308c52..0000000 --- a/include/configs/mpc7448hpc2.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2005 Freescale Semiconductor, Inc. - * - * (C) Copyright 2006 - * Alex Bounine , Tundra Semiconductor Corp. - * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board specific configuration options for Freescale - * MPC7448HPC2 (High-Performance Computing II) (Taiga) board - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board Configuration Definitions */ -/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */ - -#define CONFIG_MPC7448HPC2 - -#define CONFIG_74xx -#define CONFIG_HIGH_BATS /* High BATs supported */ -#define CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -#define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II" -#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" - -#define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */ -#define CONFIG_SYS_BUS_CLK 133000000 - -#define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ - -#undef CONFIG_ECC /* disable ECC support */ - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -/* Board-specific Initialization Functions to be called */ -#define CONFIG_SYS_BOARD_ASM_INIT -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_MISC_INIT_R - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -#define CONFIG_ENV_OVERWRITE - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TSI "tsi108@c0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * If you have hacked a serial cable onto the second DUART channel, - * change the CONFIG_SYS_DUART port from 1 to 0 below. - * - */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08) - -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -/* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ - setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ - ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" -#endif - -#undef CONFIG_EXTRA_ENV_SETTINGS - -#define CONFIG_SERIAL "No. 1" - -/* Networking Configuration */ - -#define CONFIG_TSI108_ETH -#define CONFIG_TSI108_ETH_NUM_PORTS 2 - - -#define CONFIG_BOOTFILE "zImage.initrd.elf" -#define CONFIG_LOADADDR 0x400000 - -/*-------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_DATE - - -/*set date in u-boot*/ -#define CONFIG_RTC_M48T35A -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 -#define CONFIG_SYS_NVRAM_SIZE 0x8000 -/* - * Miscellaneous configurable options - */ -#define CONFIG_VERSION_VARIABLE 1 -#define CONFIG_TSI108_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized - */ -#undef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000/* larger space - we have SDRAM initialized */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ - -#define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ -#define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ - -#define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ - -#define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ - -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */ -#define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ - -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ - -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0x3fffff00 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* u-boot code base */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* Peripheral Device section */ - -/* - * Resources on the Tsi108 - */ - -#define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ -#define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ - -#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ - -#undef DISABLE_PBM - -/* - * PCI stuff - * - */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_TSI108_PCI /* include tsi108 pci support */ - -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ - -/* PCI view of System Memory */ -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000 - -/* PCI Memory Space */ -#define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS) -#define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */ -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ - -/* PCI I/O Space */ -#define CONFIG_SYS_PCI_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ - -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */ - -/* PCI Config Space mapping */ -#define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ -#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */ - -#define CONFIG_SYS_IBAT0U 0xFE0003FF -#define CONFIG_SYS_IBAT0L 0xFE000002 - -#define CONFIG_SYS_IBAT1U 0x00007FFF -#define CONFIG_SYS_IBAT1L 0x00000012 - -#define CONFIG_SYS_IBAT2U 0x80007FFF -#define CONFIG_SYS_IBAT2L 0x80000022 - -#define CONFIG_SYS_IBAT3U 0x00000000 -#define CONFIG_SYS_IBAT3L 0x00000000 - -#define CONFIG_SYS_IBAT4U 0x00000000 -#define CONFIG_SYS_IBAT4L 0x00000000 - -#define CONFIG_SYS_IBAT5U 0x00000000 -#define CONFIG_SYS_IBAT5L 0x00000000 - -#define CONFIG_SYS_IBAT6U 0x00000000 -#define CONFIG_SYS_IBAT6L 0x00000000 - -#define CONFIG_SYS_IBAT7U 0x00000000 -#define CONFIG_SYS_IBAT7L 0x00000000 - -#define CONFIG_SYS_DBAT0U 0xE0003FFF -#define CONFIG_SYS_DBAT0L 0xE000002A - -#define CONFIG_SYS_DBAT1U 0x00007FFF -#define CONFIG_SYS_DBAT1L 0x00000012 - -#define CONFIG_SYS_DBAT2U 0x00000000 -#define CONFIG_SYS_DBAT2L 0x00000000 - -#define CONFIG_SYS_DBAT3U 0xC0000003 -#define CONFIG_SYS_DBAT3L 0xC000002A - -#define CONFIG_SYS_DBAT4U 0x00000000 -#define CONFIG_SYS_DBAT4L 0x00000000 - -#define CONFIG_SYS_DBAT5U 0x00000000 -#define CONFIG_SYS_DBAT5L 0x00000000 - -#define CONFIG_SYS_DBAT6U 0x00000000 -#define CONFIG_SYS_DBAT6L 0x00000000 - -#define CONFIG_SYS_DBAT7U 0x00000000 -#define CONFIG_SYS_DBAT7L 0x00000000 - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ } - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -#define PHYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_SECT (128) - -#define CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_ADDR 0xFC000000 - -#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ -#undef CONFIG_SYS_L2 - -#define L2_INIT 0 -#define L2_ENABLE (L2_INIT | L2CR_L2E) -#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION -#endif /* __CONFIG_H */ diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h deleted file mode 100644 index 18f9a6c..0000000 --- a/include/configs/ppmc7xx.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * ppmc7xx.h - * --------- - * - * Wind River PPMC 7xx/74xx board configuration file. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPMC7XX - - -/*=================================================================== - * - * User configurable settings - Modify to your preference - * - *=================================================================== - */ - -/* - * Debug - * - * DEBUG - Define this is you want extra debug info - * GTREGREAD - Required to build with debug - * do_bdinfo - Required to build with debug - */ - -#ifdef DEBUG -#define GTREGREAD(x) 0xFFFFFFFF -#define do_bdinfo(a,b,c,d) -#endif - -/* - * CPU type - * - * CONFIG_7xx - We have a 750 or 755 CPU - * CONFIG_74xx - We have a 7400 CPU - * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) - * CONFIG_BUS_CLK - System bus clock in Hz - */ - -#define CONFIG_7xx -#undef CONFIG_74xx -#undef CONFIG_ALTIVEC -#define CONFIG_BUS_CLK 66000000 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -/* - * Monitor configuration - * - * List of command sets to include in shell - * - * The following command sets have been tested and known to work: - * - * CMD_CACHE - Cache control commands - * CMD_MEMORY - Memory display, change and test commands - * CMD_FLASH - Erase and program flash - * CMD_ENV - Environment commands - * CMD_RUN - Run commands stored in env vars - * CMD_ELF - Load ELF files - * CMD_NET - Networking/file download commands - * CMD_PIN - ICMP Echo Request command - * CMD_PCI - PCI Bus scanning command - */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_RUN -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_PCI - -#undef CONFIG_CMD_KGDB - - -/* - * Serial configuration - * - * CONFIG_CONS_INDEX - Serial console port number (COM1) - * CONFIG_BAUDRATE - Serial speed - */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - - -/* - * PCI config - * - * CONFIG_PCI - Enable PCI bus - * CONFIG_PCI_PNP - Enable Plug & Play support - * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup - */ - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW - - -/* - * Network config - * - * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller - * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM - */ - -#define CONFIG_EEPRO100 -#define CONFIG_EEPRO100_SROM_WRITE - - -/* - * Enable extra init functions - * - * CONFIG_MISC_INIT_F - Call pre-relocation init functions - * CONFIG_MISC_INIT_R - Call post relocation init functions - */ - -#undef CONFIG_MISC_INIT_F -#define CONFIG_MISC_INIT_R - - -/* - * Boot config - * - * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot - * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) - */ - -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm" -#define CONFIG_BOOTDELAY 5 - - -/*=================================================================== - * - * Board configuration settings - You should not need to modify these - * - *=================================================================== - */ - - -/* - * Memory map - * - * This board runs in a standard CHRP (Map-B) configuration. - * - * Type Start End Size Width Chip Sel - * ----------- ----------- ----------- ------- ------- -------- - * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 - * User LED's 0x78000000 RCS3 - * UART 0x7C000000 RCS2 - * Mailbox 0xFF000000 RCS1 - * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 - * - * Flash sectors are laid out as follows. - * - * Sector Start End Size Comments - * ------- ----------- ----------- ------- ----------- - * 0 0xFFC00000 0xFFC3FFFF 256KB - * 1 0xFFC40000 0xFFC7FFFF 256KB - * 2 0xFFC80000 0xFFCBFFFF 256KB - * 3 0xFFCC0000 0xFFCFFFFF 256KB - * 4 0xFFD00000 0xFFD3FFFF 256KB - * 5 0xFFD40000 0xFFD7FFFF 256KB - * 6 0xFFD80000 0xFFDBFFFF 256KB - * 7 0xFFDC0000 0xFFDFFFFF 256KB - * 8 0xFFE00000 0xFFE3FFFF 256KB - * 9 0xFFE40000 0xFFE7FFFF 256KB - * 10 0xFFE80000 0xFFEBFFFF 256KB - * 11 0xFFEC0000 0xFFEFFFFF 256KB - * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here - * 13 0xFFF40000 0xFFF7FFFF 256KB - * 14 0xFFF80000 0xFFFBFFFF 256KB - * 15 0xFFFC0000 0xFFFDFFFF 128KB - * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here - * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here - * 18 0xFFFF0000 0xFFFFFFFF 64KB - */ - - -/* - * SDRAM config - see memory map details above. - * - * CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! - * CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) - */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - - -/* - * Flash config - see memory map details above. - * - * CONFIG_SYS_FLASH_BASE - Start address of flash memory - * CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem - * CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms - * CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms - * CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board - * CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank - */ - -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 -#define CONFIG_SYS_FLASH_ERASE_TOUT 250000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 5000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - - -/* - * Monitor config - see memory map details above - * - * CONFIG_SYS_MONITOR_BASE - Base address of monitor code - * CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB) - */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x20000 - - -/* - * Command shell settings - * - * CONFIG_SYS_BARGSIZE - Boot Argument buffer size - * CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB) - * CONFIG_SYS_CBSIZE - Console Buffer (input) size - * CONFIG_SYS_LOAD_ADDR - Default load address - * CONFIG_SYS_LONGHELP - Provide more detailed help - * CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands - * CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM - * CONFIG_SYS_MEMTEST_END - End address of RAM test - * CONFIG_SYS_PBSIZE - Print Buffer (output) size - * CONFIG_SYS_PROMPT - Prompt string - */ - -#define CONFIG_SYS_BARGSIZE 1024 -#define CONFIG_SYS_BOOTMAPSZ 0x800000 -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MEMTEST_START 0x00040000 -#define CONFIG_SYS_MEMTEST_END 0x00040100 -#define CONFIG_SYS_PBSIZE 1024 - - -/* - * Environment config - see memory map details above - * - * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash - * CONFIG_ENV_ADDR - Address of the sector containing env vars - * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB) - * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB) - */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFFE0000 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000 -#define CONFIG_ENV_SIZE_REDUND 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x8000 - - -/* - * Initial RAM config - * - * Since the main system RAM is initialised very early, we place the INIT_RAM - * in the main system RAM just above the exception vectors. The contents are - * copied to top of RAM by the init code. - * - * CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect - * CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM - * GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data - * CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack - */ - -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000) -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/* - * Initial BAT config - * - * BAT0 - System SDRAM - * BAT1 - LED's and Serial Port - * BAT2 - PCI Memory - * BAT3 - PCI I/O including Flash Memory - */ - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - - -/* - * Cache config - * - * CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific) - * CONFIG_SYS_L2 - L2 cache enabled if defined - * L2_INIT - L2 cache init flags - * L2_ENABLE - L2 cache enable flags - */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#undef CONFIG_SYS_L2 -#define L2_INIT 0 -#define L2_ENABLE 0 - - -/* - * Clocks config - * - * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz - * CONFIG_SYS_HZ - Decrementer freq in Hz - */ - -#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK - - -/* - * Serial port config - * - * CONFIG_SYS_NS16550 - Include the NS16550 driver - * CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver - * CONFIG_SYS_NS16550_CLK - Frequency of reference clock - * CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port - * CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port - */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 3686400 -#define CONFIG_SYS_NS16550_REG_SIZE -8 -#define CONFIG_SYS_NS16550_COM1 0x7C000000 - - -/* - * PCI Config - Address Map B (CHRP) - */ - -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000 -#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000 -#define CONFIG_SYS_ISA_MEM_BUS 0x00000000 -#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000 -#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000 -#define CONFIG_SYS_PCI_IO_BUS 0x00800000 -#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000 -#define CONFIG_SYS_PCI_IO_SIZE 0x00400000 -#define CONFIG_SYS_ISA_IO_BUS 0x00000000 -#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000 -#define CONFIG_SYS_ISA_IO_SIZE 0x00800000 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS - - -/* - * Extra init functions - * - * CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code - */ - -#define CONFIG_SYS_BOARD_ASM_INIT - -#endif /* __CONFIG_H */ diff --git a/include/galileo/core.h b/include/galileo/core.h deleted file mode 100644 index 95013fa..0000000 --- a/include/galileo/core.h +++ /dev/null @@ -1,217 +0,0 @@ -/* Core.h - Basic core logic functions and definitions */ - -/* Copyright Galileo Technology. */ - -/* -DESCRIPTION -This header file contains simple read/write macros for addressing -the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address -space). The macros take care of Big/Little endian conversions. -*/ - -#ifndef __INCcoreh -#define __INCcoreh - -/* includes */ -#include "gt64260R.h" -#include <stdbool.h> - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/* - * GT-6426x variants - */ -#define GT_64260 0 /* includes both 64260A and 64260B */ -#define GT_64261 1 - -#if (CONFIG_SYS_GT_6426x == GT_64260) -#ifdef CONFIG_ETHER_PORT_MII -#define GAL_ETH_DEVS 2 -#else -#define GAL_ETH_DEVS 3 -#endif -#elif (CONFIG_SYS_GT_6426x == GT_64261) -#define GAL_ETH_DEVS 2 -#else -#define GAL_ETH_DEVS 3 /* default to a 64260 */ -#endif - -/****************************************/ -/* GENERAL Definitions */ -/****************************************/ - -#define NO_BIT 0x00000000 -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#define _1K 0x00000400 -#define _2K 0x00000800 -#define _4K 0x00001000 -#define _8K 0x00002000 -#define _16K 0x00004000 -#define _32K 0x00008000 -#define _64K 0x00010000 -#define _128K 0x00020000 -#define _256K 0x00040000 -#define _512K 0x00080000 - -#define _1M 0x00100000 -#define _2M 0x00200000 -#define _3M 0x00300000 -#define _4M 0x00400000 -#define _5M 0x00500000 -#define _6M 0x00600000 -#define _7M 0x00700000 -#define _8M 0x00800000 -#define _9M 0x00900000 -#define _10M 0x00a00000 -#define _11M 0x00b00000 -#define _12M 0x00c00000 -#define _13M 0x00d00000 -#define _14M 0x00e00000 -#define _15M 0x00f00000 -#define _16M 0x01000000 - -#define _32M 0x02000000 -#define _64M 0x04000000 -#define _128M 0x08000000 -#define _256M 0x10000000 -#define _512M 0x20000000 - -#define _1G 0x40000000 -#define _2G 0x80000000 - -/* Little to Big endian conversion macros */ - -#ifdef LE /* Little Endian */ -#define SHORT_SWAP(X) (X) -#define WORD_SWAP(X) (X) -#define LONG_SWAP(X) ((l64)(X)) - -#else /* Big Endian */ -#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) - -#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ - (((X)&0xff00)<<8)+ \ - (((X)&0xff0000)>>8)+ \ - (((X)&0xff000000)>>24) - -#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ - (((X)&0xff00ULL)<<40)+ \ - (((X)&0xff0000ULL)<<24)+ \ - (((X)&0xff000000ULL)<<8)+ \ - (((X)&0xff00000000ULL)>>8)+ \ - (((X)&0xff0000000000ULL)>>24)+ \ - (((X)&0xff000000000000ULL)>>40)+ \ - (((X)&0xff00000000000000ULL)>>56)) - -#endif - -#ifndef NULL -#define NULL 0 -#endif - -/* Those two definitions were defined to be compatible with MIPS */ -#define NONE_CACHEABLE 0x00000000 -#define CACHEABLE 0x00000000 - -/* 750 cache line */ -#define CACHE_LINE_SIZE 32 -#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) -#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) - -/* Read/Write to/from GT`s internal registers */ -#define GT_REG_READ(offset, pData) \ -*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ -*pData = WORD_SWAP(*pData) - -#define GTREGREAD(offset) \ - (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) )) - -#define GT_REG_WRITE(offset, data) \ -*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ - WORD_SWAP(data) - -/* Write 32/16/8 bit */ -#define WRITE_CHAR(address, data) \ - *((unsigned char *)(address)) = data -#define WRITE_SHORT(address, data) \ - *((unsigned short *)(address)) = data -#define WRITE_WORD(address, data) \ - *((unsigned int *)(address)) = data - -/* Read 32/16/8 bits - returns data in variable. */ -#define READ_CHAR(address, pData) \ - *pData = *((volatile unsigned char *)(address)) - -#define READ_SHORT(address, pData) \ - *pData = *((volatile unsigned short *)(address)) - -#define READ_WORD(address, pData) \ - *pData = *((volatile unsigned int *)(address)) - -/* Read 32/16/8 bit - returns data direct. */ -#define READCHAR(address) \ - *((volatile unsigned char *)((address) | NONE_CACHEABLE)) - -#define READSHORT(address) \ - *((volatile unsigned short *)((address) | NONE_CACHEABLE)) - -#define READWORD(address) \ - *((volatile unsigned int *)((address) | NONE_CACHEABLE)) - -/* Those two Macros were defined to be compatible with MIPS */ -#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) -#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE) - -/* SET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '1' in the - internal register the bits which given as an input example: - SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '1' in register 0x840 while the other bits stays as is. */ -#define SET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ - regOffset) |= (unsigned int)WORD_SWAP(bits) - -/* RESET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '0' in the - internal register the bits which given as an input example: - RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '0' in register 0x840 while the other bits stays as is. */ -#define RESET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ - | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) - -#endif /* __INCcoreh */ diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h deleted file mode 100644 index b55da9d..0000000 --- a/include/galileo/gt64260R.h +++ /dev/null @@ -1,1194 +0,0 @@ -/* gt64260R.h - GT64260 Internal registers definition file */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCgt64260rh -#define __INCgt64260rh - -#ifndef GT64260 -#define GT64260 -#endif - -/* CPU MASTER CONTROL REGISTER */ -#define CPU_CONFIGURATION 0x0 -#define CPU_MASTER_CONTROL 0x160 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* Sdram's BAR'S */ -#define SCS_0_LOW_DECODE_ADDRESS 0x008 -#define SCS_0_HIGH_DECODE_ADDRESS 0x010 -#define SCS_1_LOW_DECODE_ADDRESS 0x208 -#define SCS_1_HIGH_DECODE_ADDRESS 0x210 -#define SCS_2_LOW_DECODE_ADDRESS 0x018 -#define SCS_2_HIGH_DECODE_ADDRESS 0x020 -#define SCS_3_LOW_DECODE_ADDRESS 0x218 -#define SCS_3_HIGH_DECODE_ADDRESS 0x220 -/* Devices BAR'S */ -#define CS_0_LOW_DECODE_ADDRESS 0x028 -#define CS_0_HIGH_DECODE_ADDRESS 0x030 -#define CS_1_LOW_DECODE_ADDRESS 0x228 -#define CS_1_HIGH_DECODE_ADDRESS 0x230 -#define CS_2_LOW_DECODE_ADDRESS 0x248 -#define CS_2_HIGH_DECODE_ADDRESS 0x250 -#define CS_3_LOW_DECODE_ADDRESS 0x038 -#define CS_3_HIGH_DECODE_ADDRESS 0x040 -#define BOOTCS_LOW_DECODE_ADDRESS 0x238 -#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 - -#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 -#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 -#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 -#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 -#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 -#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 -#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 -#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 -#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 -#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 - -#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 -#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 -#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 -#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 -#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 -#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 -#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 -#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 -#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 -#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 - - -#define INTERNAL_SPACE_DECODE 0x068 - -#define CPU_0_LOW_DECODE_ADDRESS 0x290 -#define CPU_0_HIGH_DECODE_ADDRESS 0x298 -#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 -#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 - -#define PCI_0I_O_ADDRESS_REMAP 0x0f0 -#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 -#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 -#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 -#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 -#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 -#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 -#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 -#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 - -#define PCI_1I_O_ADDRESS_REMAP 0x108 -#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 -#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 -#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 -#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 -#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 -#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 -#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 -#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 - - -/****************************************/ -/* CPU Sync Barrier */ -/****************************************/ - -#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0 -#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8 - - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define CPU_LOW_PROTECT_ADDRESS_0 0x180 -#define CPU_HIGH_PROTECT_ADDRESS_0 0x188 -#define CPU_LOW_PROTECT_ADDRESS_1 0x190 -#define CPU_HIGH_PROTECT_ADDRESS_1 0x198 -#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0 -#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8 -#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0 -#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8 -#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0 -#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8 -#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0 -#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8 -#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0 -#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8 -#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0 -#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8 - - -/****************************************/ -/* Snoop Control */ -/****************************************/ - -#define SNOOP_BASE_ADDRESS_0 0x380 -#define SNOOP_TOP_ADDRESS_0 0x388 -#define SNOOP_BASE_ADDRESS_1 0x390 -#define SNOOP_TOP_ADDRESS_1 0x398 -#define SNOOP_BASE_ADDRESS_2 0x3a0 -#define SNOOP_TOP_ADDRESS_2 0x3a8 -#define SNOOP_BASE_ADDRESS_3 0x3b0 -#define SNOOP_TOP_ADDRESS_3 0x3b8 - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define CPU_ERROR_ADDRESS_LOW 0x070 -#define CPU_ERROR_ADDRESS_HIGH 0x078 -#define CPU_ERROR_DATA_LOW 0x128 -#define CPU_ERROR_DATA_HIGH 0x130 -#define CPU_ERROR_PARITY 0x138 -#define CPU_ERROR_CAUSE 0x140 -#define CPU_ERROR_MASK 0x148 - -/****************************************/ -/* Pslave Debug */ -/****************************************/ - -#define X_0_ADDRESS 0x360 -#define X_0_COMMAND_ID 0x368 -#define X_1_ADDRESS 0x370 -#define X_1_COMMAND_ID 0x378 -#define WRITE_DATA_LOW 0x3c0 -#define WRITE_DATA_HIGH 0x3c8 -#define WRITE_BYTE_ENABLE 0x3e0 -#define READ_DATA_LOW 0x3d0 -#define READ_DATA_HIGH 0x3d8 -#define READ_ID 0x3e8 - - -/****************************************/ -/* SDRAM and Device Address Space */ -/****************************************/ - - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - - -#define SDRAM_CONFIGURATION 0x448 -#define SDRAM_OPERATION_MODE 0x474 -#define SDRAM_ADDRESS_DECODE 0x47c -#define SDRAM_UMA_CONTROL 0x4a4 -#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 -#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac -#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 -#define SDRAM_TIMING 0x4b4 - - -/****************************************/ -/* SDRAM Parameters */ -/****************************************/ - -#define SDRAM_BANK0PARAMETERS 0x44C -#define SDRAM_BANK1PARAMETERS 0x450 -#define SDRAM_BANK2PARAMETERS 0x454 -#define SDRAM_BANK3PARAMETERS 0x458 - - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define SDRAM_ERROR_DATA_LOW 0x484 -#define SDRAM_ERROR_DATA_HIGH 0x480 -#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490 -#define SDRAM_RECEIVED_ECC 0x488 -#define SDRAM_CALCULATED_ECC 0x48c -#define SDRAM_ECC_CONTROL 0x494 -#define SDRAM_ECC_ERROR_COUNTER 0x498 - - -/****************************************/ -/* SDunit Debug (for internal use) */ -/****************************************/ - -#define X0_ADDRESS 0x500 -#define X0_COMMAND_AND_ID 0x504 -#define X0_WRITE_DATA_LOW 0x508 -#define X0_WRITE_DATA_HIGH 0x50c -#define X0_WRITE_BYTE_ENABLE 0x518 -#define X0_READ_DATA_LOW 0x510 -#define X0_READ_DATA_HIGH 0x514 -#define X0_READ_ID 0x51c -#define X1_ADDRESS 0x520 -#define X1_COMMAND_AND_ID 0x524 -#define X1_WRITE_DATA_LOW 0x528 -#define X1_WRITE_DATA_HIGH 0x52c -#define X1_WRITE_BYTE_ENABLE 0x538 -#define X1_READ_DATA_LOW 0x530 -#define X1_READ_DATA_HIGH 0x534 -#define X1_READ_ID 0x53c -#define X0_SNOOP_ADDRESS 0x540 -#define X0_SNOOP_COMMAND 0x544 -#define X1_SNOOP_ADDRESS 0x548 -#define X1_SNOOP_COMMAND 0x54c - - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define DEVICE_BANK0PARAMETERS 0x45c -#define DEVICE_BANK1PARAMETERS 0x460 -#define DEVICE_BANK2PARAMETERS 0x464 -#define DEVICE_BANK3PARAMETERS 0x468 -#define DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define DEVICE_CONTROL 0x4c0 -#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 - - -/****************************************/ -/* Device Interrupt */ -/****************************************/ - -#define DEVICE_INTERRUPT_CAUSE 0x4d0 -#define DEVICE_INTERRUPT_MASK 0x4d4 -#define DEVICE_ERROR_ADDRESS 0x4d8 - -/****************************************/ -/* DMA Record */ -/****************************************/ - -#define CHANNEL0_DMA_BYTE_COUNT 0x800 -#define CHANNEL1_DMA_BYTE_COUNT 0x804 -#define CHANNEL2_DMA_BYTE_COUNT 0x808 -#define CHANNEL3_DMA_BYTE_COUNT 0x80C -#define CHANNEL4_DMA_BYTE_COUNT 0x900 -#define CHANNEL5_DMA_BYTE_COUNT 0x904 -#define CHANNEL6_DMA_BYTE_COUNT 0x908 -#define CHANNEL7_DMA_BYTE_COUNT 0x90C -#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 -#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 -#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 -#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C -#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910 -#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914 -#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918 -#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C -#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 -#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 -#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 -#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C -#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920 -#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924 -#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928 -#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C -#define CHANNEL0NEXT_RECORD_POINTER 0x830 -#define CHANNEL1NEXT_RECORD_POINTER 0x834 -#define CHANNEL2NEXT_RECORD_POINTER 0x838 -#define CHANNEL3NEXT_RECORD_POINTER 0x83C -#define CHANNEL4NEXT_RECORD_POINTER 0x930 -#define CHANNEL5NEXT_RECORD_POINTER 0x934 -#define CHANNEL6NEXT_RECORD_POINTER 0x938 -#define CHANNEL7NEXT_RECORD_POINTER 0x93C -#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 -#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 -#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 -#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C -#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970 -#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974 -#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978 -#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C -#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890 -#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894 -#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898 -#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c -#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990 -#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994 -#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998 -#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c -#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0 -#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4 -#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8 -#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac -#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0 -#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4 -#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8 -#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac -#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0 -#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4 -#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8 -#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc -#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0 -#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4 -#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8 -#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define CHANNEL0CONTROL 0x840 -#define CHANNEL0CONTROL_HIGH 0x880 -#define CHANNEL1CONTROL 0x844 -#define CHANNEL1CONTROL_HIGH 0x884 -#define CHANNEL2CONTROL 0x848 -#define CHANNEL2CONTROL_HIGH 0x888 -#define CHANNEL3CONTROL 0x84C -#define CHANNEL3CONTROL_HIGH 0x88C - -#define CHANNEL4CONTROL 0x940 -#define CHANNEL4CONTROL_HIGH 0x980 -#define CHANNEL5CONTROL 0x944 -#define CHANNEL5CONTROL_HIGH 0x984 -#define CHANNEL6CONTROL 0x948 -#define CHANNEL6CONTROL_HIGH 0x988 -#define CHANNEL7CONTROL 0x94C -#define CHANNEL7CONTROL_HIGH 0x98C - - -/****************************************/ -/* DMA Arbiter */ -/****************************************/ - -#define ARBITER_CONTROL_0_3 0x860 -#define ARBITER_CONTROL_4_7 0x960 - - -/****************************************/ -/* DMA Interrupt */ -/****************************************/ - -#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 -#define CHANELS0_3_INTERRUPT_MASK 0x8c4 -#define CHANELS0_3_ERROR_ADDRESS 0x8c8 -#define CHANELS0_3_ERROR_SELECT 0x8cc -#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0 -#define CHANELS4_7_INTERRUPT_MASK 0x9c4 -#define CHANELS4_7_ERROR_ADDRESS 0x9c8 -#define CHANELS4_7_ERROR_SELECT 0x9cc - - -/****************************************/ -/* DMA Debug (for internal use) */ -/****************************************/ - -#define DMA_X0_ADDRESS 0x8e0 -#define DMA_X0_COMMAND_AND_ID 0x8e4 -#define DMA_X0_WRITE_DATA_LOW 0x8e8 -#define DMA_X0_WRITE_DATA_HIGH 0x8ec -#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8 -#define DMA_X0_READ_DATA_LOW 0x8f0 -#define DMA_X0_READ_DATA_HIGH 0x8f4 -#define DMA_X0_READ_ID 0x8fc -#define DMA_X1_ADDRESS 0x9e0 -#define DMA_X1_COMMAND_AND_ID 0x9e4 -#define DMA_X1_WRITE_DATA_LOW 0x9e8 -#define DMA_X1_WRITE_DATA_HIGH 0x9ec -#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8 -#define DMA_X1_READ_DATA_LOW 0x9f0 -#define DMA_X1_READ_DATA_HIGH 0x9f4 -#define DMA_X1_READ_ID 0x9fc - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define TIMER_COUNTER0 0x850 -#define TIMER_COUNTER1 0x854 -#define TIMER_COUNTER2 0x858 -#define TIMER_COUNTER3 0x85C -#define TIMER_COUNTER_0_3_CONTROL 0x864 -#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c -#define TIMER_COUNTER4 0x950 -#define TIMER_COUNTER5 0x954 -#define TIMER_COUNTER6 0x958 -#define TIMER_COUNTER7 0x95C -#define TIMER_COUNTER_4_7_CONTROL 0x964 -#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968 -#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c - -/****************************************/ -/* PCI Slave Address Decoding */ -/****************************************/ - -#define PCI_0SCS_0_BANK_SIZE 0xc08 -#define PCI_1SCS_0_BANK_SIZE 0xc88 -#define PCI_0SCS_1_BANK_SIZE 0xd08 -#define PCI_1SCS_1_BANK_SIZE 0xd88 -#define PCI_0SCS_2_BANK_SIZE 0xc0c -#define PCI_1SCS_2_BANK_SIZE 0xc8c -#define PCI_0SCS_3_BANK_SIZE 0xd0c -#define PCI_1SCS_3_BANK_SIZE 0xd8c -#define PCI_0CS_0_BANK_SIZE 0xc10 -#define PCI_1CS_0_BANK_SIZE 0xc90 -#define PCI_0CS_1_BANK_SIZE 0xd10 -#define PCI_1CS_1_BANK_SIZE 0xd90 -#define PCI_0CS_2_BANK_SIZE 0xd18 -#define PCI_1CS_2_BANK_SIZE 0xd98 -#define PCI_0CS_3_BANK_SIZE 0xc14 -#define PCI_1CS_3_BANK_SIZE 0xc94 -#define PCI_0CS_BOOT_BANK_SIZE 0xd14 -#define PCI_1CS_BOOT_BANK_SIZE 0xd94 -#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c -#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c -#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 -#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 -#define PCI_0P2P_I_O_BAR_SIZE 0xd24 -#define PCI_1P2P_I_O_BAR_SIZE 0xda4 -#define PCI_0CPU_BAR_SIZE 0xd28 -#define PCI_1CPU_BAR_SIZE 0xda8 -#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 -#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 -#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 -#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 -#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 -#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 -#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c -#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c -#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 -#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 -#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 -#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 -#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 -#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 -#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c -#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c -#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 -#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 -#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 -#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 -#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 -#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 -#define PCI_0DAC_CPU_BAR_SIZE 0xe2c -#define PCI_1DAC_CPU_BAR_SIZE 0xeac -#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c -#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac -#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c -#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc -#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 -#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 -#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 -#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 -#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c -#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc -#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c -#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc -#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 -#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 -#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 -#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 -#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 -#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 -#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 -#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 -#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 -#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 -#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c -#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec -#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 -#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 -#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 -#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 -#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 -#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 -#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 -#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 -#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c -#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c -#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 -#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 -#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 -#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 -#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 -#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 -#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c -#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c -#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 -#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 -#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 -#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 -#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 -#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 -#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c -#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc - -/****************************************/ -/* PCI Control */ -/****************************************/ - -#define PCI_0COMMAND 0xc00 -#define PCI_1COMMAND 0xc80 -#define PCI_0MODE 0xd00 -#define PCI_1MODE 0xd80 -#define PCI_0TIMEOUT_RETRY 0xc04 -#define PCI_1TIMEOUT_RETRY 0xc84 -#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 -#define MSI_0TRIGGER_TIMER 0xc38 -#define MSI_1TRIGGER_TIMER 0xcb8 -#define PCI_0ARBITER_CONTROL 0x1d00 -#define PCI_1ARBITER_CONTROL 0x1d80 -/* changing untill here */ -#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c -#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 -#define PCI_0P2P_CONFIGURATION 0x1d14 -#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 -#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 -#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 -#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 -#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 -#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 -#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60 -#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 -#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 -#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70 -#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 -#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 -#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c -#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 -#define PCI_1P2P_CONFIGURATION 0x1d94 -#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 -#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 -#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 -#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 -#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 -#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 -#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0 -#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 -#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 -#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0 -#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 -#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 - -/****************************************/ -/* PCI Snoop Control */ -/****************************************/ - -#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 -#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 -#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 -#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 -#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 -#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 -#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 -#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 -#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 -#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 -#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 -#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 -#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 -#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 -#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 -#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 -#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 -#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 -#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 -#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 -#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 -#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 -#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 -#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 - -/****************************************/ -/* PCI Configuration Address */ -/****************************************/ - -#define PCI_0CONFIGURATION_ADDRESS 0xcf8 -#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc -#define PCI_1CONFIGURATION_ADDRESS 0xc78 -#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c -#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 -#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 - -/****************************************/ -/* PCI Error Report */ -/****************************************/ - -#define PCI_0SERR_MASK 0xc28 -#define PCI_0ERROR_ADDRESS_LOW 0x1d40 -#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 -#define PCI_0ERROR_DATA_LOW 0x1d48 -#define PCI_0ERROR_DATA_HIGH 0x1d4c -#define PCI_0ERROR_COMMAND 0x1d50 -#define PCI_0ERROR_CAUSE 0x1d58 -#define PCI_0ERROR_MASK 0x1d5c -#define PCI_1SERR_MASK 0xca8 -#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 -#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 -#define PCI_1ERROR_DATA_LOW 0x1dc8 -#define PCI_1ERROR_DATA_HIGH 0x1dcc -#define PCI_1ERROR_COMMAND 0x1dd0 -#define PCI_1ERROR_CAUSE 0x1dd8 -#define PCI_1ERROR_MASK 0x1ddc - - -/****************************************/ -/* Lslave Debug (for internal use) */ -/****************************************/ - -#define L_SLAVE_X0_ADDRESS 0x1d20 -#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 -#define L_SLAVE_X1_ADDRESS 0x1d28 -#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c -#define L_SLAVE_WRITE_DATA_LOW 0x1d30 -#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 -#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 -#define L_SLAVE_READ_DATA_LOW 0x1d38 -#define L_SLAVE_READ_DATA_HIGH 0x1d3c -#define L_SLAVE_READ_ID 0x1d64 - -/****************************************/ -/* PCI Configuration Function 0 */ -/****************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/****************************************/ -/* PCI Configuration Function 1 */ -/****************************************/ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/****************************************/ -/* PCI Configuration Function 2 */ -/****************************************/ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 -#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 -#define PCI_CPU_BASE_ADDRESS 0x21c - -/****************************************/ -/* PCI Configuration Function 4 */ -/****************************************/ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/****************************************/ -/* PCI Configuration Function 5 */ -/****************************************/ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/****************************************/ -/* PCI Configuration Function 6 */ -/****************************************/ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/****************************************/ -/* PCI Configuration Function 7 */ -/****************************************/ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 -#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68 -#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c -#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c -#define CPU_SELECT_CAUSE_REGISTER 0xc70 -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24 -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64 -#define PCI_0SELECT_CAUSE 0xc74 -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4 -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4 -#define PCI_1SELECT_CAUSE 0xcf4 -#define CPU_INT_0_MASK 0xe60 -#define CPU_INT_1_MASK 0xe64 -#define CPU_INT_2_MASK 0xe68 -#define CPU_INT_3_MASK 0xe6c - -/****************************************/ -/* I20 Support registers */ -/****************************************/ - -#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C -#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C - -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C - -/****************************************/ -/* Communication Unit Registers */ -/****************************************/ - -#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200 -#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 -#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 -#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c -#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 -#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 -#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 -#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 -#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 -#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 -#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c -#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 -#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 -#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 -#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 -#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 -#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 -#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c -#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 -#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 -#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 -#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 -#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 -#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 -#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c -#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 -#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 -#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0 -#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4 -#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 -#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc -#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 -#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 -#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 -#define SERIAL_INIT_LAST_DATA 0xf324 -#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 -#define COMM_UNIT_ARBITER_CONTROL 0xf300 -#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 -#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 -#define COMM_UNIT_INTERRUPT_MASK 0xf314 -#define COMM_UNIT_ERROR_ADDRESS 0xf314 - -/****************************************/ -/* Cunit Debug (for internal use) */ -/****************************************/ - -#define CUNIT_ADDRESS 0xf340 -#define CUNIT_COMMAND_AND_ID 0xf344 -#define CUNIT_WRITE_DATA_LOW 0xf348 -#define CUNIT_WRITE_DATA_HIGH 0xf34c -#define CUNIT_WRITE_BYTE_ENABLE 0xf358 -#define CUNIT_READ_DATA_LOW 0xf350 -#define CUNIT_READ_DATA_HIGH 0xf354 -#define CUNIT_READ_ID 0xf35c - -/****************************************/ -/* Fast Ethernet Unit Registers */ -/****************************************/ - -/* Ethernet */ - -#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 -#define ETHERNET_SMI_REGISTER 0x2010 - -/* Ethernet 0 */ - -#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 -#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 -#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 -#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 -#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 -#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 -#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 -#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 -#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 -#define ETHERNET0_MIB_COUNTER_BASE 0x2500 - -/* Ethernet 1 */ - -#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 -#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 -#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 -#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 -#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 -#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 -#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 -#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 -#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 -#define ETHERNET1_MIB_COUNTER_BASE 0x2900 - -/* Ethernet 2 */ - -#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 -#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 -#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 -#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 -#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 -#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 -#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 -#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 -#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 -#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 - -/****************************************/ -/* SDMA Registers */ -/****************************************/ - -#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 -#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 -#define CHANNEL0_COMMAND_REGISTER 0x4008 -#define CHANNEL0_RX_CMD_STATUS 0x4800 -#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 -#define CHANNEL0_RX_BUFFER_POINTER 0x4808 -#define CHANNEL0_RX_NEXT_POINTER 0x480c -#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 -#define CHANNEL0_TX_CMD_STATUS 0x4C00 -#define CHANNEL0_TX_PACKET_SIZE 0x4C04 -#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 -#define CHANNEL0_TX_NEXT_POINTER 0x4C0c -#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 -#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 -#define CHANNEL1_CONFIGURATION_REGISTER 0x5000 -#define CHANNEL1_COMMAND_REGISTER 0x5008 -#define CHANNEL1_RX_CMD_STATUS 0x5800 -#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804 -#define CHANNEL1_RX_BUFFER_POINTER 0x5808 -#define CHANNEL1_RX_NEXT_POINTER 0x580c -#define CHANNEL1_TX_CMD_STATUS 0x5C00 -#define CHANNEL1_TX_PACKET_SIZE 0x5C04 -#define CHANNEL1_TX_BUFFER_POINTER 0x5C08 -#define CHANNEL1_TX_NEXT_POINTER 0x5C0c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810 -#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10 -#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14 -#define CHANNEL2_CONFIGURATION_REGISTER 0x6000 -#define CHANNEL2_COMMAND_REGISTER 0x6008 -#define CHANNEL2_RX_CMD_STATUS 0x6800 -#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804 -#define CHANNEL2_RX_BUFFER_POINTER 0x6808 -#define CHANNEL2_RX_NEXT_POINTER 0x680c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_TX_CMD_STATUS 0x6C00 -#define CHANNEL2_TX_PACKET_SIZE 0x6C04 -#define CHANNEL2_TX_BUFFER_POINTER 0x6C08 -#define CHANNEL2_TX_NEXT_POINTER 0x6C0c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 -#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 - -/* SDMA Interrupt */ - -#define SDMA_CAUSE 0xb820 -#define SDMA_MASK 0xb8a0 - - -/****************************************/ -/* Baude Rate Generators Registers */ -/****************************************/ - -/* BRG 0 */ - -#define BRG0_CONFIGURATION_REGISTER 0xb200 -#define BRG0_BAUDE_TUNING_REGISTER 0xb204 - -/* BRG 1 */ - -#define BRG1_CONFIGURATION_REGISTER 0xb208 -#define BRG1_BAUDE_TUNING_REGISTER 0xb20c - -/* BRG 2 */ - -#define BRG2_CONFIGURATION_REGISTER 0xb210 -#define BRG2_BAUDE_TUNING_REGISTER 0xb214 - -/* BRG Interrupts */ - -#define BRG_CAUSE_REGISTER 0xb834 -#define BRG_MASK_REGISTER 0xb8b4 - -/* MISC */ - -#define MAIN_ROUTING_REGISTER 0xb400 -#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 -#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 -#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c -#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 -#define WATCHDOG_VALUE_REGISTER 0xb414 - - -/****************************************/ -/* Flex TDM Registers */ -/****************************************/ - -/* FTDM Port */ - -#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 -#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 -#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 -#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c -#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 -#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 -#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 - -/* FTDM Interrupts */ - -#define FTDM_CAUSE_REGISTER 0xb830 -#define FTDM_MASK_REGISTER 0xb8b0 - - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define GPP_IO_CONTROL 0xf100 -#define GPP_LEVEL_CONTROL 0xf110 -#define GPP_VALUE 0xf104 -#define GPP_INTERRUPT_CAUSE 0xf108 -#define GPP_INTERRUPT_MASK 0xf10c - -#define MPP_CONTROL0 0xf000 -#define MPP_CONTROL1 0xf004 -#define MPP_CONTROL2 0xf008 -#define MPP_CONTROL3 0xf00c -#define DEBUG_PORT_MULTIPLEX 0xf014 -#define SERIAL_PORT_MULTIPLEX 0xf010 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define I2C_SLAVE_ADDRESS 0xc000 -#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 -#define I2C_DATA 0xc004 -#define I2C_CONTROL 0xc008 -#define I2C_STATUS_BAUDE_RATE 0xc00C -#define I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* MPSC Registers */ -/****************************************/ - -/* MPSC0 */ - -#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 -#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 -#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 -#define CHANNEL0_REGISTER1 0x800c -#define CHANNEL0_REGISTER2 0x8010 -#define CHANNEL0_REGISTER3 0x8014 -#define CHANNEL0_REGISTER4 0x8018 -#define CHANNEL0_REGISTER5 0x801c -#define CHANNEL0_REGISTER6 0x8020 -#define CHANNEL0_REGISTER7 0x8024 -#define CHANNEL0_REGISTER8 0x8028 -#define CHANNEL0_REGISTER9 0x802c -#define CHANNEL0_REGISTER10 0x8030 -#define CHANNEL0_REGISTER11 0x8034 - -/* MPSC1 */ - -#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840 -#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844 -#define MPSC1_PROTOCOL_CONFIGURATION 0x8848 -#define CHANNEL1_REGISTER1 0x884c -#define CHANNEL1_REGISTER2 0x8850 -#define CHANNEL1_REGISTER3 0x8854 -#define CHANNEL1_REGISTER4 0x8858 -#define CHANNEL1_REGISTER5 0x885c -#define CHANNEL1_REGISTER6 0x8860 -#define CHANNEL1_REGISTER7 0x8864 -#define CHANNEL1_REGISTER8 0x8868 -#define CHANNEL1_REGISTER9 0x886c -#define CHANNEL1_REGISTER10 0x8870 -#define CHANNEL1_REGISTER11 0x8874 - -/* MPSC2 */ - -#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040 -#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044 -#define MPSC2_PROTOCOL_CONFIGURATION 0x9048 -#define CHANNEL2_REGISTER1 0x904c -#define CHANNEL2_REGISTER2 0x9050 -#define CHANNEL2_REGISTER3 0x9054 -#define CHANNEL2_REGISTER4 0x9058 -#define CHANNEL2_REGISTER5 0x905c -#define CHANNEL2_REGISTER6 0x9060 -#define CHANNEL2_REGISTER7 0x9064 -#define CHANNEL2_REGISTER8 0x9068 -#define CHANNEL2_REGISTER9 0x906c -#define CHANNEL2_REGISTER10 0x9070 -#define CHANNEL2_REGISTER11 0x9074 - -/* MPSCs Interrupts */ - -#define MPSC0_CAUSE 0xb824 -#define MPSC0_MASK 0xb8a4 -#define MPSC1_CAUSE 0xb828 -#define MPSC1_MASK 0xb8a8 -#define MPSC2_CAUSE 0xb82c -#define MPSC2_MASK 0xb8ac - -#endif /* __INCgt64260rh */ diff --git a/include/galileo/memory.h b/include/galileo/memory.h deleted file mode 100644 index 0c46c24..0000000 --- a/include/galileo/memory.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Memory.h - Memory mappings and remapping functions declarations */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCmemoryh -#define __INCmemoryh - -/* includes */ - -#include "core.h" - -/* defines */ - -#define DONT_MODIFY 0xffffffff -#define PARITY_SUPPORT 0x40000000 - -#define _8BIT 0x00000000 -#define _16BIT 0x00100000 -#define _32BIT 0x00200000 -#define _64BIT 0x00300000 - -/* typedefs */ - - typedef struct deviceParam -{ /* boundary values */ - unsigned int turnOff; /* 0x0 - 0xf */ - unsigned int acc2First; /* 0x0 - 0x1f */ - unsigned int acc2Next; /* 0x0 - 0x1f */ - unsigned int ale2Wr; /* 0x0 - 0xf */ - unsigned int wrLow; /* 0x0 - 0xf */ - unsigned int wrHigh; /* 0x0 - 0xf */ - unsigned int deviceWidth; /* in Bytes */ -} DEVICE_PARAM; - -typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; -typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; - -typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \ - MEM_REGION3,MEM_REGION4,MEM_REGION5, \ - MEM_REGION6,MEM_REGION7} \ - MEMORY_PROTECT_REGION; -typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \ - MEMORY_ACCESS; -typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \ - MEMORY_ACCESS_WRITE; -typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \ - MEMORY_CACHE_PROTECT; -typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \ - MEMORY_SNOOP_TYPE; -typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \ - MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ - MEMORY_SNOOP_REGION; - -/* functions */ -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); -unsigned int memoryGetDeviceBaseAddress(DEVICE device); -unsigned int memoryGetBankSize(MEMORY_BANK bank); -unsigned int memoryGetDeviceSize(DEVICE device); -unsigned int memoryGetDeviceWidth(DEVICE device); - -/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ -bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); -bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); - -/* Change the Internal Register Base Address to a new given Address. */ -bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); -/* returns internal Register Space Base Address. */ -unsigned int memoryGetInternalRegistersSpace(void); -/* Configurate the protection feature to a given space. */ -bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memoryAccess, - MEMORY_ACCESS_WRITE memoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength); -/* Configurate the snoop feature to a given space. */ -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); -bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -#endif /* __INCmemoryh */ diff --git a/include/galileo/pci.h b/include/galileo/pci.h deleted file mode 100644 index 6ed8b95..0000000 --- a/include/galileo/pci.h +++ /dev/null @@ -1,113 +0,0 @@ -/* PCI.h - PCI functions header file */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCpcih -#define __INCpcih - -/* includes */ - -#include "core.h" -#include "memory.h" - -/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ -#define PCI_MAX_DEVICES 22 - - -/* Macros */ -#define SELF 32 - -/* Defines for the access regions. */ -#define PREFETCH_ENABLE BIT12 -#define PREFETCH_DISABLE NO_BIT -#define DELAYED_READ_ENABLE BIT13 -/* #define CACHING_ENABLE BIT14 */ -/* aggressive prefetch: PCI slave prefetch two burst in advance*/ -#define AGGRESSIVE_PREFETCH BIT16 -/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_LINE_AGGRESSIVE_PREFETCH BIT17 -/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18 -#define MAX_BURST_4 NO_BIT -#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */ -#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */ -#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ -#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ -#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ -#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ -#define PCI_ACCESS_PROTECT BIT28 -#define PCI_WRITE_PROTECT BIT29 - -/* typedefs */ - -typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, - REGION6,REGION7} PCI_ACCESS_REGIONS; - -typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; -typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; - -typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} - PCI_SNOOP_TYPE; -typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, - PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} - PCI_SNOOP_REGION; - -typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; -typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, - PCI_REGION2,PCI_REGION3, - PCI_IO} - PCI_REGION; - -/* read/write configuration registers on local PCI bus. */ -void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data); -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum); - -/* read/write configuration registers on another PCI bus. */ -void pciOverBridgeWriteConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data); -unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum); - -/* Master`s memory space */ -bool pciMapSpace(PCI_HOST host, PCI_REGION region, - unsigned int remapBase, - unsigned int deviceBase, - unsigned int deviceLength); -unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); -unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); - -/* Slave`s memory space */ -void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, - unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); - -/* PCI region options */ - -bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength); - -void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); - -/* PCI arbiter */ - -bool pciArbiterEnable(PCI_HOST host); -bool pciArbiterDisable(PCI_HOST host); -bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5); -bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -#endif /* __INCpcih */ |