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authorChin Liang See <clsee@altera.com>2015-10-17 08:32:56 -0500
committerMarek Vasut <marex@denx.de>2015-11-05 02:34:15 +0100
commita55f28624e97e1e43ac333c39713b8b9435fcbd3 (patch)
treedfca1589ec53187b44907ace0c1a8d0629552bbc
parent4e609b6cb1e6e8cb14c55fd50c73c5affcba26b5 (diff)
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arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash
With a working QSPI calibration, the SCLK can now run up to 100MHz Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
-rw-r--r--arch/arm/dts/socfpga_cyclone5_socdk.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 5465609..9eb5a22 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -89,7 +89,7 @@
#size-cells = <1>;
compatible = "n25q00";
reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ spi-max-frequency = <100000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */