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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-08-24 01:14:03 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-08-26 07:54:17 -0700 |
| commit | a1f1582b73a5c82b3d63697d521dbcef31e05229 (patch) | |
| tree | 02c41d26fc6b8150903bc564acd818678a06450c | |
| parent | cdeb2ba99cb333f7729cd5784ea2de00e265f22f (diff) | |
| download | u-boot-imx-a1f1582b73a5c82b3d63697d521dbcef31e05229.zip u-boot-imx-a1f1582b73a5c82b3d63697d521dbcef31e05229.tar.gz u-boot-imx-a1f1582b73a5c82b3d63697d521dbcef31e05229.tar.bz2 | |
x86: crownbay: Support Topcliff integrated pci uart devices with driver model
In order to make a pci uart device node to be properly bound to its
driver, we need make sure its parent node has a compatible string
which matches a driver that scans all of its child device nodes in
the device tree.
Change all pci bridge nodes under root pci node to use "pci-bridge"
compatible driver, as well as corresponding <reg> properties to
indicate its devfn. At last, adding "u-boot,dm-pre-reloc" to each
of these nodes for driver model to initialize them before relocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | arch/x86/dts/crownbay.dts | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 800901c..3e354c4 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -91,7 +91,6 @@ #address-cells = <3>; #size-cells = <2>; compatible = "pci-x86"; - device_type = "pci"; u-boot,dm-pre-reloc; ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 @@ -100,14 +99,16 @@ pcie@17,0 { #address-cells = <3>; #size-cells = <2>; - compatible = "intel,pci"; - device_type = "pci"; + compatible = "pci-bridge"; + u-boot,dm-pre-reloc; + reg = <0x0000b800 0x0 0x0 0x0 0x0>; topcliff@0,0 { #address-cells = <3>; #size-cells = <2>; - compatible = "intel,pci"; - device_type = "pci"; + compatible = "pci-bridge"; + u-boot,dm-pre-reloc; + reg = <0x00010000 0x0 0x0 0x0 0x0>; pciuart0: uart@a,1 { compatible = "pci8086,8811.00", @@ -115,6 +116,7 @@ "pciclass,070002", "pciclass,0700", "x86-uart"; + u-boot,dm-pre-reloc; reg = <0x00025100 0x0 0x0 0x0 0x0 0x01025110 0x0 0x0 0x0 0x0>; reg-shift = <0>; @@ -128,6 +130,7 @@ "pciclass,070002", "pciclass,0700", "x86-uart"; + u-boot,dm-pre-reloc; reg = <0x00025200 0x0 0x0 0x0 0x0 0x01025210 0x0 0x0 0x0 0x0>; reg-shift = <0>; @@ -141,6 +144,7 @@ "pciclass,070002", "pciclass,0700", "x86-uart"; + u-boot,dm-pre-reloc; reg = <0x00025300 0x0 0x0 0x0 0x0 0x01025310 0x0 0x0 0x0 0x0>; reg-shift = <0>; @@ -154,6 +158,7 @@ "pciclass,070002", "pciclass,0700", "x86-uart"; + u-boot,dm-pre-reloc; reg = <0x00025400 0x0 0x0 0x0 0x0 0x01025410 0x0 0x0 0x0 0x0>; reg-shift = <0>; |