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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2014-01-27 14:07:11 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-02-03 08:38:49 -0800 |
| commit | 9b444be32230160ee6b3e4dbf625b4201ac3897d (patch) | |
| tree | ab0ab4939a7817df65f926d71ae1c8a7c1c39de8 | |
| parent | 5b7672fc49af1b771a7e318522b010fd5b11c4ab (diff) | |
| download | u-boot-imx-9b444be32230160ee6b3e4dbf625b4201ac3897d.zip u-boot-imx-9b444be32230160ee6b3e4dbf625b4201ac3897d.tar.gz u-boot-imx-9b444be32230160ee6b3e4dbf625b4201ac3897d.tar.bz2 | |
powerpc/t104xrdb: Update T1040RDB.h in config folder
Add usb2 node entry in "hwconfig string"
Remove controller interleaving from hwconfig string as T1040
has only one DDR conroller
SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
are move outside so that they are defined for all cases as these
macros are also used by other u-boot code
Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change to commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | include/configs/T1040RDB.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 5e988c2..611b95c 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -79,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -202,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -386,6 +383,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -627,9 +628,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |