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authorStefan Roese <sr@denx.de>2015-07-01 12:55:07 +0200
committerLuka Perkov <luka.perkov@sartura.hr>2015-08-17 18:48:34 +0200
commit8ed20d65010d46fd58121ea9ee9c913abc3d8e13 (patch)
tree81d9385f68d132682aba3aeffc7ecdfc0d1faae6
parent2bd8711ef019ee4247e80a3dfd789f47f26f28f9 (diff)
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arm: mvebu: Change MBUS base addresses and sizes
This patch changes the MBUS base addresses and sizes to use more generic names and also adds defines for the sizes. It also moves the base address to higher addresses. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
-rw-r--r--arch/arm/mach-mvebu/cpu.c14
-rw-r--r--arch/arm/mach-mvebu/include/mach/cpu.h12
2 files changed, 16 insertions, 10 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 9496d5f..7335620 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -19,18 +19,20 @@
static struct mbus_win windows[] = {
/* PCIE MEM address space */
- { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
+ { MBUS_PCI_MEM_BASE, MBUS_PCI_MEM_SIZE,
+ CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
/* PCIE IO address space */
- { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
+ { MBUS_PCI_IO_BASE, MBUS_PCI_IO_SIZE,
+ CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
/* SPI */
- { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
- CPU_ATTR_SPIFLASH },
+ { MBUS_SPI_BASE, MBUS_SPI_SIZE,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
/* NOR */
- { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
- CPU_ATTR_BOOTROM },
+ { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
};
void reset_cpu(unsigned long ignored)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 8bcdef6..674fdaa 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -65,10 +65,14 @@ enum {
/*
* Default Device Address MAP BAR values
*/
-#define DEFADR_PCI_MEM 0x90000000
-#define DEFADR_PCI_IO 0xC0000000
-#define DEFADR_SPIF 0xF4000000
-#define DEFADR_BOOTROM 0xF8000000
+#define MBUS_PCI_MEM_BASE 0xE8000000
+#define MBUS_PCI_MEM_SIZE (128 << 20)
+#define MBUS_PCI_IO_BASE 0xF1100000
+#define MBUS_PCI_IO_SIZE (64 << 10)
+#define MBUS_SPI_BASE 0xF4000000
+#define MBUS_SPI_SIZE (8 << 20)
+#define MBUS_BOOTROM_BASE 0xF8000000
+#define MBUS_BOOTROM_SIZE (8 << 20)
struct mbus_win {
u32 base;