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| author | Marek Vasut <marex@denx.de> | 2016-04-04 17:28:16 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2016-04-20 11:28:44 +0200 |
| commit | 8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1 (patch) | |
| tree | ae45e6bcfb09551775df7068f8d94a9406ac087a | |
| parent | bba7711092a48ef2af00832213c3cb6c2d5f171c (diff) | |
| download | u-boot-imx-8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1.zip u-boot-imx-8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1.tar.gz u-boot-imx-8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1.tar.bz2 | |
ddr: altera: Fix scc_mgr_set() argument order
The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index bf74b4e..3859e66 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -279,7 +279,7 @@ static void scc_mgr_initialize(void) for (i = 0; i < 16; i++) { debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n", __func__, __LINE__, i); - scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i); + scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0); } } |