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authorChris Packham <judge.packham@gmail.com>2016-02-02 12:35:09 +1300
committerStefan Roese <sr@denx.de>2016-04-06 15:40:33 +0200
commit46a16bd895144617575c788d9c2554aeef76ac44 (patch)
treee3229012a8e5f0f1b9ccb6b0571b7bd4634ca3a3
parent9fc56631a4f784ecaf860ae822d48580cd4317ed (diff)
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kirkwood_nand: claim MPP pins on the fly
Claim the MPP pins for the NAND flash controller only when it's actually being used. This allows the pins to be shared with the SPI interface which already supports an equivalent on-access MPP reconfiguration. Reviewed-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--drivers/mtd/nand/kirkwood_nand.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
index 4fc34d6..d734113 100644
--- a/drivers/mtd/nand/kirkwood_nand.c
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
#include <nand.h>
/* NAND Flash Soc registers */
@@ -22,6 +23,8 @@ struct kwnandf_registers {
static struct kwnandf_registers *nf_reg =
(struct kwnandf_registers *)KW_NANDF_BASE;
+static u32 nand_mpp_backup[9] = { 0 };
+
/*
* hardware specific access to control-lines/bits
*/
@@ -49,6 +52,22 @@ static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
void kw_nand_select_chip(struct mtd_info *mtd, int chip)
{
u32 data;
+ static const u32 nand_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ 0
+ };
+
+ if (chip >= 0)
+ kirkwood_mpp_conf(nand_config, nand_mpp_backup);
+ else
+ kirkwood_mpp_conf(nand_mpp_backup, NULL);
data = readl(&nf_reg->ctrl);
data |= NAND_ACTCEBOOT_BIT;