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| author | Marek Vasut <marex@denx.de> | 2015-07-19 07:03:15 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:20 +0200 |
| commit | 37b7b13d4818ca3941dc5f8217ff0fa8d60ce501 (patch) | |
| tree | cd59f56c4f2665a963ce09dc861f9ac4278eac47 | |
| parent | 23e8ea901a87e0a6296ecf135b3b71672d832676 (diff) | |
| download | u-boot-imx-37b7b13d4818ca3941dc5f8217ff0fa8d60ce501.zip u-boot-imx-37b7b13d4818ca3941dc5f8217ff0fa8d60ce501.tar.gz u-boot-imx-37b7b13d4818ca3941dc5f8217ff0fa8d60ce501.tar.bz2 | |
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3
Clean up odd multiline loop, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 16d09c1..3d975f9 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -1633,8 +1633,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp) } /* The dtap increment to find the failing edge is done here. */ - for (; d <= IO_DQS_EN_DELAY_MAX; - d++, work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) { + for (; d <= IO_DQS_EN_DELAY_MAX; d++) { debug_cond(DLEVEL == 2, "%s:%d end-2: dtap=%u\n", __func__, __LINE__, d); @@ -1645,6 +1644,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp) &bit_chk, 0)) { break; } + + work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP; } /* Go back to working dtap */ |