diff options
| author | zhang sanshan <sanshan.zhang@nxp.com> | 2017-05-22 15:17:44 +0800 |
|---|---|---|
| committer | Chen Guoyin <guoyin.chen@nxp.com> | 2017-07-10 15:08:58 +0800 |
| commit | 2c1196079eaf31bd8a7bf5a15e1cbf3c6c7902bb (patch) | |
| tree | 5148602bd0fc6f1d90666fd1d1494bbbc41dbccc | |
| parent | ff92794f05268eac978e9ab3e7d97a651819fe36 (diff) | |
| download | u-boot-imx-2c1196079eaf31bd8a7bf5a15e1cbf3c6c7902bb.zip u-boot-imx-2c1196079eaf31bd8a7bf5a15e1cbf3c6c7902bb.tar.gz u-boot-imx-2c1196079eaf31bd8a7bf5a15e1cbf3c6c7902bb.tar.bz2 | |
MA-9409-3 Add base board support for android and android things.
* add board support for android and android things.
mx6ul_nxpu_iopb, pico-6ul, pico-imx7d, aquila-6ul
reorganize the Kconfig, and fix the redefine issue.
* add android configure into configure-while
* add a common file mx_android_common.h
it will be included by android and android things.
defconfig only include ANDROID_THINGS_SUPPORT or ANDROID_SUPPORT
* move partition_table_valid into f_fastboot.c.
it's a common code.
* add invalidate_dcache_range in fixed order.
It will have salt invalid issue if we do not add it in order
* add display for pico-7d.
Change-Id: I6f8a4876c2f8bbd098034d1e3f53033109300bca
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>
84 files changed, 6461 insertions, 445 deletions
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 0a714db..a3bb47e 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -290,6 +290,12 @@ config TARGET_MX6UL_14X14_EVK select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6UL_NXPU_IOPB + bool "Support mx6ul_nxpu_iopb" + select MX6UL + select DM + select DM_THERMAL + config TARGET_MX6UL_14X14_DDR3_ARM2 bool "mx6ul_14x14_ddr3_arm2" select BOARD_LATE_INIT @@ -337,6 +343,18 @@ config TARGET_MX6ULL_9X9_EVK select DM select DM_THERMAL +config TARGET_PICOSOM_IMX6UL + bool "Support picosom-imx6ul" + select MX6UL + select DM + select DM_THERMAL + +config TARGET_MX6UL_AQUILA + bool "Support mx6ul_aquila" + select MX6UL + select DM + select DM_THERMAL + config TARGET_NITROGEN6X bool "nitrogen6x" @@ -475,6 +493,7 @@ source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6sx_17x17_arm2/Kconfig" source "board/freescale/mx6sx_19x19_arm2/Kconfig" +source "board/freescale/mx6ul_nxpu_iopb/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig" source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig" @@ -488,7 +507,8 @@ source "board/samtec/vining_2000/Kconfig" source "board/liebherr/mccmon6/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" -source "board/technexion/pico-imx6ul/Kconfig" +source "board/freescale/picosom-imx6ul/Kconfig" +source "board/freescale/mx6ul_aquila/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index c4ae258..fed49bd 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -30,6 +30,12 @@ config TARGET_MX7D_12X12_LPDDR3_ARM2 select DM select DM_THERMAL +config TARGET_PICO_IMX7D + bool "Support pico-imx7d" + select MX7D + select DM + select DM_THERMAL + config TARGET_MX7D_12X12_DDR3_ARM2 bool "Support mx7d_12x12_ddr3_arm2" select BOARD_LATE_INIT @@ -82,6 +88,7 @@ source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig" source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig" source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig" source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig" +source "board/freescale/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" source "board/warp7/Kconfig" diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index 8701a36..91f25ae 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -2008,29 +2008,29 @@ struct mxc_ccm_anatop_reg { #define MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET 0 #define MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK (3 << MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET) -#define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i)) -#define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i)) -#define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i)) -#define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i)) -#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) - -#define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4) -#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) -#define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) -#define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) -#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) - -#define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8) -#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) -#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) -#define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) -#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) - -#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12) -#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) -#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) -#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) -#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) +#define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i)) +#define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i)) +#define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i)) +#define CCM_CCGR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i)) +#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) + +#define CCM_GPR_SET(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4) +#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) +#define CCM_SCTRL_SET(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) +#define CCM_CCGR_SET(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) +#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) + +#define CCM_GPR_CLR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8) +#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) +#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) +#define CCM_CCGR_CLR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) +#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) + +#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12) +#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) +#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) +#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) +#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) #define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i)) #define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i)) diff --git a/board/freescale/mx6ul_aquila/Kconfig b/board/freescale/mx6ul_aquila/Kconfig new file mode 100644 index 0000000..e4e0a39 --- /dev/null +++ b/board/freescale/mx6ul_aquila/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6UL_AQUILA + +config SYS_BOARD + default "mx6ul_aquila" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6ul_aquila" + +endif diff --git a/board/freescale/mx6ul_aquila/Makefile b/board/freescale/mx6ul_aquila/Makefile new file mode 100644 index 0000000..4b95075 --- /dev/null +++ b/board/freescale/mx6ul_aquila/Makefile @@ -0,0 +1,12 @@ +# (C) Copyright 2017 Murata Electronics +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# (C) Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_aquila.o + +extra-$(CONFIG_USE_PLUGIN) := plugin.bin +$(obj)/plugin.bin: $(obj)/plugin.o + $(OBJCOPY) -O binary --gap-fill 0xff $< $@ diff --git a/board/freescale/mx6ul_aquila/imximage.cfg b/board/freescale/mx6ul_aquila/imximage.cfg new file mode 100644 index 0000000..12f91b0 --- /dev/null +++ b/board/freescale/mx6ul_aquila/imximage.cfg @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2017 Murata Electronics. + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul-som-evk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* New DDR type MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x415C015C +DATA 4 0x021B0848 0x40404244 +DATA 4 0x021B0850 0x40405A58 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#endif diff --git a/board/freescale/mx6ul_aquila/mx6ul_aquila.c b/board/freescale/mx6ul_aquila/mx6ul_aquila.c new file mode 100644 index 0000000..e087cb6 --- /dev/null +++ b/board/freescale/mx6ul_aquila/mx6ul_aquila.c @@ -0,0 +1,893 @@ +/* + * Copyright (C) 2017 Murata Electronics + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Specified for EVK consisting of Murata Aquila (iMX6UL + PMIC + eMMC + WiFi/BT) + iMX6UL-Base board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <linux/sizes.h> +#include <linux/fb.h> +#include <miiphy.h> +#include <mmc.h> +#include <mxsfb.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +#ifdef CONFIG_POWER +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include "../common/pfuze.h" +#else + #error "Not defined: CONFIG_POWER" +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include <fsl_fastboot.h> +#ifdef CONFIG_ANDROID_RECOVERY +#include <recovery.h> +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define IOX_SDI IMX_GPIO_NR(5, 10) +#define IOX_STCP IMX_GPIO_NR(5, 7) +#define IOX_SHCP IMX_GPIO_NR(5, 11) +#define IOX_OE IMX_GPIO_NR(5, 8) + +static iomux_v3_cfg_t const iox_pads[] = { + /* IOX_SDI */ + MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_SHCP */ + MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_STCP */ + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_nOE */ + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* + * HDMI_nRST --> Q0 + * ENET1_nRST --> Q1 + * ENET2_nRST --> Q2 + * CAN1_2_STBY --> Q3 + * BT_nPWD --> Q4 + * CSI_RST --> Q5 + * CSI_PWDN --> Q6 + * LCD_nPWREN --> Q7 + */ +enum qn { + HDMI_nRST, + ENET1_nRST, + ENET2_nRST, + CAN1_2_STBY, + BT_nPWD, + CSI_RST, + CSI_PWDN, + LCD_nPWREN, +}; + +enum qn_func { + qn_reset, + qn_enable, + qn_disable, +}; + +enum qn_level { + qn_low = 0, + qn_high = 1, +}; + +static enum qn_level seq[3][2] = { + {0, 1}, {1, 1}, {0, 0} +}; + +static enum qn_func qn_output[8] = { + qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, qn_disable, + qn_enable +}; + +void iox74lv_init(void) +{ + int i; + + gpio_direction_output(IOX_OE, 0); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + gpio_direction_output(IOX_OE, 1); +}; + +void iox74lv_set(int index) +{ + int i; + + gpio_direction_output(IOX_OE, 0); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + + if (i == index) + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + else + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + gpio_direction_output(IOX_OE, 1); +}; + + + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, + .gp = IMX_GPIO_NR(1, 28), + }, + .sda = { + .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, + .gp = IMX_GPIO_NR(1, 29), + }, +}; +#else +/* Murata Aquila uses PMIC */ + #error "Need to define CONFIG_SYS_I2C_MXC" +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + +/* Murata Aquila does not use VSELECT, CD and RST_B for WiFi control */ +}; + +/* Murata Aquila uses 8-bit eMMC at uSDHC2 */ +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* + * RST_B + */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_SYS_USE_NAND +/* Murata Aquila uses NAND pads for eMMC at uSDHC2 */ +#error "Cannot define CONFIG_SYS_USE_NAND" +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + else + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI + +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC2_BASE_ADDR, 0, 8}, +}; + +/* Murata Aquila eMMC reset */ +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + int dev_no; + u32 bootsel; + + bootsel = (soc_sbmr & 0x000000FF) >> 6 ; + + /* If not boot from sd/mmc, use default value */ + if (bootsel != 1) + return CONFIG_SYS_MMC_ENV_DEV; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + /* Murata Aquila always use uSDHC2 for eMMC. Note the 1 difference in mapping. */ + if (dev_no == 2 && mx6_esdhc_fused(USDHC2_BASE_ADDR)) + { + dev_no = 1; + } + + return dev_no; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Murata Aquila always use uSDHC2 for eMMC and uSDHC1 for WiFi. Note the 1 difference in mapping. */ + if (dev_no == 1 && mx6_esdhc_fused(USDHC2_BASE_ADDR)) + { + dev_no = 2; + } + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + /* Murata Aquila always has WiFi connected to uSDHC1 which is not available for storage*/ + ret = 0; + break; + case USDHC2_BASE_ADDR: + /* Murata Aquila always has eMMC connected to uSDHC2 */ + ret = 1; + break; + } + + return ret; + +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 --> WiFi + * mmc1 USDHC2 --> eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); + + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + } + } + + return 0; +} + +int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_devno(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#else + #error "Not defined: CONFIG_FSL_ESDHC" +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + /* LCD_RST */ + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev) +{ + enable_lcdif_clock(dev->lcdif_base_addr, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); + + /* Set Brightness to high */ + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); +} + +static struct lcd_panel_info_t const displays[] = {{ + .lcdif_base_addr = MX6UL_LCDIF1_BASE_ADDR, + .depth = 24, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "TFT43AB", + .xres = 480, + .yres = 272, + .pixclock = 108695, + .left_margin = 8, + .right_margin = 4, + .upper_margin = 2, + .lower_margin = 4, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth, + displays[i].lcdif_base_addr); + if (!ret) { + if (displays[i].enable) + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MX6_MODULE_ENET1)) + return -1; + + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + if (check_module_fused(MX6_MODULE_ENET2)) + return -1; + + /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* At default the 3v3 enables the MIC2026 for VBUS power */ +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(1275); + pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(1175); + + pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); + + iox74lv_init(); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: Murata MX6UL-Aquila\n"); + + return 0; +} + +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* No key defined for this board */ + return 0; +} +#endif diff --git a/board/freescale/mx6ul_aquila/plugin.S b/board/freescale/mx6ul_aquila/plugin.S new file mode 100644 index 0000000..802a510 --- /dev/null +++ b/board/freescale/mx6ul_aquila/plugin.S @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +/* DDR script */ +.macro imx6ul_ddr3_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41570155 + str r1, [r0, #0x83C] + ldr r1, =0x4040474A + str r1, [r0, #0x848] + ldr r1, =0x40405550 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x23400A38 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6ul_ddr3_eol_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41490145 + str r1, [r0, #0x83C] + ldr r1, =0x40404546 + str r1, [r0, #0x848] + ldr r1, =0x4040524D + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x00333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D8B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6ul_lpddr2_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000030 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003030 + str r1, [r0, #0x280] + ldr r1, =0x00003030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x85c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00470000 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020012 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00001748 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x0F9F0682 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x00000047 + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025576 + str r1, [r0, #0x004] + ldr r1, =0x00010106 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6UL_9X9_LPDDR2) + imx6ul_lpddr2_evk_setting +#elif defined(CONFIG_DDR3L_MT41K256M16HA) + imx6ul_ddr3_eol_evk_setting +#else + imx6ul_ddr3_evk_setting +#endif +.endm + +/* include the common plugin code here */ +#include <asm/arch/mx6_plugin.S> diff --git a/board/freescale/mx6ul_nxpu_iopb/Kconfig b/board/freescale/mx6ul_nxpu_iopb/Kconfig new file mode 100644 index 0000000..8141c05 --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6UL_NXPU_IOPB + +config SYS_BOARD + default "mx6ul_nxpu_iopb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6ul_nxpu_iopb" + +endif diff --git a/board/freescale/mx6ul_nxpu_iopb/MAINTAINERS b/board/freescale/mx6ul_nxpu_iopb/MAINTAINERS new file mode 100644 index 0000000..600c000 --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/MAINTAINERS @@ -0,0 +1,6 @@ +MX6ULIOPB BOARD +M: Fang Hui <hui.fang@nxp.com> +S: Maintained +F: board/freescale/mx6ul_nxpu_iopb/ +F: include/configs/mx6ul_nxpu_iopb.h +F: configs/mx6ul_nxpu_iopb_defconfig diff --git a/board/freescale/mx6ul_nxpu_iopb/Makefile b/board/freescale/mx6ul_nxpu_iopb/Makefile new file mode 100644 index 0000000..2fdac8d --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/Makefile @@ -0,0 +1,10 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_nxpu_iopb.o + +extra-$(CONFIG_USE_PLUGIN) := plugin.bin +$(obj)/plugin.bin: $(obj)/plugin.o + $(OBJCOPY) -O binary --gap-fill 0xff $< $@ diff --git a/board/freescale/mx6ul_nxpu_iopb/imximage.cfg b/board/freescale/mx6ul_nxpu_iopb/imximage.cfg new file mode 100644 index 0000000..a45ff0d --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/imximage.cfg @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_nxpu_iopb/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#ifdef CONFIG_DDR3L_MT41K256M16HA + +/* DDR type MT41K256M16HA-125 which is EOL */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41490145 +DATA 4 0x021B0848 0x40404546 +DATA 4 0x021B0850 0x4040524D +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x00333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D8B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#else + +/* New DDR type MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41570155 +DATA 4 0x021B0848 0x4040474A +DATA 4 0x021B0850 0x40405550 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif + +#endif diff --git a/board/freescale/mx6ul_nxpu_iopb/mx6ul_nxpu_iopb.c b/board/freescale/mx6ul_nxpu_iopb/mx6ul_nxpu_iopb.c new file mode 100644 index 0000000..7bec9fc --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/mx6ul_nxpu_iopb.c @@ -0,0 +1,572 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <linux/sizes.h> +#include <linux/fb.h> +#include <miiphy.h> +#include <mmc.h> +#include <mxsfb.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +#ifdef CONFIG_POWER +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include "../common/pfuze.h" +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include <fsl_fastboot.h> +#ifdef CONFIG_ANDROID_RECOVERY +#include <recovery.h> +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), /* MDIO */ + MX6_PAD_ENET2_RX_DATA1__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), /* MDC */ + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_LCD_HSYNC__GPIO3_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ + MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + else + printf("Warning: fec_id %d, should be 0\n", fec_id); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 17) + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + dev_no = 1; + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + } + } + + return 0; +} + +int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MX6_MODULE_ENET1)) + return -1; + + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[17](ENET1_TX_CLK), + set gpr1[13](ENET1_CLK_SEL) */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK); + } else { + if (check_module_fused(MX6_MODULE_ENET2)) + return -1; + + /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* At default the 3v3 enables the MIC2026 for VBUS power */ +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value); + value &= ~0x1f; + value |= PFUZE300_SW1AB_SETP(1275); + pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE300_SW1AB_SETP(1175); + + pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + gpio_direction_output(IMX_GPIO_NR(3, 2) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(3, 2) , 1); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL NXPU IOPB\n"); + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* No key defined for this board */ + return 0; +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/mx6ul_nxpu_iopb/plugin.S b/board/freescale/mx6ul_nxpu_iopb/plugin.S new file mode 100755 index 0000000..0c49b35 --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/plugin.S @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +/* DDR script */ +.macro imx6ul_ddr3_iopb_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41570155 + str r1, [r0, #0x83C] + ldr r1, =0x4040474A + str r1, [r0, #0x848] + ldr r1, =0x40405550 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x23400A38 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ul_ddr3_iopb_setting +.endm + +/* include the common plugin code here */ +#include <asm/arch/mx6_plugin.S> diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index a35f724..87730aa 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -21,7 +21,7 @@ #ifdef CONFIG_ANDROID_RECOVERY #include <recovery.h> #endif /*CONFIG_ANDROID_RECOVERY*/ -#endif /*CONFIG_FASTBOOT*/ +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -215,24 +215,6 @@ int board_late_init(void) } #ifdef CONFIG_FSL_FASTBOOT -void board_fastboot_setup(void) -{ - switch (get_boot_device()) { -#if defined(CONFIG_FASTBOOT_STORAGE_MMC) - case SD1_BOOT: - case MMC1_BOOT: - if (!getenv("fastboot_dev")) - setenv("fastboot_dev", "mmc0"); - if (!getenv("bootcmd")) - setenv("bootcmd", "boota mmc0"); - break; -#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ - default: - printf("unsupported boot devices\n"); - break; - } -} - #ifdef CONFIG_ANDROID_RECOVERY int is_recovery_key_pressing(void) { @@ -240,25 +222,5 @@ int is_recovery_key_pressing(void) return 0; } -void board_recovery_setup(void) -{ - int bootdev = get_boot_device(); - switch (bootdev) { -#if defined(CONFIG_FASTBOOT_STORAGE_MMC) - case SD1_BOOT: - case MMC1_BOOT: - if (!getenv("bootcmd_android_recovery")) - setenv("bootcmd_android_recovery", "boota mmc0 recovery"); - break; -#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ - default: - printf("Unsupported bootup device for recovery: dev: %d\n", - bootdev); - return; - } - - printf("setup env for recovery..\n"); - setenv("bootcmd", "run bootcmd_android_recovery"); -} #endif /*CONFIG_ANDROID_RECOVERY*/ #endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/pico-imx7d/Kconfig b/board/freescale/pico-imx7d/Kconfig new file mode 100644 index 0000000..79e12be --- /dev/null +++ b/board/freescale/pico-imx7d/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PICO_IMX7D + +config SYS_BOARD + default "pico-imx7d" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx7" + +config SYS_CONFIG_NAME + default "pico-imx7d" + +endif diff --git a/board/freescale/pico-imx7d/MAINTAINERS b/board/freescale/pico-imx7d/MAINTAINERS new file mode 100644 index 0000000..99c9982 --- /dev/null +++ b/board/freescale/pico-imx7d/MAINTAINERS @@ -0,0 +1,6 @@ +Technexion PICO-IMX7D board +M: Wig Cheng <wig.cheng@technexion.com> +S: Maintained +F: board/pico-imx7d/ +F: include/configs/pico-imx7d.h +F: configs/pico-imx7d_defconfig diff --git a/board/freescale/pico-imx7d/Makefile b/board/freescale/pico-imx7d/Makefile new file mode 100644 index 0000000..30bba14 --- /dev/null +++ b/board/freescale/pico-imx7d/Makefile @@ -0,0 +1,10 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pico-imx7d.o + +extra-$(CONFIG_USE_PLUGIN) := plugin.bin +$(obj)/plugin.bin: $(obj)/plugin.o + $(OBJCOPY) -O binary --gap-fill 0xff $< $@ diff --git a/board/freescale/pico-imx7d/imximage.cfg b/board/freescale/pico-imx7d/imximage.cfg new file mode 100644 index 0000000..0c44c27 --- /dev/null +++ b/board/freescale/pico-imx7d/imximage.cfg @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/pico-imx7d/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000b24 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/pico-imx7d/imximage_512mb.cfg b/board/freescale/pico-imx7d/imximage_512mb.cfg new file mode 100644 index 0000000..e27513d --- /dev/null +++ b/board/freescale/pico-imx7d/imximage_512mb.cfg @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * 2015-2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#if 0 +BOOT_FROM nand +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/toradex/colibri_imx7/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* IOMUXC_GPR_GPR1 */ +DATA 4 0x30340004 0x4F400005 + +/* DDR3L */ +/* assuming MEMC_FREQ_RATIO = 2 */ +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000002 +/* DDRC_MSTR */ +DATA 4 0x307a0000 0x01040001 +/* DDRC_RFSHTMG */ +DATA 4 0x307a0064 0x00400046 +/* DDRC_MP_PCTRL_0 */ +DATA 4 0x307a0490 0x00000001 +/* DDRC_INIT0 */ +DATA 4 0x307a00d0 0x00020083 +/* DDRC_INIT1 */ +DATA 4 0x307a00d4 0x00690000 +/* DDRC_INIT3 MR0/MR1 */ +DATA 4 0x307a00dc 0x09300004 +/* DDRC_INIT4 MR2/MR3 */ +DATA 4 0x307a00e0 0x04080000 +/* DDRC_INIT5 */ +DATA 4 0x307a00e4 0x00100004 +/* DDRC_RANKCTL */ +DATA 4 0x307a00f4 0x0000033f +/* DDRC_DRAMTMG0 */ +DATA 4 0x307a0100 0x09081109 +/* DDRC_DRAMTMG1 */ +DATA 4 0x307a0104 0x0007020D +/* DDRC_DRAMTMG2 */ +DATA 4 0x307a0108 0x03040407 +/* DDRC_DRAMTMG3 */ +DATA 4 0x307a010c 0x00002006 +/* DDRC_DRAMTMG4 */ +DATA 4 0x307a0110 0x04020205 +/* DDRC_DRAMTMG5 */ +DATA 4 0x307a0114 0x03030202 +/* DDRC_DRAMTMG8 */ +DATA 4 0x307a0120 0x00000803 +/* DDRC_ZQCTL0 */ +DATA 4 0x307a0180 0x00800020 +/* DDRC_DFITMG0 */ +DATA 4 0x307a0190 0x02098204 +/* DDRC_DFITMG1 */ +DATA 4 0x307a0194 0x00030303 +/* DDRC_DFIUPD0 */ +DATA 4 0x307a01a0 0x80400003 +/* DDRC_DFIUPD1 */ +DATA 4 0x307a01a4 0x00100020 +/* DDRC_DFIUPD2 */ +DATA 4 0x307a01a8 0x80100004 +/* DDRC_ADDRMAP0 */ +DATA 4 0x307a0200 0x00000015 +/* DDRC_ADDRMAP1 */ +DATA 4 0x307a0204 0x00161616 +/* DDRC_ADDRMAP4 */ +DATA 4 0x307A0210 0x00000F0F +/* DDRC_ADDRMAP5 */ +DATA 4 0x307a0214 0x04040404 +/* DDRC_ADDRMAP6 */ +DATA 4 0x307a0218 0x0F0F0404 +/* DDRC_ODTCFG */ +DATA 4 0x307a0240 0x06000604 +/* DDRC_ODTMAP */ +DATA 4 0x307a0244 0x00000001 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000000 +/* DDR_PHY_PHY_CON0 */ +DATA 4 0x30790000 0x17420f40 +/* DDR_PHY_PHY_CON1 */ +DATA 4 0x30790004 0x10210100 +/* DDR_PHY_PHY_CON4 */ +DATA 4 0x30790010 0x00060807 +/* DDR_PHY_MDLL_CON0 */ +DATA 4 0x307900b0 0x1010007e +/* DDR_PHY_DRVDS_CON0 */ +DATA 4 0x3079009c 0x00000d6e + +/* DDR_PHY_OFFSET_RD_CON0 */ +DATA 4 0x30790020 0x08080808 +/* DDR_PHY_OFFSET_WR_CON0 */ +DATA 4 0x30790030 0x08080808 +/* DDR_PHY_CMD_SDLL_CON0 */ +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 +/* DDR_PHY_ZQ_CON1 */ +CHECK_BITS_SET 4 0x307900c4 0x1 +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000000 +/* IOMUXC_GPR_GPR8 */ +DATA 4 0x30340020 0x00000178 +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000002 +/* DDR_PHY_LP_CON0 */ +DATA 4 0x30790018 0x0000000f + +/* DDRC_STAT */ +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/pico-imx7d/pico-imx7d.c b/board/freescale/pico-imx7d/pico-imx7d.c new file mode 100755 index 0000000..3935a46 --- /dev/null +++ b/board/freescale/pico-imx7d/pico-imx7d.c @@ -0,0 +1,683 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx7-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/io.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <miiphy.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include <asm/arch/clock_slice.h> +#ifdef CONFIG_SYS_I2C_MXC +#include <i2c.h> +#include <asm/imx-common/mxc_i2c.h> +#endif +#if defined(CONFIG_MXC_EPDC) +#include <lcd.h> +#include <mxc_epdc_fb.h> +#endif +#include <asm/arch/crm_regs.h> + +#ifdef CONFIG_VIDEO_MXS +#include <linux/fb.h> +#include <mxsfb.h> +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include <fsl_fastboot.h> +#ifdef CONFIG_ANDROID_RECOVERY +#include <recovery.h> +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + + + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) + +#define EPDC_PAD_CTRL 0x0 + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1*/ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_UART1_RX_DATA__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 | PC, + .gp = IMX_GPIO_NR(4, 0), + }, + .sda = { + .i2c_mode = MX7D_PAD_UART1_TX_DATA__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | PC, + .gp = IMX_GPIO_NR(4, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX7D_PAD_UART2_RX_DATA__I2C2_SCL | PC, + .gpio_mode = MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 | PC, + .gp = IMX_GPIO_NR(4, 2), + }, + .sda = { + .i2c_mode = MX7D_PAD_UART2_TX_DATA__I2C2_SDA | PC, + .gpio_mode = MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 | PC, + .gp = IMX_GPIO_NR(4, 3), + }, +}; + +/* I2C4 for PMIC*/ +struct i2c_pads_info i2c_pad_info4 = { + .scl = { + .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC, + .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC, + .gp = IMX_GPIO_NR(6, 16), + }, + .sda = { + .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC, + .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC, + .gp = IMX_GPIO_NR(6, 17), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart5_pads[] = { + MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_RESET_B__SD1_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +/* SD */ +#ifdef PICO_SD +#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 9) +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__GPIO6_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#else +/* EMMC */ +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14) +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* LCD_VDD_EN */ +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* LCD_BLT_CTRL */ +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Reset LCD */ + gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_direction_output(IMX_GPIO_NR(1, 11) , 1); + /* Set LCD enable to high */ + gpio_direction_output(IMX_GPIO_NR(1, 6) , 1); +} + +static struct lcd_panel_info_t const displays[] = {{ + .lcdif_base_addr = ELCDIF1_IPS_BASE_ADDR, + .depth = 24, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "EJ050NA", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth, + displays[i].lcdif_base_addr); + if (!ret) { + if (displays[i].enable) + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX7D_PAD_SD2_CD_B__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_SD2_WP__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), // Interrupt + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), // Reset pin +}; + +#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11) + + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} +#endif + +static iomux_v3_cfg_t const bcm4339_pads[] = { + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), //wifi reset + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), //bt reset +}; + +static iomux_v3_cfg_t const ccm_clko_pads[] = { + MX7D_PAD_GPIO1_IO03__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_GPIO1_IO02__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_get_env_dev(int devno) +{ + if (2 == devno) + devno--; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + if (1 == dev_no) + dev_no++; + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); /* Assume uSDHC1 sd is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); /* Assume uSDHC3 emmc is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc2 USDHC3 (eMMC) + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); + gpio_request(USDHC3_CD_GPIO, "usdhc3_cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + gpio_direction_output(FEC1_RST_GPIO, 0); + udelay(500); + gpio_set_value(FEC1_RST_GPIO, 1); + + return ret; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHz); + if (ret) + return ret; + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + /*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/ + + unsigned short val; + + /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ +/* phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe7; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); +*/ + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); +#endif + + return 0; +} + +#define BT_RST_GPIO IMX_GPIO_NR(6, 16) +#define WIFI_RST_GPIO IMX_GPIO_NR(6, 17) + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + //pico-imx7 custom initialize + imx_iomux_v3_setup_multiple_pads(bcm4339_pads, ARRAY_SIZE(bcm4339_pads)); + imx_iomux_v3_setup_multiple_pads(ccm_clko_pads, ARRAY_SIZE(ccm_clko_pads)); + + gpio_direction_output(BT_RST_GPIO, 1); + udelay(500); + gpio_direction_output(WIFI_RST_GPIO, 1); + udelay(500); + clock_set_src(IPP_DO_CLKO2,OSC_32K_CLK); + udelay(500); + clock_set_src(IPP_DO_CLKO1,OSC_24M_CLK); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + /* TODO: Nand */ + /*{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},*/ + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 3 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE3000"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE3000_DEVICEID, ®); + pmic_reg_read(p, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 1.025V */ + reg = 0xd; + pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); + + /* decrease SW1B normal voltage to 0.975V */ + pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(975); + pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: i.MX7D PICOSOM\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX7 +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + break; + + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + return 0; +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* No key defined for this board */ + return 0; +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/pico-imx7d/plugin.S b/board/freescale/pico-imx7d/plugin.S new file mode 100755 index 0000000..75033f7 --- /dev/null +++ b/board/freescale/pico-imx7d/plugin.S @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_sabresd_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_sabresd_ddr_setting +.endm + +/* include the common plugin code here */ +#include <asm/arch/mx7_plugin.S> diff --git a/board/freescale/picosom-imx6ul/Kconfig b/board/freescale/picosom-imx6ul/Kconfig new file mode 100644 index 0000000..e6fe3ce --- /dev/null +++ b/board/freescale/picosom-imx6ul/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PICOSOM_IMX6UL + +config SYS_BOARD + default "picosom-imx6ul" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "picosom-imx6ul" + +endif diff --git a/board/freescale/picosom-imx6ul/MAINTAINERS b/board/freescale/picosom-imx6ul/MAINTAINERS new file mode 100644 index 0000000..9ae1ff6 --- /dev/null +++ b/board/freescale/picosom-imx6ul/MAINTAINERS @@ -0,0 +1,6 @@ +Technexion PICOSOM-IMX6UL board +M: Richard Hu <richard.hu@technexion.com> +S: Maintained +F: board/picosom-imx6ul/ +F: include/configs/picosom-imx6ul.h +F: configs/picosom-imx6ul_defconfig diff --git a/board/freescale/picosom-imx6ul/Makefile b/board/freescale/picosom-imx6ul/Makefile new file mode 100644 index 0000000..a16bea9 --- /dev/null +++ b/board/freescale/picosom-imx6ul/Makefile @@ -0,0 +1,7 @@ +# (C) Copyright 2015 Technexion Ltd. +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := picosom-imx6ul.o diff --git a/board/freescale/picosom-imx6ul/imximage.cfg b/board/freescale/picosom-imx6ul/imximage.cfg new file mode 100644 index 0000000..8283673 --- /dev/null +++ b/board/freescale/picosom-imx6ul/imximage.cfg @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41490145 +DATA 4 0x021B0848 0x40404546 +DATA 4 0x021B0850 0x4040524D +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x00333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D8B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/picosom-imx6ul/picosom-imx6ul.c b/board/freescale/picosom-imx6ul/picosom-imx6ul.c new file mode 100644 index 0000000..db0f5b2 --- /dev/null +++ b/board/freescale/picosom-imx6ul/picosom-imx6ul.c @@ -0,0 +1,689 @@ +/* + * Copyright (C) 2015 Technexion Ltd. + * + * Author: Richard Hu <richard.hu@technexion.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <linux/sizes.h> +#include <linux/fb.h> +#include <miiphy.h> +#include <mmc.h> +#include <mxsfb.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +#ifdef CONFIG_POWER +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include "../../freescale/common/pfuze.h" +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include <fsl_fastboot.h> +#ifdef CONFIG_ANDROID_RECOVERY +#include <recovery.h> +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_SD_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define VERSION_DET_DDR_SIZE IMX_GPIO_NR(5, 1) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart6_pads[] = { + MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifndef CONFIG_SYS_USE_NAND + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#endif + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const version_detection_pads[] = { + /* dram size detection */ + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#ifdef CONFIG_SYS_USE_NAND +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec_pads[] = { + MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define RMII_PHY_RESET IMX_GPIO_NR(1, 28) + +static void setup_iomux_fec(int fec_id) +{ + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +} +#endif + +static void setup_iomux_version_detection(void) +{ + SETUP_IOMUX_PADS(version_detection_pads); +} +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { +#ifdef CONFIG_SYS_USE_NAND + { USDHC1_BASE_ADDR, 0, 4 }, +#else + { USDHC1_BASE_ADDR, 0, 8 }, /* 8-bit emmc */ +#endif /* CONFIG_SYS_USE_NAND */ +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_SYS_USE_NAND + ret = !gpio_get_value(USDHC1_CD_GPIO); +#else + ret = 1; +#endif + break; + } + + return ret; + +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + /* LCD_RST */ + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); + + /* Set Brightness to high */ + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); +} + +static struct display_info_t const displays[] = {{ + .lcdif_base_addr = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "TFT43AB", + .xres = 480, + .yres = 272, + .pixclock = 108695, + .left_margin = 8, + .right_margin = 4, + .upper_margin = 2, + .lower_margin = 4, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + gpio_direction_output(RMII_PHY_RESET, 0); + udelay(500); + gpio_direction_output(RMII_PHY_RESET, 1); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* At default the 3v3 enables the MIC2026 for VBUS power */ +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(1275); + pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(1175); + + pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_SYS_USE_NAND + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +void version_detection(void) +{ + setup_iomux_version_detection(); + gpio_direction_input(VERSION_DET_DDR_SIZE); + if (gpio_get_value(VERSION_DET_DDR_SIZE)) + printf("DRAM size is 512MB \r\n"); + else + printf("DRAM size is 256MB \r\n"); +} +int checkboard(void) +{ + version_detection(); + puts("Board: PicoSOM i.mx6UL\n"); + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* No key defined for this board */ + return 0; +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/common/image-android.c b/common/image-android.c index 649080a..0f6de83 100644 --- a/common/image-android.c +++ b/common/image-android.c @@ -87,7 +87,6 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, strcat(commandline, hdr->cmdline); } - printf("Kernel command line: %s\n", commandline); #ifdef CONFIG_SERIAL_TAG struct tag_serialnr serialnr; get_board_serial(&serialnr); diff --git a/configs/mx6dlsabreautoandroid_defconfig b/configs/mx6dlsabreautoandroid_defconfig index e74940e..77a19b6 100644 --- a/configs/mx6dlsabreautoandroid_defconfig +++ b/configs/mx6dlsabreautoandroid_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6dlsabreautoandroid_nand_defconfig b/configs/mx6dlsabreautoandroid_nand_defconfig index 52eec9c..37c46f5 100644 --- a/configs/mx6dlsabreautoandroid_nand_defconfig +++ b/configs/mx6dlsabreautoandroid_nand_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/mx6dlsabresdandroid_defconfig b/configs/mx6dlsabresdandroid_defconfig index fadd345..9300aab 100644 --- a/configs/mx6dlsabresdandroid_defconfig +++ b/configs/mx6dlsabresdandroid_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SABRESD=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6qpsabreautoandroid_defconfig b/configs/mx6qpsabreautoandroid_defconfig index a9a6bdd..e596582 100644 --- a/configs/mx6qpsabreautoandroid_defconfig +++ b/configs/mx6qpsabreautoandroid_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6QP" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6QP,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6qpsabreautoandroid_nand_defconfig b/configs/mx6qpsabreautoandroid_nand_defconfig index 1537f75..1f71ab4 100644 --- a/configs/mx6qpsabreautoandroid_nand_defconfig +++ b/configs/mx6qpsabreautoandroid_nand_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6QP" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6QP,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/mx6qpsabresdandroid_defconfig b/configs/mx6qpsabresdandroid_defconfig index e4ac748..53dc408 100644 --- a/configs/mx6qpsabresdandroid_defconfig +++ b/configs/mx6qpsabresdandroid_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SABRESD=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg,MX6QP" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg,MX6QP,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6qsabreautoandroid_defconfig b/configs/mx6qsabreautoandroid_defconfig index 2d9b401..cd84f7d 100644 --- a/configs/mx6qsabreautoandroid_defconfig +++ b/configs/mx6qsabreautoandroid_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6qsabreautoandroid_nand_defconfig b/configs/mx6qsabreautoandroid_nand_defconfig index 74fd951..8092e78 100644 --- a/configs/mx6qsabreautoandroid_nand_defconfig +++ b/configs/mx6qsabreautoandroid_nand_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/mx6qsabresdandroid_defconfig b/configs/mx6qsabresdandroid_defconfig index 527c2cb..92ab7d4 100644 --- a/configs/mx6qsabresdandroid_defconfig +++ b/configs/mx6qsabresdandroid_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SABRESD=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6slevkandroid_defconfig b/configs/mx6slevkandroid_defconfig index 85aa004..74b6a7b 100644 --- a/configs/mx6slevkandroid_defconfig +++ b/configs/mx6slevkandroid_defconfig @@ -1,8 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SLEVK=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y diff --git a/configs/mx6sxsabreautoandroid_defconfig b/configs/mx6sxsabreautoandroid_defconfig index 89d5415..4e97470 100644 --- a/configs/mx6sxsabreautoandroid_defconfig +++ b/configs/mx6sxsabreautoandroid_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SXSABREAUTO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y diff --git a/configs/mx6sxsabreautoandroid_nand_defconfig b/configs/mx6sxsabreautoandroid_nand_defconfig index 674ad41..e9666b2 100644 --- a/configs/mx6sxsabreautoandroid_nand_defconfig +++ b/configs/mx6sxsabreautoandroid_nand_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SXSABREAUTO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/mx6sxsabresdandroid_defconfig b/configs/mx6sxsabresdandroid_defconfig index 3f8902c..6d5ccd1 100644 --- a/configs/mx6sxsabresdandroid_defconfig +++ b/configs/mx6sxsabresdandroid_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SXSABRESD=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6ul_14x14_evk_android_defconfig b/configs/mx6ul_14x14_evk_android_defconfig index f5e234b..08be190 100644 --- a/configs/mx6ul_14x14_evk_android_defconfig +++ b/configs/mx6ul_14x14_evk_android_defconfig @@ -3,8 +3,7 @@ CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6UL_14X14_EVK=y CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/mx6ul_14x14_evk_brillo_defconfig b/configs/mx6ul_14x14_evk_brillo_defconfig new file mode 100644 index 0000000..23e14c4 --- /dev/null +++ b/configs/mx6ul_14x14_evk_brillo_defconfig @@ -0,0 +1,5 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg,MX6UL,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6ul_aquila_defconfig b/configs/mx6ul_aquila_defconfig new file mode 100644 index 0000000..12e9616 --- /dev/null +++ b/configs/mx6ul_aquila_defconfig @@ -0,0 +1,32 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_aquila/imximage.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_AQUILA=y +CONFIG_BOOTDELAY=3 +CONFIG_EFI_PARTITION=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6ul_nxpu_iopb_defconfig b/configs/mx6ul_nxpu_iopb_defconfig new file mode 100644 index 0000000..dd9959d --- /dev/null +++ b/configs/mx6ul_nxpu_iopb_defconfig @@ -0,0 +1,30 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_nxpu_iopb/imximage.cfg,MX6UL,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_NXPU_IOPB=y +CONFIG_BOOTDELAY=3 +CONFIG_EFI_PARTITION=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y + diff --git a/configs/mx7dsabresdandroid_defconfig b/configs/mx7dsabresdandroid_defconfig index aad1964..0ba135c 100644 --- a/configs/mx7dsabresdandroid_defconfig +++ b/configs/mx7dsabresdandroid_defconfig @@ -6,8 +6,7 @@ CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx7dsabresdbrillo_defconfig b/configs/mx7dsabresdbrillo_defconfig new file mode 100644 index 0000000..7d83b45 --- /dev/null +++ b/configs/mx7dsabresdbrillo_defconfig @@ -0,0 +1,8 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx7ulp_evk_android_defconfig b/configs/mx7ulp_evk_android_defconfig index e2a946e..f45975b 100644 --- a/configs/mx7ulp_evk_android_defconfig +++ b/configs/mx7ulp_evk_android_defconfig @@ -2,8 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX7ULP=y CONFIG_TARGET_MX7ULP_EVK=y CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" -CONFIG_FASTBOOT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg,ANDROID_SUPPORT" CONFIG_EFI_PARTITION=y CONFIG_BOARD_LATE_INIT=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index a2a303c..efefce6 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -1,8 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_PICO_IMX6UL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/pico-imx6ul/imximage.cfg,ANDROID_THINGS_SUPPORT" CONFIG_BOOTDELAY=3 +CONFIG_EFI_PARTITION=y CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig new file mode 100644 index 0000000..57bf3be --- /dev/null +++ b/configs/pico-imx7d_defconfig @@ -0,0 +1,34 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/pico-imx7d/imximage_512mb.cfg,MX7D,ANDROID_THINGS_SUPPORT,DDR_MB=512" +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_PICO_IMX7D=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_BOOTDELAY=3 +CONFIG_EFI_PARTITION=y +CONFIG_VIDEO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/picosom-imx6ul_defconfig b/configs/picosom-imx6ul_defconfig new file mode 100644 index 0000000..5747eef --- /dev/null +++ b/configs/picosom-imx6ul_defconfig @@ -0,0 +1,33 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/picosom-imx6ul/imximage.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_PICOSOM_IMX6UL=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_BOOTDELAY=3 +CONFIG_EFI_PARTITION=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/drivers/crypto/fsl_caam.c b/drivers/crypto/fsl_caam.c index ee556bd..e9edb67 100755 --- a/drivers/crypto/fsl_caam.c +++ b/drivers/crypto/fsl_caam.c @@ -151,6 +151,14 @@ uint32_t caam_decap_blob(uint32_t plain_text, uint32_t blob_addr, uint32_t size) flush_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, ((uint32_t)g_input_ring & ALIGN_MASK) + 128); + invalidate_dcache_range((uint32_t)decap_dsc & ALIGN_MASK, + ((uint32_t)decap_dsc & ALIGN_MASK) + 128); + invalidate_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, + ((uint32_t)g_input_ring & ALIGN_MASK) + 128); + invalidate_dcache_range((uint32_t)blob_addr & ALIGN_MASK, + (((uint32_t)blob_addr + 2 * size + 64) & ALIGN_MASK)); + invalidate_dcache_range((uint32_t)plain_text & ALIGN_MASK, + (((uint32_t)plain_text + 2 * size + 64) & ALIGN_MASK)); /* Increment jobs added */ __raw_writel(1, CAAM_IRJAR0); @@ -160,6 +168,8 @@ uint32_t caam_decap_blob(uint32_t plain_text, uint32_t blob_addr, uint32_t size) // TODO: check if Secure memory is cacheable. flush_dcache_range((uint32_t)g_output_ring & ALIGN_MASK, ((uint32_t)g_output_ring & ALIGN_MASK) + 128); + invalidate_dcache_range((uint32_t)g_output_ring & ALIGN_MASK, + ((uint32_t)g_output_ring & ALIGN_MASK) + 128); /* check that descriptor address is the one expected in the output ring */ if(g_output_ring[0] == (uint32_t)decap_dsc) { @@ -224,6 +234,9 @@ uint32_t caam_gen_blob(uint32_t plain_data_addr, uint32_t blob_addr, uint32_t si (((uint32_t)blob + 2 * size + 64) & ALIGN_MASK)); flush_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, ((uint32_t)g_input_ring & ALIGN_MASK) + 128); + + invalidate_dcache_range((uint32_t)blob & ALIGN_MASK, + (((uint32_t)blob + 2 * size + 64) & ALIGN_MASK)); /* Increment jobs added */ __raw_writel(1, CAAM_IRJAR0); diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 2f19e50..f7974d9 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -1320,7 +1320,7 @@ static int _fastboot_parts_add_ptable_entry(int ptable_index, if (part_get_info(dev_desc, mmc_dos_partition_index, &info)) { - printf("Bad partition index:%d for partition:%s\n", + debug("Bad partition index:%d for partition:%s\n", mmc_dos_partition_index, name); return -1; } @@ -1329,11 +1329,23 @@ static int _fastboot_parts_add_ptable_entry(int ptable_index, ptable[ptable_index].partition_id = mmc_partition_index; ptable[ptable_index].partition_index = mmc_dos_partition_index; strcpy(ptable[ptable_index].name, (const char *)info.name); - strcpy(ptable[ptable_index].fstype, (const char *)info.type); #ifdef CONFIG_PARTITION_UUIDS strcpy(ptable[ptable_index].uuid, (const char *)info.uuid); #endif +#ifdef CONFIG_ANDROID_AB_SUPPORT + if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM_A) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM_B) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA)) +#else + if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DEVICE) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE)) +#endif + strcpy(ptable[ptable_index].fstype, "ext4"); + else + strcpy(ptable[ptable_index].fstype, "emmc"); return 0; } @@ -2112,7 +2124,7 @@ int do_boota(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int mmcc = -1; struct andr_img_hdr *hdr = &boothdr; ulong image_size; - bool check_image_arm64; + bool check_image_arm64 = false; #ifdef CONFIG_SECURE_BOOT #define IVT_SIZE 0x20 #define CSF_PAD_SIZE CONFIG_CSF_SIZE @@ -2233,7 +2245,7 @@ use_given_ptn: } /* flush cache after read */ flush_cache((ulong)load_addr, bootimg_sectors * 512); /* FIXME */ - check_image_arm64 = image_arm64(load_addr + hdr->page_size); + check_image_arm64 = image_arm64((void *)(load_addr + hdr->page_size)); addr = load_addr; #ifdef CONFIG_FASTBOOT_LOCK int verifyresult = -1; @@ -2777,19 +2789,6 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) return; } - else if (is_slotvar(cmd)) { -#ifdef CONFIG_AVB_SUPPORT - if (get_slotvar_avb(&fsl_avb_ab_ops, cmd, - response + strlen(response), chars_left + 1) < 0) - goto fail; -#elif CONFIG_FSL_BOOTCTL - if (get_slotvar(cmd, response + strlen(response), chars_left + 1) < 0) - goto fail; -#else - strncat(response, FASTBOOT_VAR_NO, chars_left); -#endif - } - char *str = cmd; if ((str = strstr(cmd, "partition-size:"))) { str +=strlen("partition-size:"); @@ -2865,6 +2864,18 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) strncat(response, FASTBOOT_VAR_NO, chars_left); } #endif + else if (is_slotvar(cmd)) { +#ifdef CONFIG_AVB_SUPPORT + if (get_slotvar_avb(&fsl_avb_ab_ops, cmd, + response + strlen(response), chars_left + 1) < 0) + goto fail; +#elif defined(CONFIG_FSL_BOOTCTL) + if (get_slotvar(cmd, response + strlen(response), chars_left + 1) < 0) + goto fail; +#else + strncat(response, FASTBOOT_VAR_NO, chars_left); +#endif + } else { char envstr[32]; @@ -2879,7 +2890,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str(response); return; fail: - strncpy(response, "FAIL", 4); + strncpy(response, "FAIL", 5); fastboot_tx_write_str(response); return; } @@ -3167,7 +3178,10 @@ static int partition_table_valid(void) disk_partition_t info; mmc_no = fastboot_devinfo.dev_id; dev_desc = blk_get_dev("mmc", mmc_no); - status = part_get_info(dev_desc, 1, &info); + if (dev_desc) + status = part_get_info(dev_desc, 1, &info); + else + status = -1; return (status == 0); } @@ -3372,7 +3386,7 @@ static const struct cmd_dispatch_info cmd_dispatch_info[] = { .cmd = "set_active", .cb = cb_set_active_avb, }, -#elif CONFIG_FSL_BOOTCTL +#elif defined(CONFIG_FSL_BOOTCTL) { .cmd = "set_active", .cb = cb_set_active, diff --git a/drivers/usb/gadget/fastboot_lock_unlock.c b/drivers/usb/gadget/fastboot_lock_unlock.c index ee26f17..14ef88e 100644 --- a/drivers/usb/gadget/fastboot_lock_unlock.c +++ b/drivers/usb/gadget/fastboot_lock_unlock.c @@ -50,6 +50,7 @@ #endif +int fastboot_flash_find_index(const char *name); #ifndef FASTBOOT_ENCRYPT_LOCK @@ -239,8 +240,6 @@ int fastboot_set_lock_stat(FbLockState lock) { ret = -1; goto fail; } - FB_DEBUG("%s %s partition.start=%d, size=%d\n",FSL_FASTBOOT_FB_DEV, - get_mmc_part(mmc_id), fs_partition.start, fs_partition.size); status = encrypt_lock_store(lock, bdata); if (status < 0) { @@ -289,8 +288,6 @@ FbLockState fastboot_get_lock_stat(void) { ret = g_lockstat; goto fail; } - FB_DEBUG("%s %s partition.start=%d, size=%d\n",FSL_FASTBOOT_FB_DEV, - get_mmc_part(mmc_id), fs_partition.start, fs_partition.size); status = fs_dev_desc->block_read(fs_dev_desc, fs_partition.start, 1, bdata); if (!status) { @@ -343,7 +340,6 @@ void set_fastboot_lock_disable(void) { } lbaint_t target_block = fs_partition.start + fs_partition.size - 1; - FB_DEBUG("target_block.start=%d, size=%d target_block=%d\n", fs_partition.start, fs_partition.size, target_block); status = fs_dev_desc->block_write(fs_dev_desc, target_block, 1, bdata); if (!status) { printf("%s: error in block read\n", __FUNCTION__); @@ -383,7 +379,6 @@ FbLockEnableResult fastboot_lock_enable() { //The data is stored in the last blcok of this partition. lbaint_t target_block = fs_partition.start + fs_partition.size - 1; - FB_DEBUG("target_block.start=%d, size=%d target_block=%d\n", fs_partition.start, fs_partition.size, target_block); status = fs_dev_desc->block_read(fs_dev_desc, target_block, 1, bdata); if (!status) { printf("%s: error in block read\n", __FUNCTION__); @@ -456,7 +451,6 @@ int fastboot_wipe_data_partition(void) printf("error in get device partition for wipe /data\n"); return -1; } - FB_DEBUG("fs->start=%x, size=%d\n", fs_partition.start, fs_partition.size); status = fs_dev_desc->block_erase(fs_dev_desc, fs_partition.start , fs_partition.size ); if (status != fs_partition.size ) { printf("erase not complete\n"); diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 9c8582c..3fa9501 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -388,7 +388,7 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#if defined(CONFIG_FASTBOOT) +#if defined(CONFIG_ANDROID_SUPPORT) #include "mx6sabreandroid_common.h" #else diff --git a/include/configs/mx6sabreandroid_common.h b/include/configs/mx6sabreandroid_common.h index 2f35bd9..20a3b10 100644 --- a/include/configs/mx6sabreandroid_common.h +++ b/include/configs/mx6sabreandroid_common.h @@ -1,19 +1,13 @@ /* * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef MX6_SABRE_ANDROID_COMMON_H #define MX6_SABRE_ANDROID_COMMON_H - -#define CONFIG_CI_UDC -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED - - -#define CONFIG_BCB_SUPPORT -#define CONFIG_CMD_READ +#include "mx_android_common.h" /* For NAND we don't support lock/unlock */ #ifndef CONFIG_NAND_BOOT #define CONFIG_FASTBOOT_LOCK @@ -24,50 +18,9 @@ #define CONFIG_SHA1 #define CONFIG_SHA256 #endif -#define CONFIG_USB_GADGET -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 -#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 -#define CONFIG_G_DNL_MANUFACTURER "FSL" - -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_FLASH - -#define CONFIG_FSL_FASTBOOT -#define CONFIG_ANDROID_RECOVERY - -#if defined CONFIG_NAND_BOOT -#define CONFIG_FASTBOOT_STORAGE_NAND -#elif defined CONFIG_SYS_BOOT_SATA -#define CONFIG_FASTBOOT_STORAGE_SATA -#define CONFIG_FASTBOOT_SATA_NO 0 -#else -#define CONFIG_FASTBOOT_STORAGE_MMC -#endif -#if defined(CONFIG_FASTBOOT_STORAGE_NAND) +#if defined(CONFIG_NAND_BOOT) #define ANDROID_FASTBOOT_NAND_PARTS "16m@64m(boot) 16m@80m(recovery) 1m@96m(misc) 810m@97m(android_root)ubifs" #endif -#define CONFIG_CMD_BOOTA -#define CONFIG_SUPPORT_RAW_INITRD -#define CONFIG_SERIAL_TAG - -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 - #endif /* MX6_SABRE_ANDROID_COMMON_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 1b5ea02..c623513 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -237,7 +237,7 @@ #define CONFIG_WAVEFORM_BUF_SIZE 0x200000 #endif /* CONFIG_SPLASH_SCREEN */ -#if defined(CONFIG_FASTBOOT) +#if defined(CONFIG_ANDROID_SUPPORT) #include "mx6slevkandroid.h" #endif diff --git a/include/configs/mx6slevkandroid.h b/include/configs/mx6slevkandroid.h index 2aee928..4bbe6bb 100644 --- a/include/configs/mx6slevkandroid.h +++ b/include/configs/mx6slevkandroid.h @@ -1,46 +1,17 @@ /* * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef MX6SL_EVK_ANDROID_H #define MX6SL_EVK_ANDROID_H +#include "mx_android_common.h" #include <asm/imx-common/mxc_key_defs.h> -#define CONFIG_CI_UDC -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED - -#define CONFIG_BCB_SUPPORT -#define CONFIG_CMD_READ - -#define CONFIG_USB_GADGET -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 -#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 -#define CONFIG_G_DNL_MANUFACTURER "FSL" - -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_FLASH - -#define CONFIG_FSL_FASTBOOT -#define CONFIG_ANDROID_RECOVERY - -#define CONFIG_FASTBOOT_STORAGE_MMC - -#define CONFIG_CMD_BOOTA -#define CONFIG_SUPPORT_RAW_INITRD -#define CONFIG_SERIAL_TAG - /*keyboard mapping*/ #define CONFIG_VOL_DOWN_KEY KEY_BACK #define CONFIG_POWER_KEY KEY_5 @@ -56,15 +27,4 @@ #define CONFIG_MXC_KPD_COLMAX 4 #define CONFIG_MXC_KPD_ROWMAX 4 -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 - #endif diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 294e099..efc696a 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -326,7 +326,7 @@ #endif #endif -#if defined(CONFIG_FASTBOOT) +#if defined(CONFIG_ANDROID_SUPPORT) #include "mx6sxsabreautoandroid.h" #endif diff --git a/include/configs/mx6sxsabreautoandroid.h b/include/configs/mx6sxsabreautoandroid.h index cfbe92e..fcac0c2 100644 --- a/include/configs/mx6sxsabreautoandroid.h +++ b/include/configs/mx6sxsabreautoandroid.h @@ -1,19 +1,15 @@ /* * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MX6SX_SABREAUTO_ANDROID_H #define __MX6SX_SABREAUTO_ANDROID_H +#include "mx_android_common.h" -#define CONFIG_CI_UDC -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED - -#define CONFIG_BCB_SUPPORT -#define CONFIG_CMD_READ /* For NAND we don't support lock/unlock */ #ifndef CONFIG_NAND_BOOT #define CONFIG_FASTBOOT_LOCK @@ -25,47 +21,9 @@ #define CONFIG_SHA256 #endif -#define CONFIG_USB_GADGET -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 -#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 -#define CONFIG_G_DNL_MANUFACTURER "FSL" - -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_FLASH - -#define CONFIG_FSL_FASTBOOT -#define CONFIG_ANDROID_RECOVERY - -#if defined CONFIG_NAND_BOOT -#define CONFIG_FASTBOOT_STORAGE_NAND -#else -#define CONFIG_FASTBOOT_STORAGE_MMC -#endif #if defined(CONFIG_FASTBOOT_STORAGE_NAND) #define ANDROID_FASTBOOT_NAND_PARTS "16m@64m(boot) 16m@80m(recovery) 1m@96m(misc) 810m@97m(android_root)ubifs" #endif -#define CONFIG_CMD_BOOTA -#define CONFIG_SUPPORT_RAW_INITRD -#define CONFIG_SERIAL_TAG - -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 - #endif diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 0d7ee3b..0575a5d 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -314,7 +314,7 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 -#if defined(CONFIG_FASTBOOT) +#if defined(CONFIG_ANDROID_SUPPORT) #include "mx6sxsabresdandroid.h" #endif diff --git a/include/configs/mx6sxsabresdandroid.h b/include/configs/mx6sxsabresdandroid.h index 86ab49e..bc2a8fe 100644 --- a/include/configs/mx6sxsabresdandroid.h +++ b/include/configs/mx6sxsabresdandroid.h @@ -1,19 +1,15 @@ /* * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MX6SX_SABRESD_ANDROID_H #define __MX6SX_SABRESD_ANDROID_H +#include "mx_android_common.h" -#define CONFIG_CI_UDC -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED - -#define CONFIG_BCB_SUPPORT -#define CONFIG_CMD_READ /* For NAND we don't support lock/unlock */ #ifndef CONFIG_NAND_BOOT #define CONFIG_FASTBOOT_LOCK @@ -25,40 +21,4 @@ #define CONFIG_SHA256 #endif -#define CONFIG_USB_GADGET -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 -#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 -#define CONFIG_G_DNL_MANUFACTURER "FSL" - -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_FLASH - -#define CONFIG_FSL_FASTBOOT -#define CONFIG_ANDROID_RECOVERY - -#define CONFIG_FASTBOOT_STORAGE_MMC - -#define CONFIG_CMD_BOOTA -#define CONFIG_SUPPORT_RAW_INITRD -#define CONFIG_SERIAL_TAG - -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 - - #endif diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 63306c1..fcac8a0 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -339,8 +339,11 @@ #define CONFIG_MODULE_FUSE #define CONFIG_OF_SYSTEM_SETUP -#if defined(CONFIG_FASTBOOT) +#if defined(CONFIG_ANDROID_SUPPORT) #include "mx6ul_14x14_evk_android.h" #endif +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx6ul_14x14_evkandroidthings.h" +#endif #endif diff --git a/include/configs/mx6ul_14x14_evk_android.h b/include/configs/mx6ul_14x14_evk_android.h index 53c0096..26a7ac5 100644 --- a/include/configs/mx6ul_14x14_evk_android.h +++ b/include/configs/mx6ul_14x14_evk_android.h @@ -7,52 +7,10 @@ #ifndef __MX6UL_EVK_ANDROID_H #define __MX6UL_EVK_ANDROID_H - -#define CONFIG_CI_UDC -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED - -#define CONFIG_USB_GADGET -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 -#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 -#define CONFIG_G_DNL_MANUFACTURER "FSL" - -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_FLASH - -#define CONFIG_FSL_FASTBOOT -#define CONFIG_ANDROID_RECOVERY - -#if defined CONFIG_NAND_BOOT -#define CONFIG_FASTBOOT_STORAGE_NAND -#else -#define CONFIG_FASTBOOT_STORAGE_MMC -#endif +#include "mx_android_common.h" #if defined(CONFIG_FASTBOOT_STORAGE_NAND) #define ANDROID_FASTBOOT_NAND_PARTS "16m@64m(boot) 16m@80m(recovery) 810m@96m(android_root)ubifs" #endif -#define CONFIG_CMD_BOOTA -#define CONFIG_SUPPORT_RAW_INITRD -#define CONFIG_SERIAL_TAG - -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 - #endif diff --git a/include/configs/mx6ul_14x14_evkandroidthings.h b/include/configs/mx6ul_14x14_evkandroidthings.h new file mode 100644 index 0000000..469c634 --- /dev/null +++ b/include/configs/mx6ul_14x14_evkandroidthings.h @@ -0,0 +1,41 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6UL_14x14_EVKANDROIDTHINGS_H +#define __MX6UL_14x14_EVKANDROIDTHINGS_H +#include "mx_android_common.h" +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_SYS_BOOT_NAND +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_FSL_CAAM_KB +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define FASTBOOT_ENCRYPT_LOCK +#define CONFIG_FSL_BOOTCTL +#ifdef CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_PARTITION_UUIDS +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + +#define CONFIG_CMD_FAT + +#endif diff --git a/include/configs/mx6ul_aquila.h b/include/configs/mx6ul_aquila.h new file mode 100644 index 0000000..21888ca --- /dev/null +++ b/include/configs/mx6ul_aquila.h @@ -0,0 +1,368 @@ +/* + * Copyright (C) 2017 Murata Electronics + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Configuration settings for the Murata AQUILA + i.MX6UL-BB board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_AQUILA_CONFIG_H +#define __MX6UL_AQUILA_CONFIG_H + + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" +#include <asm/imx-common/gpio.h> + +/* uncomment for PLUGIN mode support */ +/* #define CONFIG_USE_PLUGIN */ + +/* uncomment for SECURE mode support */ +/* #define CONFIG_SECURE_BOOT */ + +/* uncomment for BEE support, needs to enable CONFIG_CMD_FUSE */ +/* #define CONFIG_CMD_BEE */ + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#define CONFIG_FSL_USDHC +#ifdef CONFIG_FSL_USDHC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#endif + +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_PARTITION_UUIDS +#endif + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 /* need board rework */ +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define PHYS_SDRAM_SIZE SZ_512M + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_SYS_BOOT_NAND) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" imx6ul-som-evk.dtb "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_SYS_BOOT_QSPI +#define CONFIG_FSL_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_NAND +#define CONFIG_SYS_USE_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI1_ARB_BASE_ADDR + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (37 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + + +#define CONFIG_CMD_BMODE + +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP + +#ifdef CONFIG_USB_FASTBOOT_BUF_SIZE +#undef CONFIG_USB_FASTBOOT_BUF_SIZE +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0xc800000 +#endif + +#define PRODUCT_NAME "imx6ul_aquila" +#define VARIANT_NAME "imx6ul_aquila" + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx6ul_aquila_android_things.h" +#endif + +#endif diff --git a/include/configs/mx6ul_aquila_android_things.h b/include/configs/mx6ul_aquila_android_things.h new file mode 100644 index 0000000..c6ce5fc --- /dev/null +++ b/include/configs/mx6ul_aquila_android_things.h @@ -0,0 +1,41 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PICOSOM_IMX6UL_ANDROID_THINGS_H +#define __PICOSOM_IMX6UL_ANDROID_THINGS_H +#include "mx_android_common.h" +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_SYS_BOOT_NAND +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_FSL_CAAM_KB +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE +#ifdef CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + +#endif diff --git a/include/configs/mx6ul_nxpu_iopb.h b/include/configs/mx6ul_nxpu_iopb.h new file mode 100644 index 0000000..46725ab --- /dev/null +++ b/include/configs/mx6ul_nxpu_iopb.h @@ -0,0 +1,368 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL NXPU IOPB board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_NXPU_IOPB_CONFIG_H +#define __MX6UL_NXPU_IOPB_CONFIG_H + + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" +#include <asm/imx-common/gpio.h> + +#if !defined(CONFIG_MX6UL_9X9_LPDDR2) +/* DCDC used on 14x14 EVK, no PMIC */ +#undef CONFIG_LDO_BYPASS_CHECK +#endif + +/* uncomment for PLUGIN mode support */ +/* #define CONFIG_USE_PLUGIN */ + +/* uncomment for SECURE mode support */ +/* #define CONFIG_SECURE_BOOT */ + +/* uncomment for BEE support, needs to enable CONFIG_CMD_FUSE */ +/* #define CONFIG_CMD_BEE */ + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART3_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#define CONFIG_FSL_USDHC +#ifdef CONFIG_FSL_USDHC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#endif + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 0 +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_PHYLIB +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define PHYS_SDRAM_SIZE SZ_512M + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_SYS_BOOT_NAND) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc2\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_SYS_BOOT_QSPI +#define CONFIG_FSL_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_NAND +#define CONFIG_SYS_USE_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI1_ARB_BASE_ADDR + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + + +#define CONFIG_CMD_BMODE + +#ifndef CONFIG_SYS_DCACHE_OFF +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx6ul_nxpu_iopb_android_things.h" +#endif + + +#define PRODUCT_NAME "imx6ul" +#define VARIANT_NAME "imx6ul_iopb" + +#endif diff --git a/include/configs/mx6ul_nxpu_iopb_android_things.h b/include/configs/mx6ul_nxpu_iopb_android_things.h new file mode 100644 index 0000000..95e56d9 --- /dev/null +++ b/include/configs/mx6ul_nxpu_iopb_android_things.h @@ -0,0 +1,40 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6UL_NXPU_IOPB_ANDROID_THINGS_H +#define __MX6UL_NXPU_IOPB_ANDROID_THINGS_H +#include "mx_android_common.h" +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_SYS_BOOT_NAND +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_FSL_CAAM_KB +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#define CONFIG_AVB_FUSE +#ifdef CONFIG_AVB_SUPPORT +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + + +#endif diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 9f06878..1e7e1f1 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -356,8 +356,10 @@ #define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR #endif -#if defined(CONFIG_FASTBOOT) +#if defined(CONFIG_ANDROID_SUPPORT) #include "mx7dsabresdandroid.h" +#elif defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx7dsabresd_androidthings.h" #else #define CONFIG_USBD_HS #define CONFIG_USB_FUNCTION_MASS_STORAGE diff --git a/include/configs/mx7dsabresd_androidthings.h b/include/configs/mx7dsabresd_androidthings.h new file mode 100644 index 0000000..503d80e --- /dev/null +++ b/include/configs/mx7dsabresd_androidthings.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7DSABRESDBRSD_ANDROIDTHINGS_H +#define __MX7DSABRESDBRSD_ANDROIDTHINGS_H +#include "mx_android_common.h" + +#define CONFIG_CMD_FAT + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_SYS_BOOT_NAND +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define FASTBOOT_ENCRYPT_LOCK + +#define CONFIG_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + + +#ifdef CONFIG_SYS_MMC_ENV_DEV +#undef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#endif + +#ifdef CONFIG_SYS_MMC_ENV_PART +#undef CONFIG_SYS_MMC_ENV_PART +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#endif + +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_EXT4 + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +/* infact 7D have no enough bits + * set this size to 0 will disable + * program/read FUSE */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#endif + +#endif + diff --git a/include/configs/mx7dsabresdandroid.h b/include/configs/mx7dsabresdandroid.h index a545f00..0636afe 100644 --- a/include/configs/mx7dsabresdandroid.h +++ b/include/configs/mx7dsabresdandroid.h @@ -7,48 +7,5 @@ #ifndef __MX7D_SABRESD_ANDROID_H #define __MX7D_SABRESD_ANDROID_H - -#define CONFIG_CI_UDC -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED - -#define CONFIG_BCB_SUPPORT -#define CONFIG_CMD_READ - -#define CONFIG_USB_GADGET -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 -#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 -#define CONFIG_G_DNL_MANUFACTURER "FSL" - -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_FLASH - -#define CONFIG_FSL_FASTBOOT -#define CONFIG_ANDROID_RECOVERY -#define CONFIG_FASTBOOT_STORAGE_MMC - -#define CONFIG_CMD_BOOTA -#define CONFIG_SUPPORT_RAW_INITRD -#define CONFIG_SERIAL_TAG - -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - - -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 - - +#include "mx_android_common.h" #endif diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 372d829..5ff06e9 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -248,7 +248,7 @@ #define CONFIG_OF_SYSTEM_SETUP -#if defined(CONFIG_FASTBOOT) +#if defined(CONFIG_ANDROID_SUPPORT) #include "mx7ulp_evk_android.h" #endif diff --git a/include/configs/mx7ulp_evk_android.h b/include/configs/mx7ulp_evk_android.h index 8479642..a45ec1b 100644 --- a/include/configs/mx7ulp_evk_android.h +++ b/include/configs/mx7ulp_evk_android.h @@ -7,49 +7,11 @@ #ifndef __MX7ULP_EVK_ANDROID_H #define __MX7ULP_EVK_ANDROID_H - -#define CONFIG_CI_UDC -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED - -#define CONFIG_USB_GADGET -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 -#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 -#define CONFIG_G_DNL_MANUFACTURER "FSL" +#include "mx_android_common.h" #define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_FLASH - -#define CONFIG_FSL_FASTBOOT -#define CONFIG_ANDROID_RECOVERY -#define CONFIG_FASTBOOT_STORAGE_MMC - -#define CONFIG_CMD_BOOTA -#define CONFIG_SUPPORT_RAW_INITRD -#define CONFIG_SERIAL_TAG - -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - - -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 - #endif diff --git a/include/configs/mx_android_common.h b/include/configs/mx_android_common.h new file mode 100644 index 0000000..808ac0d --- /dev/null +++ b/include/configs/mx_android_common.h @@ -0,0 +1,56 @@ +/* + * Copyright 2017 NXP + */ + +#ifndef __MX_ANDROID_COMMON_H +#define __MX_ANDROID_COMMON_H + +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 +#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 +#define CONFIG_G_DNL_MANUFACTURER "FSL" + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG__NAND_BOOT +#define CONFIG_FASTBOOT_STORAGE_NAND +#elif defined CONFIG_SYS_BOOT_SATA +#define CONFIG_FASTBOOT_STORAGE_SATA +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +#endif /*MX_ANDROID_COMMON_H*/ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 8ad7fa6..24276d8 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -150,7 +150,11 @@ #define CONFIG_ENV_OFFSET (8 * SZ_64K) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_SYS_MMC_ENV_PART 1 #define CONFIG_MMCROOT "/dev/mmcblk0p2" +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx6ul_14x14_evk_android.h" +#include "mx6ul_14x14_evk_brillo.h" +#endif #endif /* __PICO_IMX6UL_CONFIG_H */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h new file mode 100755 index 0000000..83384d2 --- /dev/null +++ b/include/configs/pico-imx7d.h @@ -0,0 +1,401 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D SABRESD board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PICO_IMX7D_CONFIG_H +#define __PICO_IMX7D_CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx7_common.h" +#include <asm/imx-common/gpio.h> + +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define CONFIG_DBG_MONITOR +/* uncomment for PLUGIN mode support */ +/* #define CONFIG_USE_PLUGIN */ + +/* uncomment for SECURE mode support */ +/* #define CONFIG_SECURE_BOOT */ + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#ifdef CONFIG_MXC_UART_BASE +#undef CONFIG_MXC_UART_BASE +#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR +#endif +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_BROADCOM + +/* ENET1 + MDIO2 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_IPS_BASE_ADDR + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + +/* I2C configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#define CONFIG_SYS_I2C_SPEED 100000 + + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 /* Set to QSPI1 A flash at default */ + +#ifdef CONFIG_CMD_BOOTAUX + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_SYS_BOOT_NAND) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=EJ050NA\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc4\0" \ + "bootargs=console=ttymxc4,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "panel=EJ050NA\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc4\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7d-pico_dwarf.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot} 2\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_SYS_BOOT_QSPI +#define CONFIG_SYS_USE_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_NAND +#define CONFIG_SYS_USE_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_SYS_USE_QSPI +#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ +#define CONFIG_QSPI_BASE QSPI1_IPS_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI0_ARB_BASE_ADDR + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (3 << 18) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#define CONFIG_CMD_BMODE + +#ifndef CONFIG_SYS_DCACHE_OFF +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_CFB_CONSOLE +#define CONFIG_CMD_BMP +#define CONFIG_LCD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +/* USB Configs */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX7 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_IMX_THERMAL + +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_SYS_USE_QSPI) +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!" +#endif + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "pico-imx7dandroidthings.h" +#endif + +#define PRODUCT_NAME "imx7d" +#define VARIANT_NAME "imx7d_pico" + +#endif /* __CONFIG_H */ diff --git a/include/configs/pico-imx7dandroidthings.h b/include/configs/pico-imx7dandroidthings.h new file mode 100644 index 0000000..334affa --- /dev/null +++ b/include/configs/pico-imx7dandroidthings.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PICO_IMX7DANDROIDTHINGS_H +#define __PICO_IMX7DANDROIDTHINGS_H +#include "mx_android_common.h" + + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_SYS_BOOT_NAND +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define FASTBOOT_ENCRYPT_LOCK + +#define CONFIG_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MMC_ENV_DEV +#undef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#endif + +#ifdef CONFIG_SYS_MMC_ENV_PART +#undef CONFIG_SYS_MMC_ENV_PART +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#endif + + +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif +/* fuse bank size in word */ +/* infact 7D have no enough bits + * set this size to 0 will disable + * program/read FUSE */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#endif + +#endif + diff --git a/include/configs/picosom-imx6ul.h b/include/configs/picosom-imx6ul.h new file mode 100644 index 0000000..91c5684 --- /dev/null +++ b/include/configs/picosom-imx6ul.h @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2015 Technexion Ltd. + * + * Configuration settings for the Technexion PicoSOM i.mx6UL board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __PICOSOM_IMX6UL_CONFIG_H +#define __PICOSOM_IMX6UL_CONFIG_H + + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" +#include <asm/imx-common/gpio.h> + +/* uncomment for SECURE mode support */ +/* #define CONFIG_SECURE_BOOT */ + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE MX6UL_UART6_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 /* need board rework */ +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#endif + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + + +#define PHYS_SDRAM_SIZE SZ_512M + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + + +/* #define CONFIG_VIDEO */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_SYS_BOOT_NAND) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc5\0" \ + "bootargs=console=ttymxc5,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc5\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_NAND +#define CONFIG_SYS_USE_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_QSPI_BASE QSPI0_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI0_AMBA_BASE + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (384 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_CMD_BMODE + +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define PRODUCT_NAME "imx6ul_pico" +#define VARIANT_NAME "imx6ul_pico" + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "picosom-imx6ul_android_things.h" +#endif + +#endif diff --git a/include/configs/picosom-imx6ul_android_things.h b/include/configs/picosom-imx6ul_android_things.h new file mode 100644 index 0000000..b081d7c --- /dev/null +++ b/include/configs/picosom-imx6ul_android_things.h @@ -0,0 +1,42 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PICOSOM_IMX6UL_ANDROID_THINGS_H +#define __PICOSOM_IMX6UL_ANDROID_THINGS_H +#include "mx_android_common.h" +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_SYS_BOOT_NAND +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_FSL_CAAM_KB +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE +#ifdef CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + + +#endif diff --git a/include/fsl_fastboot.h b/include/fsl_fastboot.h index 7d66db2..9d04da9 100644 --- a/include/fsl_fastboot.h +++ b/include/fsl_fastboot.h @@ -30,6 +30,9 @@ using the setenv and saveenv commands */ #define FASTBOOT_PTENTRY_FLAGS_WRITE_ENV 0x00000400 +/* Uneraseable partition */ +#define FASTBOOT_PTENTRY_FLAGS_UNERASEABLE 0x00000800 + #define FASTBOOT_MMC_BOOT_PARTITION_ID 1 #define FASTBOOT_MMC_USER_PARTITION_ID 0 #define FASTBOOT_MMC_NONE_PARTITION_ID -1 @@ -55,6 +58,8 @@ #define FASTBOOT_PARTITION_BOOT "boot" #define FASTBOOT_PARTITION_RECOVERY "recovery" #define FASTBOOT_PARTITION_SYSTEM "system" +#define FASTBOOT_PARTITION_CACHE "cache" +#define FASTBOOT_PARTITION_DEVICE "device" #define FASTBOOT_PARTITION_BOOTLOADER "bootloader" #define FASTBOOT_PARTITION_DATA "userdata" #define FASTBOOT_PARTITION_GPT "gpt" @@ -158,6 +163,8 @@ struct fastboot_ptentry { unsigned int partition_id; /* partition number in block device */ unsigned int partition_index; + /* partition file system type in string */ + char fstype[16]; /* filesystem UUID as string, if exists */ #ifdef CONFIG_PARTITION_UUIDS char uuid[37]; diff --git a/lib/avb/fsl/utils.c b/lib/avb/fsl/utils.c index ec50c70..458ccea 100644 --- a/lib/avb/fsl/utils.c +++ b/lib/avb/fsl/utils.c @@ -1,4 +1,9 @@ - +/* ++ * Copyright (C) 2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ #include <common.h> #include <stdlib.h> @@ -14,23 +19,23 @@ int get_margin_pos(uint64_t part_start, uint64_t part_end, unsigned long blksz, return -1; if (offset < 0) { - margin->blk_start = (offset + 1) / blksz + part_end; - margin->start = (off = offset % blksz) == 0 ? 0 : blksz + off; // offset == -1 means the last byte?, or start need -1 + margin->blk_start = (offset + 1) / (uint64_t)blksz + part_end; + margin->start = (off = offset % (uint64_t)blksz) == 0 ? 0 : blksz + off; // offset == -1 means the last byte?, or start need -1 if (offset + num_bytes - 1 >= 0) { if (!allow_partial) return -1; margin->blk_end = part_end; margin->end = blksz - 1; } else { - margin->blk_end = (num_bytes + offset) / blksz + part_end; // which blk the last byte is in - margin->end = (off = (num_bytes + offset - 1) % blksz) == 0 ? + margin->blk_end = (num_bytes + offset) / (uint64_t)blksz + part_end; // which blk the last byte is in + margin->end = (off = (num_bytes + offset - 1) % (uint64_t)blksz) == 0 ? 0 : blksz + off; // last byte } } else { - margin->blk_start = offset / blksz + part_start; - margin->start = offset % blksz; - margin->blk_end = (offset + num_bytes - 1) / blksz + part_start ; - margin->end = (offset + num_bytes - 1) % blksz; + margin->blk_start = offset / (uint64_t)blksz + part_start; + margin->start = offset % (uint64_t)blksz; + margin->blk_end = (offset + num_bytes - 1) / (uint64_t)blksz + part_start ; + margin->end = (offset + num_bytes - 1) % (uint64_t)blksz; if (margin->blk_end > part_end) { if (!allow_partial) return -1; diff --git a/lib/avb/fsl/utils.h b/lib/avb/fsl/utils.h index 6fe72f5..8100e77 100644 --- a/lib/avb/fsl/utils.h +++ b/lib/avb/fsl/utils.h @@ -1,3 +1,9 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ #ifndef __UTILS_H__ #define __UTILS_H__ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 9889e9a..8b2be7f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -95,6 +95,9 @@ CONFIG_AMCC_DEF_ENV_ROOTPATH CONFIG_AMCORE CONFIG_ANDES_PCU CONFIG_ANDES_PCU_BASE +CONFIG_ANDROID_AB_SUPPORT +CONFIG_ANDROID_SUPPORT +CONFIG_ANDROID_THINGS_SUPPORT CONFIG_AP325RXA CONFIG_APBH_DMA CONFIG_APBH_DMA_BURST @@ -218,6 +221,11 @@ CONFIG_AUTOCALIB CONFIG_AUTONEG_TIMEOUT CONFIG_AUTO_COMPLETE CONFIG_AUTO_ZRELADDR +CONFIG_AVB_FUSE +CONFIG_AVB_FUSE_BANK_END +CONFIG_AVB_FUSE_BANK_SIZEW +CONFIG_AVB_FUSE_BANK_START +CONFIG_AVB_SUPPORT CONFIG_BACKSIDE_L2_CACHE CONFIG_BAMBOO CONFIG_BAMBOO_NAND @@ -923,6 +931,7 @@ CONFIG_EMIF4 CONFIG_EMMC_BOOT CONFIG_EMU CONFIG_ENABLE_36BIT_PHYS +CONFIG_ENABLE_LOCKSTATUS_SUPPORT CONFIG_ENABLE_MMU CONFIG_ENABLE_MUST_CHECK CONFIG_ENABLE_WARN_DEPRECATED @@ -1138,6 +1147,7 @@ CONFIG_FPGA_SPARTAN3 CONFIG_FPGA_STRATIX_V CONFIG_FPGA_ZYNQPL CONFIG_FSLDMAFEC +CONFIG_FSL_BOOTCTL CONFIG_FSL_CAAM_KB CONFIG_FSL_CADMUS CONFIG_FSL_CORENET @@ -2224,6 +2234,7 @@ CONFIG_PALMAS_SMPS7_FPWM CONFIG_PALMAS_USB_SS_PWR CONFIG_PANIC_HANG CONFIG_PARAVIRT +CONFIG_PARTITION_UUIDS CONFIG_PATA_BFIN CONFIG_PATI CONFIG_PB1000 @@ -3069,6 +3080,7 @@ CONFIG_SYSFLAGS_ADDR CONFIG_SYSFS CONFIG_SYSMGR_ISWGRP_HANDOFF CONFIG_SYSTEMACE +CONFIG_SYSTEM_RAMDISK_SUPPORT CONFIG_SYS_33MHZ CONFIG_SYS_405_UART_ERRATA_59 CONFIG_SYS_460GT_SRIO_ERRATA_1 |