Merge branch 'master' of git://git.denx.de/u-boot-uniphier

31 files changed, 469 insertions, 285 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a311215..5de3bfc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -868,6 +868,8 @@ config ARCH_UNIPHIER
 	select PINCTRL
 	select SPL
 	select SPL_DM
+	select SPL_LIBCOMMON_SUPPORT
+	select SPL_LIBGENERIC_SUPPORT
 	select SPL_OF_CONTROL
 	select SPL_PINCTRL
 	select SUPPORT_SPL
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index b0b2b57..e441033 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -31,7 +31,7 @@
 			interrupts = <0 33 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 0>;
 		};
 
 		serial1: serial@54006900 {
@@ -41,7 +41,7 @@
 			interrupts = <0 35 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 1>;
 		};
 
 		serial2: serial@54006a00 {
@@ -51,7 +51,7 @@
 			interrupts = <0 37 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 2>;
 		};
 
 		serial3: serial@54006b00 {
@@ -61,7 +61,7 @@
 			interrupts = <0 177 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 3>;
 		};
 
 		system_bus: system-bus@58c00000 {
@@ -79,16 +79,33 @@
 			reg = <0x59801000 0x400>;
 		};
 
-		mio: mioctrl@59810000 {
-			/* specify compatible in each SoC DTSI */
+		mioctrl@59810000 {
+			compatible = "socionext,uniphier-mioctrl",
+				     "simple-mfd", "syscon";
 			reg = <0x59810000 0x800>;
-			#clock-cells = <1>;
+			u-boot,dm-pre-reloc;
+
+			mio_clk: clock {
+				#clock-cells = <1>;
+			};
+
+			mio_rst: reset {
+				#reset-cells = <1>;
+			};
 		};
 
-		peri: perictrl@59820000 {
-			/* specify compatible in each SoC DTSI */
+		perictrl@59820000 {
+			compatible = "socionext,uniphier-perictrl",
+				     "simple-mfd", "syscon";
 			reg = <0x59820000 0x200>;
-			#clock-cells = <1>;
+
+			peri_clk: clock {
+				#clock-cells = <1>;
+			};
+
+			peri_rst: reset {
+				#reset-cells = <1>;
+			};
 		};
 
 		timer@60000200 {
@@ -114,7 +131,8 @@
 		};
 
 		soc-glue@5f800000 {
-			compatible = "simple-mfd", "syscon";
+			compatible = "socionext,uniphier-soc-glue",
+				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
 
@@ -124,12 +142,18 @@
 			};
 		};
 
-		sysctrl: sysctrl@61840000 {
-			/* specify compatible in each SoC DTSI */
+		sysctrl@61840000 {
+			compatible = "socionext,uniphier-sysctrl",
+				     "simple-mfd", "syscon";
 			reg = <0x61840000 0x4000>;
-			#clock-cells = <1>;
-			clock-names = "ref";
-			clocks = <&refclk>;
+
+			sys_clk: clock {
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				#reset-cells = <1>;
+			};
 		};
 
 		nand: nand@68000000 {
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index ffe04f5..0bdbbdd 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -54,12 +54,6 @@
 			clock-frequency = <25000000>;
 		};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <58820000>;
-		};
-
 		i2c_clk: i2c_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -69,10 +63,10 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xf01>,
-			     <1 14 0xf01>,
-			     <1 11 0xf01>,
-			     <1 10 0xf01>;
+		interrupts = <1 13 4>,
+			     <1 14 4>,
+			     <1 11 4>,
+			     <1 10 4>;
 	};
 
 	soc {
@@ -89,7 +83,7 @@
 			interrupts = <0 33 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 0>;
 			clock-frequency = <58820000>;
 		};
 
@@ -100,7 +94,7 @@
 			interrupts = <0 35 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 1>;
 			clock-frequency = <58820000>;
 		};
 
@@ -111,7 +105,7 @@
 			interrupts = <0 37 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 2>;
 			clock-frequency = <58820000>;
 		};
 
@@ -122,7 +116,7 @@
 			interrupts = <0 177 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 3>;
 			clock-frequency = <58820000>;
 		};
 
@@ -213,6 +207,22 @@
 			reg = <0x59801000 0x400>;
 		};
 
+		perictrl@59820000 {
+			compatible = "socionext,uniphier-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
+
+			peri_clk: clock {
+				compatible = "socionext,uniphier-ld11-peri-clock";
+				#clock-cells = <1>;
+			};
+
+			peri_rst: reset {
+				compatible = "socionext,uniphier-ld11-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -220,7 +230,7 @@
 			interrupts = <0 243 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb0>;
-			clocks = <&mio 3>, <&mio 6>;
+			clocks = <&mio_clk 3>, <&mio_clk 6>;
 		};
 
 		usb1: usb@5a810100 {
@@ -230,7 +240,7 @@
 			interrupts = <0 244 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb1>;
-			clocks = <&mio 4>, <&mio 6>;
+			clocks = <&mio_clk 4>, <&mio_clk 6>;
 		};
 
 		usb2: usb@5a820100 {
@@ -240,17 +250,29 @@
 			interrupts = <0 245 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb2>;
-			clocks = <&mio 5>, <&mio 6>;
+			clocks = <&mio_clk 5>, <&mio_clk 6>;
 		};
 
-		mio: mioctrl@5b3e0000 {
-			compatible = "socionext,ph1-ld11-mioctrl";
+		mioctrl@5b3e0000 {
+			compatible = "socionext,uniphier-mioctrl",
+				     "simple-mfd", "syscon";
 			reg = <0x5b3e0000 0x800>;
-			#clock-cells = <1>;
+
+			mio_clk: clock {
+				compatible = "socionext,uniphier-ld11-mio-clock";
+				#clock-cells = <1>;
+			};
+
+			mio_rst: reset {
+				compatible = "socionext,uniphier-ld11-mio-reset";
+				#reset-cells = <1>;
+				resets = <&sys_rst 7>;
+			};
 		};
 
 		soc-glue@5f800000 {
-			compatible = "simple-mfd", "syscon";
+			compatible = "socionext,uniphier-soc-glue",
+				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
 
@@ -273,6 +295,22 @@
 			#interrupt-cells = <3>;
 			interrupts = <1 9 4>;
 		};
+
+		sysctrl@61840000 {
+			compatible = "socionext,uniphier-ld11-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x4000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-ld11-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-ld11-reset";
+				#reset-cells = <1>;
+			};
+		};
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi
index 7497539..7f97f88 100644
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi
@@ -78,12 +78,6 @@
 			clock-frequency = <25000000>;
 		};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <58820000>;
-		};
-
 		i2c_clk: i2c_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -93,10 +87,10 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xf01>,
-			     <1 14 0xf01>,
-			     <1 11 0xf01>,
-			     <1 10 0xf01>;
+		interrupts = <1 13 4>,
+			     <1 14 4>,
+			     <1 11 4>,
+			     <1 10 4>;
 	};
 
 	soc {
@@ -113,7 +107,7 @@
 			interrupts = <0 33 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 0>;
 			clock-frequency = <58820000>;
 		};
 
@@ -124,7 +118,7 @@
 			interrupts = <0 35 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 1>;
 			clock-frequency = <58820000>;
 		};
 
@@ -135,7 +129,7 @@
 			interrupts = <0 37 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 2>;
 			clock-frequency = <58820000>;
 		};
 
@@ -146,7 +140,7 @@
 			interrupts = <0 177 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
-			clocks = <&uart_clk>;
+			clocks = <&peri_clk 3>;
 			clock-frequency = <58820000>;
 		};
 
@@ -237,10 +231,36 @@
 			reg = <0x59801000 0x400>;
 		};
 
-		mio: mioctrl@59810000 {
-			compatible = "socionext,ph1-ld20-mioctrl";
+		mioctrl@59810000 {
+			compatible = "socionext,uniphier-mioctrl",
+				     "simple-mfd", "syscon";
 			reg = <0x59810000 0x800>;
-			#clock-cells = <1>;
+
+			mio_clk: clock {
+				compatible = "socionext,uniphier-ld20-mio-clock";
+				#clock-cells = <1>;
+			};
+
+			mio_rst: reset {
+				compatible = "socionext,uniphier-ld20-mio-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		perictrl@59820000 {
+			compatible = "socionext,uniphier-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
+
+			peri_clk: clock {
+				compatible = "socionext,uniphier-ld20-peri-clock";
+				#clock-cells = <1>;
+			};
+
+			peri_rst: reset {
+				compatible = "socionext,uniphier-ld20-peri-reset";
+				#reset-cells = <1>;
+			};
 		};
 
 		sd: sdhc@5a400000 {
@@ -250,12 +270,13 @@
 			interrupts = <0 76 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_sd>;
-			clocks = <&mio 0>;
+			clocks = <&mio_clk 0>;
 			bus-width = <4>;
 		};
 
 		soc-glue@5f800000 {
-			compatible = "simple-mfd", "syscon";
+			compatible = "socionext,uniphier-soc-glue",
+				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
 
@@ -278,6 +299,22 @@
 			#interrupt-cells = <3>;
 			interrupts = <1 9 4>;
 		};
+
+		sysctrl@61840000 {
+			compatible = "socionext,uniphier-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x4000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-ld20-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-ld20-reset";
+				#reset-cells = <1>;
+			};
+		};
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 07f315a..e4884b9 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -30,12 +30,6 @@
 			clock-frequency = <50000000>;
 		};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <36864000>;
-		};
-
 		iobus_clk: iobus_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -228,7 +222,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_sd>;
 		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio 0>;
+		clocks = <&mio_clk 0>;
 		bus-width = <4>;
 	};
 
@@ -240,7 +234,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_emmc>;
 		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio 1>;
+		clocks = <&mio_clk 1>;
 		bus-width = <8>;
 		non-removable;
 	};
@@ -252,7 +246,7 @@
 		interrupts = <0 80 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb0>;
-		clocks = <&mio 3>, <&mio 6>;
+		clocks = <&mio_clk 3>, <&mio_clk 6>;
 	};
 
 	usb1: usb@5a810100 {
@@ -262,7 +256,7 @@
 		interrupts = <0 81 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb1>;
-		clocks = <&mio 4>, <&mio 6>;
+		clocks = <&mio_clk 4>, <&mio_clk 6>;
 	};
 
 	usb2: usb@5a820100 {
@@ -272,7 +266,7 @@
 		interrupts = <0 82 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio 5>, <&mio 6>;
+		clocks = <&mio_clk 5>, <&mio_clk 6>;
 	};
 
 	aidet@61830000 {
@@ -302,22 +296,30 @@
 	clock-frequency = <36864000>;
 };
 
-&mio {
-	compatible = "socionext,ph1-ld4-mioctrl";
-	clock-names = "stdmac", "ehci";
-	clocks = <&sysctrl 10>, <&sysctrl 18>;
+&mio_clk {
+	compatible = "socionext,uniphier-ld4-mio-clock";
+};
+
+&mio_rst {
+	compatible = "socionext,uniphier-ld4-mio-reset";
+};
+
+&peri_clk {
+	compatible = "socionext,uniphier-ld4-peri-clock";
 };
 
-&peri {
-	compatible = "socionext,ph1-ld4-perictrl";
-	clock-names = "uart", "i2c";
-	clocks = <&sysctrl 3>, <&sysctrl 4>;
+&peri_rst {
+	compatible = "socionext,uniphier-ld4-peri-reset";
 };
 
 &pinctrl {
 	compatible = "socionext,uniphier-ld4-pinctrl";
 };
 
-&sysctrl {
-	compatible = "socionext,ph1-ld4-sysctrl";
+&sys_clk {
+	compatible = "socionext,uniphier-ld4-clock";
+};
+
+&sys_rst {
+	compatible = "socionext,uniphier-ld4-reset";
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
index 965fe08..3f178d2 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
@@ -89,7 +89,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&mio {
+&mio_clk {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index e0b28b8..192ce84 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -351,7 +351,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_sd>;
 		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio 0>;
+		clocks = <&mio_clk 0>;
 		bus-width = <4>;
 	};
 
@@ -363,7 +363,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_emmc>;
 		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio 1>;
+		clocks = <&mio_clk 1>;
 		bus-width = <8>;
 		non-removable;
 	};
@@ -376,7 +376,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_sd1>;
 		pinctrl-1 = <&pinctrl_sd1_1v8>;
-		clocks = <&mio 2>;
+		clocks = <&mio_clk 2>;
 		bus-width = <4>;
 	};
 
@@ -387,7 +387,7 @@
 		interrupts = <0 80 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio 3>, <&mio 6>;
+		clocks = <&mio_clk 3>, <&mio_clk 6>;
 	};
 
 	usb3: usb@5a810100 {
@@ -397,7 +397,7 @@
 		interrupts = <0 81 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb3>;
-		clocks = <&mio 4>, <&mio 6>;
+		clocks = <&mio_clk 4>, <&mio_clk 6>;
 	};
 
 	aidet@5fc20000 {
@@ -444,22 +444,30 @@
 	clock-frequency = <73728000>;
 };
 
-&mio {
-	compatible = "socionext,ph1-pro4-mioctrl";
-	clock-names = "stdmac", "ehci";
-	clocks = <&sysctrl 10>, <&sysctrl 18>;
+&mio_clk {
+	compatible = "socionext,uniphier-pro4-mio-clock";
 };
 
-&peri {
-	compatible = "socionext,ph1-pro4-perictrl";
-	clock-names = "uart", "fi2c";
-	clocks = <&sysctrl 3>, <&sysctrl 4>;
+&mio_rst {
+	compatible = "socionext,uniphier-pro4-mio-reset";
+};
+
+&peri_clk {
+	compatible = "socionext,uniphier-pro4-peri-clock";
+};
+
+&peri_rst {
+	compatible = "socionext,uniphier-pro4-peri-reset";
 };
 
 &pinctrl {
 	compatible = "socionext,uniphier-pro4-pinctrl";
 };
 
-&sysctrl {
-	compatible = "socionext,ph1-pro4-sysctrl";
+&sys_clk {
+	compatible = "socionext,uniphier-pro4-clock";
+};
+
+&sys_rst {
+	compatible = "socionext,uniphier-pro4-reset";
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 05f961f..22a70b1 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -38,12 +38,6 @@
 			clock-frequency = <50000000>;
 		};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <73728000>;
-		};
-
 		i2c_clk: i2c_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -367,7 +361,7 @@
 		interrupts = <0 78 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_emmc>;
-		clocks = <&mio 1>;
+		clocks = <&mio_clk 1>;
 		bus-width = <8>;
 		non-removable;
 	};
@@ -380,7 +374,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_sd>;
 		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio 0>;
+		clocks = <&mio_clk 0>;
 		bus-width = <4>;
 	};
 
@@ -423,22 +417,30 @@
 	clock-frequency = <73728000>;
 };
 
-&mio {
-	compatible = "socionext,ph1-pro5-mioctrl";
-	clock-names = "stdmac";
-	clocks = <&sysctrl 10>;
+&mio_clk {
+	compatible = "socionext,uniphier-pro5-mio-clock";
+};
+
+&mio_rst {
+	compatible = "socionext,uniphier-pro5-mio-reset";
+};
+
+&peri_clk {
+	compatible = "socionext,uniphier-pro5-peri-clock";
 };
 
-&peri {
-	compatible = "socionext,ph1-pro5-perictrl";
-	clock-names = "uart", "fi2c";
-	clocks = <&sysctrl 3>, <&sysctrl 4>;
+&peri_rst {
+	compatible = "socionext,uniphier-pro5-peri-reset";
 };
 
 &pinctrl {
 	compatible = "socionext,uniphier-pro5-pinctrl";
 };
 
-&sysctrl {
-	compatible = "socionext,ph1-pro5-sysctrl";
+&sys_clk {
+	compatible = "socionext,uniphier-pro5-clock";
+};
+
+&sys_rst {
+	compatible = "socionext,uniphier-pro5-reset";
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index f3e76b3..116e571 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -86,10 +86,6 @@
        u-boot,dm-pre-reloc;
 };
 
-&mio {
-       u-boot,dm-pre-reloc;
-};
-
 &emmc {
        u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index d8c44b7..a554b08 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -42,12 +42,6 @@
 			clock-frequency = <50000000>;
 		};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <36864000>;
-		};
-
 		iobus_clk: iobus_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -92,7 +86,6 @@
 			interrupts = <0 33 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
-			clocks = <&uart_clk>;
 			clock-frequency = <36864000>;
 		};
 
@@ -103,7 +96,6 @@
 			interrupts = <0 35 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
-			clocks = <&uart_clk>;
 			clock-frequency = <36864000>;
 		};
 
@@ -114,7 +106,6 @@
 			interrupts = <0 37 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
-			clocks = <&uart_clk>;
 			clock-frequency = <36864000>;
 		};
 
@@ -299,12 +290,22 @@
 			reg = <0x59801000 0x400>;
 		};
 
-		mio: mioctrl@59810000 {
-			compatible = "socionext,ph1-sld3-mioctrl";
+		mioctrl@59810000 {
+			compatible = "socionext,uniphier-mioctrl",
+				     "simple-mfd", "syscon";
 			reg = <0x59810000 0x800>;
-			#clock-cells = <1>;
-			clock-names = "stdmac", "ehci";
-			clocks = <&sysctrl 10>, <&sysctrl 18>;
+			u-boot,dm-pre-reloc;
+
+			mio_clk: clock {
+				compatible = "socionext,uniphier-sld3-mio-clock";
+				#clock-cells = <1>;
+				u-boot,dm-pre-reloc;
+			};
+
+			mio_rst: reset {
+				compatible = "socionext,uniphier-sld3-mio-reset";
+				#reset-cells = <1>;
+			};
 		};
 
 		emmc: sdhc@5a400000 {
@@ -315,7 +316,7 @@
 			pinctrl-names = "default", "1.8v";
 			pinctrl-0 = <&pinctrl_emmc>;
 			pinctrl-1 = <&pinctrl_emmc_1v8>;
-			clocks = <&mio 1>;
+			clocks = <&mio_clk 1>;
 			bus-width = <8>;
 			non-removable;
 		};
@@ -328,7 +329,7 @@
 			pinctrl-names = "default", "1.8v";
 			pinctrl-0 = <&pinctrl_sd>;
 			pinctrl-1 = <&pinctrl_sd_1v8>;
-			clocks = <&mio 0>;
+			clocks = <&mio_clk 0>;
 			bus-width = <4>;
 		};
 
@@ -339,7 +340,7 @@
 			interrupts = <0 80 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb0>;
-			clocks = <&mio 3>, <&mio 6>;
+			clocks = <&mio_clk 3>, <&mio_clk 6>;
 		};
 
 		usb1: usb@5a810100 {
@@ -349,7 +350,7 @@
 			interrupts = <0 81 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb1>;
-			clocks = <&mio 4>, <&mio 6>;
+			clocks = <&mio_clk 4>, <&mio_clk 6>;
 		};
 
 		usb2: usb@5a820100 {
@@ -359,7 +360,7 @@
 			interrupts = <0 82 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb2>;
-			clocks = <&mio 5>, <&mio 6>;
+			clocks = <&mio_clk 5>, <&mio_clk 6>;
 		};
 
 		usb3: usb@5a830100 {
@@ -369,7 +370,7 @@
 			interrupts = <0 83 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb3>;
-			clocks = <&mio 7>, <&mio 6>;
+			clocks = <&mio_clk 7>, <&mio_clk 6>;
 		};
 
 		soc-glue@5f800000 {
@@ -388,12 +389,20 @@
 			reg = <0xf1830000 0x200>;
 		};
 
-		sysctrl: sysctrl@f1840000 {
-			compatible = "socionext,ph1-sld3-sysctrl";
+		sysctrl@f1840000 {
+			compatible = "socionext,uniphier-sysctrl",
+				     "simple-mfd", "syscon";
 			reg = <0xf1840000 0x4000>;
-			#clock-cells = <1>;
-			clock-names = "ref";
-			clocks = <&refclk>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-sld3-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-sld3-reset";
+				#reset-cells = <1>;
+			};
 		};
 
 		nand: nand@f8000000 {
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index e0376a1..1ecce50 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -30,12 +30,6 @@
 			clock-frequency = <50000000>;
 		};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <80000000>;
-		};
-
 		iobus_clk: iobus_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -228,7 +222,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_sd>;
 		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio 0>;
+		clocks = <&mio_clk 0>;
 		bus-width = <4>;
 	};
 
@@ -240,7 +234,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_emmc>;
 		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio 1>;
+		clocks = <&mio_clk 1>;
 		bus-width = <8>;
 		non-removable;
 	};
@@ -252,7 +246,7 @@
 		interrupts = <0 80 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb0>;
-		clocks = <&mio 3>, <&mio 6>;
+		clocks = <&mio_clk 3>, <&mio_clk 6>;
 	};
 
 	usb1: usb@5a810100 {
@@ -262,7 +256,7 @@
 		interrupts = <0 81 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb1>;
-		clocks = <&mio 4>, <&mio 6>;
+		clocks = <&mio_clk 4>, <&mio_clk 6>;
 	};
 
 	usb2: usb@5a820100 {
@@ -272,7 +266,7 @@
 		interrupts = <0 82 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio 5>, <&mio 6>;
+		clocks = <&mio_clk 5>, <&mio_clk 6>;
 	};
 
 	aidet@61830000 {
@@ -302,22 +296,30 @@
 	clock-frequency = <80000000>;
 };
 
-&mio {
-	compatible = "socionext,ph1-sld8-mioctrl";
-	clock-names = "stdmac", "ehci";
-	clocks = <&sysctrl 10>, <&sysctrl 18>;
+&mio_clk {
+	compatible = "socionext,uniphier-sld8-mio-clock";
+};
+
+&mio_rst {
+	compatible = "socionext,uniphier-sld8-mio-reset";
+};
+
+&peri_clk {
+	compatible = "socionext,uniphier-sld8-peri-clock";
 };
 
-&peri {
-	compatible = "socionext,ph1-sld8-perictrl";
-	clock-names = "uart", "i2c";
-	clocks = <&sysctrl 3>, <&sysctrl 4>;
+&peri_rst {
+	compatible = "socionext,uniphier-sld8-peri-reset";
 };
 
 &pinctrl {
 	compatible = "socionext,uniphier-sld8-pinctrl";
 };
 
-&sysctrl {
-	compatible = "socionext,ph1-sld8-sysctrl";
+&sys_clk {
+	compatible = "socionext,uniphier-sld8-clock";
+};
+
+&sys_rst {
+	compatible = "socionext,uniphier-sld8-reset";
 };
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
index 1175703..7233dc6 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -69,7 +69,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&mio {
+&mio_clk {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
index 928a092..30ea270 100644
--- a/arch/arm/dts/uniphier-proxstream2-vodka.dts
+++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts
@@ -54,7 +54,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&mio {
+&mio_clk {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index 23a6bfa..609cbaa 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -52,12 +52,6 @@
 			clock-frequency = <50000000>;
 		};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <88900000>;
-		};
-
 		i2c_clk: i2c_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -366,7 +360,7 @@
 		interrupts = <0 78 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_emmc>;
-		clocks = <&mio 1>;
+		clocks = <&mio_clk 1>;
 		bus-width = <8>;
 		non-removable;
 	};
@@ -379,7 +373,7 @@
 		pinctrl-names = "default", "1.8v";
 		pinctrl-0 = <&pinctrl_sd>;
 		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio 0>;
+		clocks = <&mio_clk 0>;
 		bus-width = <4>;
 	};
 
@@ -427,22 +421,30 @@
 	clock-frequency = <88900000>;
 };
 
-&mio {
-	compatible = "socionext,proxstream2-mioctrl";
-	clock-names = "stdmac";
-	clocks = <&sysctrl 10>;
+&mio_clk {
+	compatible = "socionext,uniphier-pxs2-mio-clock";
+};
+
+&mio_rst {
+	compatible = "socionext,uniphier-pxs2-mio-reset";
+};
+
+&peri_clk {
+	compatible = "socionext,uniphier-pxs2-peri-clock";
 };
 
-&peri {
-	compatible = "socionext,proxstream2-perictrl";
-	clock-names = "uart", "fi2c";
-	clocks = <&sysctrl 3>, <&sysctrl 4>;
+&peri_rst {
+	compatible = "socionext,uniphier-pxs2-peri-reset";
 };
 
 &pinctrl {
 	compatible = "socionext,uniphier-pxs2-pinctrl";
 };
 
-&sysctrl {
-	compatible = "socionext,proxstream2-sysctrl";
+&sys_clk {
+	compatible = "socionext,uniphier-pxs2-clock";
+};
+
+&sys_rst {
+	compatible = "socionext,uniphier-pxs2-reset";
 };
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 2e824bb..7bee6c7 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -1,20 +1,5 @@
 if ARCH_UNIPHIER
 
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y if !ARCH_UNIPHIER_64BIT
-
-config SPL_NAND_SUPPORT
-	default y if !ARM64
-
-config SPL_SERIAL_SUPPORT
-	default y
-
 config SYS_CONFIG_NAME
 	default "uniphier"
 
diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
index b57a33f..b9be52f 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -128,6 +128,7 @@ int board_init(void)
 		sg_set_pinsel(153, 14, 8, 4);	/* XIRQ4    -> XIRQ4 */
 		sg_set_iectrl(153);
 		led_puts("U1");
+		uniphier_ld11_pll_init();
 		uniphier_ld11_clk_init();
 		break;
 #endif
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index c8d59ea..95f433e 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= early-clk-ld4.o dpll-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= early-clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-clk-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-clk-ld11.o dpll-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-clk-ld20.o dpll-ld20.o
 
 else
@@ -23,9 +23,10 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o pll-ld4.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o pll-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o pll-ld20.o
 
 endif
 
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= pll-base-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pll-base-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld11.c b/arch/arm/mach-uniphier/clk/dpll-ld11.c
new file mode 100644
index 0000000..7f0677c
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-ld11.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd)
+{
+	uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
new file mode 100644
index 0000000..8a4a748
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+void uniphier_ld11_pll_init(void)
+{
+	uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);	/* 2000MHz -> 1960MHz */
+	/* do nothing for SPLL */
+	uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2);	/* 1500MHz -> 1600MHz */
+	uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+	mdelay(1);
+
+	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+
+	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+	writel(0, SC_CA53_GEARSET);	/* Gear0: CPLL/2 */
+	writel(SC_CA_GEARUPD, SC_CA53_GEARUPD);
+}
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 5c7cd6b..4e3bee1 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -87,6 +87,7 @@ int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd);
 
 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
@@ -105,6 +106,7 @@ int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
 void uniphier_sld3_pll_init(void);
 void uniphier_ld4_pll_init(void);
 void uniphier_pro4_pll_init(void);
+void uniphier_ld11_pll_init(void);
 int uniphier_ld20_pll_init(const struct uniphier_board_data *bd);
 
 void uniphier_ld4_clk_init(void);
diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c
index 758df8d..e324c94 100644
--- a/arch/arm/mach-uniphier/init/init-ld11.c
+++ b/arch/arm/mach-uniphier/init/init-ld11.c
@@ -31,12 +31,14 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd)
 
 	led_puts("L2");
 
-	led_puts("L3");
-
 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 	preloader_console_init();
 #endif
 
+	led_puts("L3");
+
+	uniphier_ld11_dpll_init(bd);
+
 	led_puts("L4");
 
 	{
diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index 1e52bb1..780fdd1 100644
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -13,12 +13,14 @@
 #define SC_BASE_ADDR		0x61840000
 
 /* PLL type: SSC */
-#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* LD20: CPU/ARM */
-#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* LD20: misc */
+#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* LD11/20: CPU/ARM */
+#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* LD11/20: misc */
 #define SC_SPLL2CTRL	(SC_BASE_ADDR | 0x1420)	/* LD20: IPP */
-#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* LD20: Video codec */
+#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* LD11/20: Video codec */
+#define SC_VSPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* LD11 */
 #define SC_VPPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* LD20: VPE etc. */
 #define SC_GPPLLCTRL	(SC_BASE_ADDR | 0x1450)	/* LD20: GPU/Mali */
+#define SC_DPLLCTRL	(SC_BASE_ADDR | 0x1460)	/* LD11: DDR memory */
 #define SC_DPLL0CTRL	(SC_BASE_ADDR | 0x1460)	/* LD20: DDR memory 0 */
 #define SC_DPLL1CTRL	(SC_BASE_ADDR | 0x1470)	/* LD20: DDR memory 1 */
 #define SC_DPLL2CTRL	(SC_BASE_ADDR | 0x1480)	/* LD20: DDR memory 2 */
@@ -61,4 +63,12 @@
 #define   SC_CLKCTRL7_UMC31		(1 << 1)
 #define   SC_CLKCTRL7_UMC30		(1 << 0)
 
+#define SC_CA72_GEARST		(SC_BASE_ADDR | 0x8080)
+#define SC_CA72_GEARSET		(SC_BASE_ADDR | 0x8084)
+#define SC_CA72_GEARUPD		(SC_BASE_ADDR | 0x8088)
+#define SC_CA53_GEARST		(SC_BASE_ADDR | 0x8080)
+#define SC_CA53_GEARSET		(SC_BASE_ADDR | 0x8084)
+#define SC_CA53_GEARUPD		(SC_BASE_ADDR | 0x8088)
+#define   SC_CA_GEARUPD			(1 << 0)
+
 #endif /* SC64_REGS_H */
diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
index f6578c1..864e04e 100644
--- a/configs/uniphier_ld11_defconfig
+++ b/configs/uniphier_ld11_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_ARCH_UNIPHIER_LD11=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index b85f528..3fe3758 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_ARCH_UNIPHIER_LD20=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index e996355..c18f042 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index f0f47ee..9441b05 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index 64684de..0bf39f4 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index f4ed2ee..bd9c327 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_ARCH_UNIPHIER_SLD3=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index a91924e..3948326 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -14,10 +14,39 @@
 
 #include "clk-uniphier.h"
 
+/**
+ * struct uniphier_clk_priv - private data for UniPhier clock driver
+ *
+ * @base: base address of the clock provider
+ * @socdata: SoC specific data
+ */
+struct uniphier_clk_priv {
+	void __iomem *base;
+	const struct uniphier_clk_soc_data *socdata;
+};
+
+int uniphier_clk_probe(struct udevice *dev)
+{
+	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev->parent);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->base = devm_ioremap(dev, addr, SZ_4K);
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->socdata = (void *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
 static int uniphier_clk_enable(struct clk *clk)
 {
 	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
-	struct uniphier_clk_gate_data *gate = priv->socdata->gate;
+	const struct uniphier_clk_gate_data *gate = priv->socdata->gate;
 	unsigned int nr_gate = priv->socdata->nr_gate;
 	void __iomem *reg;
 	u32 mask, data, tmp;
@@ -44,7 +73,7 @@ static int uniphier_clk_enable(struct clk *clk)
 static ulong uniphier_clk_get_rate(struct clk *clk)
 {
 	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
-	struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
+	const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
 	unsigned int nr_rdata = priv->socdata->nr_rate;
 	void __iomem *reg;
 	u32 mask, data;
@@ -78,7 +107,7 @@ static ulong uniphier_clk_get_rate(struct clk *clk)
 static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
 {
 	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
-	struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
+	const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
 	unsigned int nr_rdata = priv->socdata->nr_rate;
 	void __iomem *reg;
 	u32 mask, data, tmp;
@@ -128,20 +157,47 @@ const struct clk_ops uniphier_clk_ops = {
 	.set_rate = uniphier_clk_set_rate,
 };
 
-int uniphier_clk_probe(struct udevice *dev)
-{
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
-	fdt_addr_t addr;
-
-	addr = dev_get_addr(dev);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-
-	priv->base = devm_ioremap(dev, addr, SZ_4K);
-	if (!priv->base)
-		return -ENOMEM;
-
-	priv->socdata = (void *)dev_get_driver_data(dev);
+static const struct udevice_id uniphier_clk_match[] = {
+	{
+		.compatible = "socionext,uniphier-sld3-mio-clock",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld4-mio-clock",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro4-mio-clock",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-sld8-mio-clock",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro5-mio-clock",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs2-mio-clock",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld11-mio-clock",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld20-mio-clock",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{ /* sentinel */ }
+};
 
-	return 0;
-}
+U_BOOT_DRIVER(uniphier_clk) = {
+	.name = "uniphier-clk",
+	.id = UCLASS_CLK,
+	.of_match = uniphier_clk_match,
+	.probe = uniphier_clk_probe,
+	.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
+	.ops = &uniphier_clk_ops,
+};
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 2eea5eb..c1e7197 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -115,7 +115,7 @@
 		.data = 0x00020000,		\
 	}
 
-static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
+static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
 	UNIPHIER_MIO_CLK_GATE_SD(0, 0),
 	UNIPHIER_MIO_CLK_GATE_SD(1, 1),
 	UNIPHIER_MIO_CLK_GATE_SD(2, 2),		/* for PH1-Pro4 only */
@@ -126,60 +126,15 @@ static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
 	UNIPHIER_MIO_CLK_GATE_USB(3, 7),	/* for PH1-sLD3 only */
 };
 
-static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
+static const struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
 	UNIPHIER_MIO_CLK_RATE_SD(0, 0),
 	UNIPHIER_MIO_CLK_RATE_SD(1, 1),
 	UNIPHIER_MIO_CLK_RATE_SD(2, 2),		/* for PH1-Pro4 only */
 };
 
-static struct uniphier_clk_soc_data uniphier_mio_clk_data = {
+const struct uniphier_clk_soc_data uniphier_mio_clk_data = {
 	.gate = uniphier_mio_clk_gate,
 	.nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
 	.rate = uniphier_mio_clk_rate,
 	.nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
 };
-
-static const struct udevice_id uniphier_mio_clk_match[] = {
-	{
-		.compatible = "socionext,ph1-sld3-mioctrl",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{
-		.compatible = "socionext,ph1-ld4-mioctrl",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{
-		.compatible = "socionext,ph1-pro4-mioctrl",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{
-		.compatible = "socionext,ph1-sld8-mioctrl",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{
-		.compatible = "socionext,ph1-pro5-mioctrl",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{
-		.compatible = "socionext,proxstream2-mioctrl",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{
-		.compatible = "socionext,ph1-ld11-mioctrl",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{
-		.compatible = "socionext,ph1-ld20-mioctrl",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(uniphier_mio_clk) = {
-	.name = "uniphier-mio-clk",
-	.id = UCLASS_CLK,
-	.of_match = uniphier_mio_clk_match,
-	.probe = uniphier_clk_probe,
-	.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
-	.ops = &uniphier_clk_ops,
-};
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
index 18aa888..0b60337 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -27,9 +27,9 @@ struct uniphier_clk_rate_data {
 };
 
 struct uniphier_clk_soc_data {
-	struct uniphier_clk_gate_data *gate;
+	const struct uniphier_clk_gate_data *gate;
 	unsigned int nr_gate;
-	struct uniphier_clk_rate_data *rate;
+	const struct uniphier_clk_rate_data *rate;
 	unsigned int nr_rate;
 };
 
@@ -40,18 +40,6 @@ struct uniphier_clk_soc_data {
 		.rate = f,				\
 	}
 
-/**
- * struct uniphier_clk_priv - private data for UniPhier clock driver
- *
- * @base: base address of the clock provider
- * @socdata: SoC specific data
- */
-struct uniphier_clk_priv {
-	void __iomem *base;
-	struct uniphier_clk_soc_data *socdata;
-};
-
-extern const struct clk_ops uniphier_clk_ops;
-int uniphier_clk_probe(struct udevice *dev);
+extern const struct uniphier_clk_soc_data uniphier_mio_clk_data;
 
 #endif /* __CLK_UNIPHIER_H__ */