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| author | Ye.Li <B37916@freescale.com> | 2014-10-30 18:20:58 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-11-03 11:21:49 +0100 |
| commit | 0f8ec145ba1354a479abecf7f83a86bb6db04ba2 (patch) | |
| tree | 678877e6485e5bfc57594a0100cccd9c561c9540 | |
| parent | e68661a32eb1304413ce45900446bcce9204537e (diff) | |
| download | u-boot-imx-0f8ec145ba1354a479abecf7f83a86bb6db04ba2.zip u-boot-imx-0f8ec145ba1354a479abecf7f83a86bb6db04ba2.tar.gz u-boot-imx-0f8ec145ba1354a479abecf7f83a86bb6db04ba2.tar.bz2 | |
imx: mx6sl: Set the preclk clock source to OSC 24Mhz
For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the
preclk setting with kernel.
Signed-off-by: Ye.Li <B37916@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 6dc2600..c0bb431 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -239,6 +239,18 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); } +#ifdef CONFIG_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif + int arch_cpu_init(void) { init_aips(); @@ -254,6 +266,11 @@ int arch_cpu_init(void) if (mxc_get_clock(MXC_ARM_CLK) == 396000000) set_ahb_rate(132000000); + /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_MX6SL) + set_preclk_from_osc(); +#endif + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifdef CONFIG_APBH_DMA |