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authorPavel Machek <pavel@denx.de>2014-12-11 18:06:31 +0100
committerMarek Vasut <marex@denx.de>2014-12-16 15:32:14 +0100
commit065496d1b5304a6a67b366b613c3504aab2e2dbd (patch)
tree08b5ddecbeef30db3b66db7546e5ddc533373cfc
parentb9b5cf0ea3c5c141f31cc0c4c8edebbfd9ff5866 (diff)
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arm: socfpga: board: Repair Micrel PHY tuning
Add proper error checking into the PHY tuning patch. Make the PHY tunning only happen in case the KSZ9021 PHY is enabled in config. Call the config callback after the tuning finished. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Tom Rini <trini@ti.com> Cc: Pavel Machek <pavel@denx.de>
-rw-r--r--board/altera/socfpga/socfpga_cyclone5.c34
1 files changed, 28 insertions, 6 deletions
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 772a58e..459d82f 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -46,19 +46,41 @@ int board_init(void)
return 0;
}
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
int board_phy_config(struct phy_device *phydev)
{
+ int ret;
/*
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
* to work reliably on most flavors of cyclone5 boards.
*/
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
}
+#endif
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {