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MLK-10227 video: mxsfb: Correct interrupt handling

We've got a race condition bewteen the interrupt handler mxsfb_irq_handler()
and the function mxsfb_wait_for_vsync() on the flag host->wait4vsync.
If a CUR_FRAME_DONE interrupt comes and we just finish setting host->wait4vsync
to be 1 in mxsfb_wait_for_vsync() before we go to the interrupt handler, we are
likely to see the VSYNC_EDGE interrupt status bit asserted in the interrupt
handler for the CUR_FRAME_DONE interrupt, disable the not yet enabled VSYNC_EDGE
interrupt and finally clear host->wait4vsync.
Then, we go back to mxsfb_wait_for_vsync() and enable the VSYNC_EDGE interrupt
with host->wait4vsync=0.  This may leave the VSYNC_EDGE interrupt enabled all
the time and never get a chance to be disabled in the interrupt handler.
So, we are deemed to hang up because the uncleared VSYNC_EDGE interrupt status
bit will cause the CPU to be trapped forever, according to SoC designer's words.
This patch corrects the interrupt handling to handle only the interrupts which
are acknowledged by checking both the interrupt enablement bits and the status
bits but not the status bits only.  This may avoid any bogus interrupt from
being handled.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 24e1e55076)
isee-imx_3.14.28.y
Liu Ying 6 years ago
parent
commit
fea9f69322
1 changed files with 23 additions and 12 deletions
  1. +23
    -12
      drivers/video/mxsfb.c

+ 23
- 12
drivers/video/mxsfb.c View File

@ -115,6 +115,16 @@
#define CTRL1_UNDERFLOW_IRQ (1 << 10)
#define CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
#define CTRL1_VSYNC_EDGE_IRQ (1 << 8)
#define CTRL1_IRQ_ENABLE_MASK (CTRL1_OVERFLOW_IRQ_EN | \
CTRL1_UNDERFLOW_IRQ_EN | \
CTRL1_CUR_FRAME_DONE_IRQ_EN | \
CTRL1_VSYNC_EDGE_IRQ_EN)
#define CTRL1_IRQ_ENABLE_SHIFT 12
#define CTRL1_IRQ_STATUS_MASK (CTRL1_OVERFLOW_IRQ | \
CTRL1_UNDERFLOW_IRQ | \
CTRL1_CUR_FRAME_DONE_IRQ | \
CTRL1_VSYNC_EDGE_IRQ)
#define CTRL1_IRQ_STATUS_SHIFT 8
#define CTRL2_OUTSTANDING_REQS__REQ_16 (3 << 21)
@ -367,31 +377,32 @@ static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
static irqreturn_t mxsfb_irq_handler(int irq, void *dev_id)
{
struct mxsfb_info *host = dev_id;
u32 status_lcd = readl(host->base + LCDC_CTRL1);
u32 ctrl1, enable, status, acked_status;
if ((status_lcd & CTRL1_VSYNC_EDGE_IRQ) &&
host->wait4vsync) {
ctrl1 = readl(host->base + LCDC_CTRL1);
enable = (ctrl1 & CTRL1_IRQ_ENABLE_MASK) >> CTRL1_IRQ_ENABLE_SHIFT;
status = (ctrl1 & CTRL1_IRQ_STATUS_MASK) >> CTRL1_IRQ_STATUS_SHIFT;
acked_status = (enable & status) << CTRL1_IRQ_STATUS_SHIFT;
if ((acked_status & CTRL1_VSYNC_EDGE_IRQ) && host->wait4vsync) {
writel(CTRL1_VSYNC_EDGE_IRQ_EN,
host->base + LCDC_CTRL1 + REG_CLR);
host->wait4vsync = 0;
complete(&host->vsync_complete);
}
if (status_lcd & CTRL1_CUR_FRAME_DONE_IRQ) {
if (acked_status & CTRL1_CUR_FRAME_DONE_IRQ) {
writel(CTRL1_CUR_FRAME_DONE_IRQ_EN,
host->base + LCDC_CTRL1 + REG_CLR);
up(&host->flip_sem);
}
if (status_lcd & CTRL1_UNDERFLOW_IRQ) {
writel(CTRL1_UNDERFLOW_IRQ,
host->base + LCDC_CTRL1 + REG_CLR);
}
if (acked_status & CTRL1_UNDERFLOW_IRQ)
writel(CTRL1_UNDERFLOW_IRQ, host->base + LCDC_CTRL1 + REG_CLR);
if (acked_status & CTRL1_OVERFLOW_IRQ)
writel(CTRL1_OVERFLOW_IRQ, host->base + LCDC_CTRL1 + REG_CLR);
if (status_lcd & CTRL1_OVERFLOW_IRQ) {
writel(CTRL1_OVERFLOW_IRQ,
host->base + LCDC_CTRL1 + REG_CLR);
}
return IRQ_HANDLED;
}


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