MLK-10003-1: ASoC: fsl_sai: The record sound is faster or slower in master mode

The default setting of sai is RX sync with TX, TX output the I2S clock. So When recording, we should set TCR2's divider, not RCR2's divider. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>

MLK-10003-1: ASoC: fsl_sai: The record sound is faster or slower in master mode
9bfe1d33 · Shengjiu Wang · 991a1f26 · 9bfe1d33
Commit 9bfe1d33 authored Dec 16, 2014 by Shengjiu Wang
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Showing with 11 additions and 4 deletions

fsl_sai.c sound/soc/fsl/fsl_sai.c +11 -4

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--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -349,10 +349,17 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
 		return -EINVAL;
 	}

-	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), FSL_SAI_CR2_MSEL_MASK,
-			   FSL_SAI_CR2_MSEL(sai->mclk_id));
-	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
-			   FSL_SAI_CR2_DIV_MASK, savediv - 1);
+	if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
+		regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_MSEL_MASK,
+				FSL_SAI_CR2_MSEL(sai->mclk_id));
+		regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
+				FSL_SAI_CR2_DIV_MASK, savediv - 1);
+	} else {
+		regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_MSEL_MASK,
+				FSL_SAI_CR2_MSEL(sai->mclk_id));
+		regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
+				FSL_SAI_CR2_DIV_MASK, savediv - 1);
+	}

 	dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
 			sai->mclk_id, savediv, savesub);