1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
|
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* Configuration settings for the MX6Solo SABRE-AI Freescale board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/mx6.h>
/* High Level Configuration Options */
#define CONFIG_MFG
#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
#define CONFIG_MXC
#define CONFIG_MX6DL
#define CONFIG_MX6DL_DDR3
#define CONFIG_MX6Q_SABREAUTO
#define CONFIG_FLASH_HEADER
#define CONFIG_FLASH_HEADER_OFFSET 0x400
#define CONFIG_MX6_CLK32 32768
#define CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_ARCH_MMU /* disable MMU first */
#define CONFIG_L2_OFF /* disable L2 cache first*/
#define CONFIG_MX6_HCLK_FREQ 24000000
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_64BIT_VSPRINTF
#define BOARD_LATE_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SERIAL_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_MXC_GPIO
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Hardware drivers
*/
#define CONFIG_MXC_UART
#define CONFIG_UART_BASE_ADDR UART4_BASE_ADDR
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/***********************************************************
* Command definition
***********************************************************/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_NET_MULTI 1
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
#define CONFIG_CMD_SPI
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMXOTP
/* Enable below configure when supporting nand */
#define CONFIG_CMD_SF
#define CONFIG_CMD_MMC
#define CONFIG_CMD_ENV
#define CONFIG_CMD_REGUL
#define CONFIG_CMD_CLOCK
#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_IMX_DOWNLOAD_MODE
#define CONFIG_BOOTDELAY 0
#define CONFIG_PRIME "FEC0"
#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
#define CONFIG_BOOTARGS "console=ttymxc3,115200 rdinit=/linuxrc mtdparts=gpmi-nand:16m(boot),16m(kernel),128m(rootfs),-(user)"\
"arm_freq=800"
#define CONFIG_BOOTCOMMAND "bootm 0x10800000 0x10c00000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ethprime=FEC0\0" \
"uboot=u-boot.bin\0" \
"kernel=uImage\0" \
#define CONFIG_ARP_TIMEOUT 200UL
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "MX6SOLO SABREAUTO MFG U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10010000
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
#define CONFIG_FEC0_PINMUX -1
#define CONFIG_FEC0_MIIBASE -1
#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
#define CONFIG_MXC_FEC
#define CONFIG_FEC0_PHY_ADDR 1
#define CONFIG_ETH_PRIME
#define CONFIG_RMII
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_CMD_MII
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_IPADDR 192.168.1.103
#define CONFIG_SERVERIP 192.168.1.101
#define CONFIG_NETMASK 255.255.255.0
/*
* OCOTP Configs
*/
#ifdef CONFIG_CMD_IMXOTP
#define CONFIG_IMX_OTP
#define IMX_OTP_BASE OCOTP_BASE_ADDR
#define IMX_OTP_ADDR_MAX 0x7F
#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
#endif
/*
* I2C Configs
*/
#ifdef CONFIG_CMD_I2C
#define CONFIG_HARD_I2C 1
#define CONFIG_I2C_MXC 1
#define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0x30
#endif
/*
* SPI Configs
*/
#ifdef CONFIG_CMD_SF
#define CONFIG_FSL_SF 1
#define CONFIG_SPI_FLASH_IMX_M25PXX 1
#define CONFIG_SPI_FLASH_CS 1
#define CONFIG_IMX_ECSPI
#define IMX_CSPI_VER_2_3 1
#define MAX_SPI_BYTES (64 * 4)
#endif
/* Regulator Configs */
#ifdef CONFIG_CMD_REGUL
#define CONFIG_ANATOP_REGULATOR
#define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
#define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
#endif
/*
* MMC Configs
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_IMX_MMC
#define CONFIG_SYS_FSL_USDHC_NUM 4
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_ENV_DEV 2
#define CONFIG_DOS_PARTITION 1
#define CONFIG_CMD_FAT 1
#define CONFIG_CMD_EXT2 1
/* detect whether SD1, 2, 3, or 4 is boot device */
#define CONFIG_DYNAMIC_MMC_DEVNO
/* SD3 and SD4 are 8 bit */
#define CONFIG_MMC_8BIT_PORTS 0xC
/* Setup target delay in DDR mode for each SD port */
#define CONFIG_GET_DDR_TARGET_DELAY
#endif
/*
* GPMI Nand Configs
*/
/* #define CONFIG_CMD_NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_GPMI
#define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK
#define CONFIG_GPMI_NFC_V2
#define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR
#define CONFIG_BCH_REG_BASE BCH_BASE_ADDR
#define NAND_MAX_CHIPS 8
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* NAND is the unique module invoke APBH-DMA */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_V2
#define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR
#endif
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
#ifdef CONFIG_DDR_32BIT
#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
#else
#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
#endif
#define iomem_valid_addr(addr, size) \
(addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_NO_FLASH
/* Monitor at beginning of flash */
/* #define CONFIG_FSL_ENV_IN_MMC */
/* #define CONFIG_FSL_ENV_IN_SATA */
/* #define CONFIG_FSL_ENV_IN_SF */
#define CONFIG_ENV_SECT_SIZE (8 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_IS_NOWHERE 1
#endif /* __CONFIG_H */
|
