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/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1012ARDB_H__
#define __LS1012ARDB_H__
#include "ls1012a_common.h"
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
/* DDR board-specific timing parameters */
#define CONFIG_MMDC_MDCTL 0x04180000
#define CONFIG_MMDC_MDPDC 0x00030035
#define CONFIG_MMDC_MDOTC 0x12554000
#define CONFIG_MMDC_MDCFG0 0xbabf7954
#define CONFIG_MMDC_MDCFG1 0xdb328f64
#define CONFIG_MMDC_MDCFG2 0x01ff00db
#define CONFIG_MMDC_MDMISC 0x00001680
#define CONFIG_MMDC_MDREF 0x0f3c8000
#define CONFIG_MMDC_MDRWD 0x00002000
#define CONFIG_MMDC_MDOR 0x00bf1023
#define CONFIG_MMDC_MDASP 0x0000003f
#define CONFIG_MMDC_MPODTCTRL 0x0000022a
#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
/*
* USB
*/
#define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
#endif /* __LS1012ARDB_H__ */
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