1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
|
/*
* National Semiconductor PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <phy.h>
/* NatSemi DP83630 */
#define DP83630_PHY_PAGESEL_REG 0x13
#define DP83630_PHY_PTP_COC_REG 0x14
#define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
#define DP83630_PHY_RBR_REG 0x17
static int dp83630_config(struct phy_device *phydev)
{
int ptp_coc_reg;
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
DP83630_PHY_PTP_COC_REG);
ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
ptp_coc_reg);
phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
genphy_config_aneg(phydev);
return 0;
}
static struct phy_driver DP83630_driver = {
.name = "NatSemi DP83630",
.uid = 0x20005ce1,
.mask = 0xfffffff0,
.features = PHY_BASIC_FEATURES,
.config = &dp83630_config,
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
/* DP83865 Link and Auto-Neg Status Register */
#define MIIM_DP83865_LANR 0x11
#define MIIM_DP83865_SPD_MASK 0x0018
#define MIIM_DP83865_SPD_1000 0x0010
#define MIIM_DP83865_SPD_100 0x0008
#define MIIM_DP83865_DPX_FULL 0x0002
/* NatSemi DP83865 */
static int dp83865_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
genphy_config_aneg(phydev);
return 0;
}
static int dp83865_parse_status(struct phy_device *phydev)
{
int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
switch (mii_reg & MIIM_DP83865_SPD_MASK) {
case MIIM_DP83865_SPD_1000:
phydev->speed = SPEED_1000;
break;
case MIIM_DP83865_SPD_100:
phydev->speed = SPEED_100;
break;
default:
phydev->speed = SPEED_10;
break;
}
if (mii_reg & MIIM_DP83865_DPX_FULL)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
return 0;
}
static int dp83865_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
dp83865_parse_status(phydev);
return 0;
}
static struct phy_driver DP83865_driver = {
.name = "NatSemi DP83865",
.uid = 0x20005c70,
.mask = 0xfffffff0,
.features = PHY_GBIT_FEATURES,
.config = &dp83865_config,
.startup = &dp83865_startup,
.shutdown = &genphy_shutdown,
};
int phy_natsemi_init(void)
{
phy_register(&DP83630_driver);
phy_register(&DP83865_driver);
return 0;
}
|
