summaryrefslogtreecommitdiff
path: root/drivers/net/phy/mv88e61xx.c
blob: 3754e8bdc43206760c184706ffbee78dc69fc398 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Prafulla Wadaskar <prafulla@marvell.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

#include <common.h>
#include <netdev.h>
#include "mv88e61xx.h"

#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
/* Chip Address mode
 * The Switch support two modes of operation
 * 1. single chip mode and
 * 2. Multi-chip mode
 * Refer section 9.2 &9.3 in chip datasheet-02 for more details
 *
 * By default single chip mode is configured
 * multichip mode operation can be configured in board header
 */
static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
{
	u16 reg = 0;
	u32 timeout = MV88E61XX_PHY_TIMEOUT;

	/* Poll till SMIBusy bit is clear */
	do {
		miiphy_read(name, devaddr, 0x0, &reg);
		if (timeout-- == 0) {
			printf("SMI busy timeout\n");
			return -1;
		}
	} while (reg & (1 << 15));
	return 0;
}

static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
{
	u16 mii_dev_addr;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
		printf("Error..could not read PHY dev address\n");
		return;
	}
	mv88e61xx_busychk_multic(name, mii_dev_addr);
	/* Write data to Switch indirect data register */
	miiphy_write(name, mii_dev_addr, 0x1, data);
	/* Write command to Switch indirect command register (write) */
	miiphy_write(name, mii_dev_addr, 0x0,
		     reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
									 15));
}

static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
{
	u16 mii_dev_addr;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
		printf("Error..could not read PHY dev address\n");
		return;
	}
	mv88e61xx_busychk_multic(name, mii_dev_addr);
	/* Write command to Switch indirect command register (read) */
	miiphy_write(name, mii_dev_addr, 0x0,
		     reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
									 15));
	mv88e61xx_busychk_multic(name, mii_dev_addr);
	/* Read data from Switch indirect data register */
	miiphy_read(name, mii_dev_addr, 0x1, data);
}
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */

static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
				       u32 max_prtnum, u32 ports_ofs)
{
	u32 prt;
	u16 reg;
	char *name = swconfig->name;
	u32 cpu_port = swconfig->cpuport;
	u32 port_mask = swconfig->ports_enabled;
	enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;

	/* be sure all ports are disabled */
	for (prt = 0; prt < max_prtnum; prt++) {
		RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, &reg);
		reg &= ~0x3;
		WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);

		if (!(cpu_port & (1 << prt)))
			continue;
		/* Set CPU port VID to 0x1 */
		RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, &reg);
		reg &= ~0xfff;
		reg |= 0x1;
		WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
	}

	/* Setting  Port default priority for all ports to zero */
	for (prt = 0; prt < max_prtnum; prt++) {
		RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, &reg);
		reg &= ~0xc000;
		WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
	}
	/* Setting VID and VID map for all ports except CPU port */
	for (prt = 0; prt < max_prtnum; prt++) {
		/* only for enabled ports */
		if ((1 << prt) & port_mask) {
			/* skip CPU port */
			if ((1 << prt) & cpu_port) {
				/*
				 * Set Vlan map table for cpu_port to see
				 * all ports
				 */
				RD_PHY(name, (ports_ofs + prt),
				       MV88E61XX_PRT_VMAP_REG, &reg);
				reg &= ~((1 << max_prtnum) - 1);
				reg |= port_mask & ~(1 << prt);
				WR_PHY(name, (ports_ofs + prt),
				       MV88E61XX_PRT_VMAP_REG, reg);
			} else {

				/*
				 *  set Ports VLAN Mapping.
				 *      port prt <--> cpu_port VLAN #prt+1.
				 */
				RD_PHY(name, ports_ofs + prt,
				       MV88E61XX_PRT_VID_REG, &reg);
				reg &= ~0x0fff;
				reg |= (prt + 1);
				WR_PHY(name, ports_ofs + prt,
				       MV88E61XX_PRT_VID_REG, reg);

				RD_PHY(name, ports_ofs + prt,
				       MV88E61XX_PRT_VMAP_REG, &reg);
				if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
					/*
					 * all any port can send frames to all other ports
					 * ref: sec 3.2.1.1 of datasheet
					 */
					reg |= 0x03f;
					reg &= ~(1 << prt);
				} else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
					/*
					 * all other ports can send frames to CPU port only
					 * ref: sec 3.2.1.2 of datasheet
					 */
					reg &= ~((1 << max_prtnum) - 1);
					reg |= cpu_port;
				}
				WR_PHY(name, ports_ofs + prt,
				       MV88E61XX_PRT_VMAP_REG, reg);
			}
		}
	}

	/*
	 * enable only appropriate ports to forwarding mode
	 * and disable the others
	 */
	for (prt = 0; prt < max_prtnum; prt++) {
		if ((1 << prt) & port_mask) {
			RD_PHY(name, ports_ofs + prt,
			       MV88E61XX_PRT_CTRL_REG, &reg);
			reg |= 0x3;
			WR_PHY(name, ports_ofs + prt,
			       MV88E61XX_PRT_CTRL_REG, reg);
		} else {
			/* Disable port */
			RD_PHY(name, ports_ofs + prt,
			       MV88E61XX_PRT_CTRL_REG, &reg);
			reg &= ~0x3;
			WR_PHY(name, ports_ofs + prt,
			       MV88E61XX_PRT_CTRL_REG, reg);
		}
	}
}

/*
 * Make sure SMIBusy bit cleared before another
 * SMI operation can take place
 */
static int mv88e61xx_busychk(char *name)
{
	u32 reg = 0;
	u32 timeout = MV88E61XX_PHY_TIMEOUT;
	do {
		RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
		       MV88E61XX_PHY_CMD, (u16 *) & reg);
		if (timeout-- == 0) {
			printf("SMI busy timeout\n");
			return -1;
		}
	} while (reg & 1 << 15);	/* busy mask */
	return 0;
}

/*
 * Power up the specified port and reset PHY
 */
static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
{
	char *name = swconfig->name;

	/* Write Copper Specific control reg1 (0x14) for-
	 * Enable Phy power up
	 * Energy Detect on (sense&Xmit NLP Periodically
	 * reset other settings default
	 */
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360);
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
	       MV88E61XX_PHY_CMD, (0x9410 | (prt << 5)));

	if (mv88e61xx_busychk(name))
		return -1;

	/* Write PHY ctrl reg (0x0) to apply
	 * Phy reset (set bit 15 low)
	 * reset other default values
	 */
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140);
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
	       MV88E61XX_PHY_CMD, (0x9400 | (prt << 5)));

	if (mv88e61xx_busychk(name))
		return -1;

	return 0;
}

/*
 * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
 * is set to "On-1000Mb/s Link, Off Else"
 * This function sets it to "On-Link, Blink-Activity, Off-NoLink"
 *
 * This is optional settings may be needed on some boards
 * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
 * Link status
 */
static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
{
	char *name = swconfig->name;
	u16 reg;

	if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
		return 0;

	/* set page address to 3 */
	reg = 3;
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
				   1 << MV88E61XX_MODE_OFST |
				   1 << MV88E61XX_OP_OFST |
				   prt << MV88E61XX_ADDR_OFST | 22));

	if (mv88e61xx_busychk(name))
		return -1;

	/* set LED Func Ctrl reg */
	reg = 1;	/* LED[0] On-Link, Blink-Activity, Off-NoLink */
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
				   1 << MV88E61XX_MODE_OFST |
				   1 << MV88E61XX_OP_OFST |
				   prt << MV88E61XX_ADDR_OFST | 16));

	if (mv88e61xx_busychk(name))
		return -1;

	/* set page address to 0 */
	reg = 0;
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
				   1 << MV88E61XX_MODE_OFST |
				   1 << MV88E61XX_OP_OFST |
				   prt << MV88E61XX_ADDR_OFST | 22));

	if (mv88e61xx_busychk(name))
		return -1;

	return 0;
}

/*
 * Reverse Transmit polarity for Media Dependent Interface
 * Pins (MDIP) bits in Copper Specific Control Register 3
 * (Page 0, Reg 20 for each phy (except cpu port)
 * Reference: Section 1.1 Switch datasheet-3
 *
 * This is optional settings may be needed on some boards
 * for PHY<->magnetics h/w tuning
 */
static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt)
{
	char *name = swconfig->name;
	u16 reg;

	if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
		return 0;

	reg = 0x0f;		/*Reverse MDIP/N[3:0] bits */
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
				   1 << MV88E61XX_MODE_OFST |
				   1 << MV88E61XX_OP_OFST |
				   prt << MV88E61XX_ADDR_OFST | 20));

	if (mv88e61xx_busychk(name))
		return -1;

	return 0;
}

/*
 * Marvell 88E61XX Switch initialization
 */
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
{
	u32 prt;
	u16 reg;
	char *idstr;
	char *name = swconfig->name;

	if (miiphy_set_current_dev(name)) {
		printf("%s failed\n", __FUNCTION__);
		return -1;
	}

	if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
		swconfig->cpuport = (1 << 5);
		printf("Invalid cpu port config, using default port5\n");
	}

	RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg);
	switch (reg &= 0xfff0) {
	case 0x1610:
		idstr = "88E6161";
		break;
	case 0x1650:
		idstr = "88E6165";
		break;
	case 0x1210:
		idstr = "88E6123";
		/* ports 2,3,4 not available */
		swconfig->ports_enabled &= 0x023;
		break;
	default:
		/* Could not detect switch id */
		idstr = "88E61??";
		break;
	}

	/* Port based VLANs configuration */
	if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
	    || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
		mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
					   MV88E61XX_PRT_OFST);
	else {
		printf("Unsupported mode %s failed\n", __FUNCTION__);
		return -1;
	}

	if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
		/*
		 * Enable RGMII delay on Tx and Rx for CPU port
		 * Ref: sec 9.5 of chip datasheet-02
		 */
		WR_PHY(name, MV88E61XX_PRT_OFST + 5,
		       MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
		WR_PHY(name, MV88E61XX_PRT_OFST + 4,
		       MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
	}

	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
		if (!((1 << prt) & swconfig->cpuport)) {

			if (mv88361xx_led_init(swconfig, prt))
				return -1;
			if (mv88361xx_reverse_mdipn(swconfig, prt))
				return -1;
			if (mv88361xx_powerup(swconfig, prt))
				return -1;
		}

		/*Program port state */
		RD_PHY(name, MV88E61XX_PRT_OFST + prt,
		       MV88E61XX_PRT_CTRL_REG, &reg);
		WR_PHY(name, MV88E61XX_PRT_OFST + prt,
		       MV88E61XX_PRT_CTRL_REG,
		       reg | (swconfig->portstate & 0x03));
	}

	printf("%s Initialized on %s\n", idstr, name);
	return 0;
}