1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
|
/*
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0x0F
#define ZYNQ_BM_NOR 0x02
#define ZYNQ_BM_SD 0x05
#define ZYNQ_BM_JTAG 0x0
#ifdef CONFIG_FPGA
Xilinx_desc fpga;
/* It can be done differently */
Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
int board_init(void)
{
#ifdef CONFIG_FPGA
u32 idcode;
idcode = zynq_slcr_get_idcode();
switch (idcode) {
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
case XILINX_ZYNQ_7015:
fpga = fpga015;
break;
case XILINX_ZYNQ_7020:
fpga = fpga020;
break;
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
case XILINX_ZYNQ_7100:
fpga = fpga100;
break;
}
#endif
#ifdef CONFIG_FPGA
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
return 0;
}
int board_late_init(void)
{
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
case ZYNQ_BM_NOR:
setenv("modeboot", "norboot");
break;
case ZYNQ_BM_SD:
setenv("modeboot", "sdboot");
break;
case ZYNQ_BM_JTAG:
setenv("modeboot", "jtagboot");
break;
default:
setenv("modeboot", "");
break;
}
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
#ifdef CONFIG_XILINX_AXIEMAC
ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
XILINX_AXIDMA_BASEADDR);
#endif
#ifdef CONFIG_XILINX_EMACLITE
u32 txpp = 0;
u32 rxpp = 0;
# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
txpp = 1;
# endif
# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
rxpp = 1;
# endif
ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
txpp, rxpp);
#endif
#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
# endif
#endif
return ret;
}
#endif
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{
int ret = 0;
#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
return ret;
}
#endif
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
zynq_ddrc_init();
return 0;
}
|
