1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
|
/*
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
extern long int spd_sdram (void);
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
long int fixed_sdram (void);
#if defined(CONFIG_DDR_ECC)
void dma_init(void);
uint dma_check(void);
int dma_xfer(void *dest, uint count, void *src);
#endif
/* MPC8540ADS Board Status & Control Registers */
#if 0
typedef struct bscr_ {
unsigned long bcsr0;
unsigned long bcsr1;
unsigned long bcsr2;
unsigned long bcsr3;
unsigned long bcsr4;
unsigned long bcsr5;
unsigned long bcsr6;
unsigned long bcsr7;
} bcsr_t;
#endif
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
return 0;
}
int checkboard (void)
{
puts("Board: ADS\n");
return 0;
}
long int initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur= &immap->im_gur;
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
uint pvr = get_pvr();
if (pvr == PVR_85xx_REV1) {
/*
* Need change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4
* temporarily.
*/
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CFG_BR2_PRELIM;
lbc->lbcr = CFG_LBC_LBCR;
lbc->lsdmr = CFG_LBC_LSDMR_1;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_3;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_5;
asm("sync");
lbc->lsrt = CFG_LBC_LSRT;
asm("sync");
lbc->mrtpr = CFG_LBC_MRTPR;
asm("sync");
#endif
#if defined(CONFIG_DDR_ECC)
{
/* Initialize all of memory for ECC, then
* enable errors */
uint *p = 0;
uint i = 0;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
}
/* 8K */
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
/* 16K */
dma_xfer((uint *)0x4000,0x4000,(uint *)0);
/* 32K */
dma_xfer((uint *)0x8000,0x8000,(uint *)0);
/* 64K */
dma_xfer((uint *)0x10000,0x10000,(uint *)0);
/* 128k */
dma_xfer((uint *)0x20000,0x20000,(uint *)0);
/* 256k */
dma_xfer((uint *)0x40000,0x40000,(uint *)0);
/* 512k */
dma_xfer((uint *)0x80000,0x80000,(uint *)0);
/* 1M */
dma_xfer((uint *)0x100000,0x100000,(uint *)0);
/* 2M */
dma_xfer((uint *)0x200000,0x200000,(uint *)0);
/* 4M */
dma_xfer((uint *)0x400000,0x400000,(uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
}
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
asm("sync;isync;msync");
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
return (CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
