blob: d5318c4f32823ec37e7b0d298257f9592ed03ae9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
/*
* LG Optimus Black (P970) codename sniper board
*
* Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <dm.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <ns16550.h>
#include <twl4030.h>
#include "sniper.h"
DECLARE_GLOBAL_DATA_PTR;
const omap3_sysinfo sysinfo = {
.mtype = DDR_STACKED,
.board_string = "Sniper",
.nand_string = "MMC"
};
static const struct ns16550_platdata serial_omap_platdata = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK
};
U_BOOT_DEVICE(sniper_serial) = {
.name = "serial_omap",
.platdata = &serial_omap_platdata
};
#ifdef CONFIG_SPL_BUILD
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
timings->ctrla = HYNIX_V_ACTIMA_200;
timings->ctrlb = HYNIX_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
timings->mr = MICRON_V_MR_165;
}
#endif
u32 get_board_rev(void)
{
/* Sold devices are expected to be at least revision F. */
return 6;
}
int board_init(void)
{
/* GPMC init */
gpmc_init();
/* MACH number */
gd->bd->bi_arch_number = 3000;
/* ATAGs location */
gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
return 0;
}
void set_muxconf_regs(void)
{
MUX_SNIPER();
}
#ifndef CONFIG_SPL_BUILD
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(1, 0, 0, -1, -1);
}
#endif
void board_mmc_power_init(void)
{
twl4030_power_mmc_init(1);
}
|