path: root/board/isee/igep0046/igep0046.c

/*
 * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
 *
 * Source file for IGEP0046 board
 *
 * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mx6-ddr.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <malloc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx6/sys_proto.h>
#include <i2c.h>
#include <asm/io.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "pfuze.h"
#include "igep0046_eeprom.h"
#include "../common/igep_common.h"
#include <usb.h>
#include <mmc.h>

DECLARE_GLOBAL_DATA_PTR;

/* MACRO MUX defines */
#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define GPIO_VERSION_PAD_CTRL  (PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
	PAD_CTL_SRE_FAST)

#define GPIO_LED_PAD_CTRL  (PAD_CTL_PUS_22K_UP |	\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |	\
	PAD_CTL_SRE_FAST )

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |	\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS |	\
	PAD_CTL_PUE | PAD_CTL_PKE)

#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_100K_DOWN |	\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#ifdef CONFIG_SYS_I2C
#define I2C_PAD_CTRL  ( PAD_CTL_ODE | PAD_CTL_SPEED_MED |	\
	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PMIC	1
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
#endif

#ifdef CONFIG_USB_EHCI_MX6
#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
#endif

#define PCB_CFG_0	IMX_GPIO_NR(3, 22)
#define PCB_CFG_1	IMX_GPIO_NR(3, 23)
#define PCB_CFG_2	IMX_GPIO_NR(3, 29)
#define PCB_CFG_3	IMX_GPIO_NR(6, 31)
#define PCB_REV_A	1
#define PCB_REV_B	2
#define PCB_REV_C	3
#define PCB_REV_D10	4

/* Dual Lite case */
#define GPIO_LED_RED1		IMX_GPIO_NR(4, 18)
#define GPIO_LED_GREEN1		IMX_GPIO_NR(4, 19)
#define GPIO_LED_RED2		IMX_GPIO_NR(4, 20)
#define GPIO_LED_GREEN2		IMX_GPIO_NR(4, 17)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = imx_ddr_size();
}

/* UART MUX */
static iomux_v3_cfg_t const uart1_pads[] =
{
	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const uart2_pads[] =
{
	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};

/* SDIO MUX */
iomux_v3_cfg_t const usdhc1_pads[] =
{
	MX6_PAD_SD1_CLK__SD1_CLK		| MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
	MX6_PAD_SD1_CMD__SD1_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL),
};
/* eMMC MUX */
iomux_v3_cfg_t const usdhc3_pads[] =
{
	MX6_PAD_SD3_CLK__SD3_CLK   	| MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
	MX6_PAD_SD3_CMD__SD3_CMD   	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
/* Ethernet MUX */
iomux_v3_cfg_t const enet_pads[] =
{
	MX6_PAD_ENET_MDIO__ENET_MDIO				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_MDC__ENET_MDC				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TXC__RGMII_TXC				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD0__RGMII_TD0				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD1__RGMII_TD1				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD2__RGMII_TD2				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD3__RGMII_TD3				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL			| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK			| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RXC__RGMII_RXC				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD0__RGMII_RD0				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD1__RGMII_RD1				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD2__RGMII_RD2				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD3__RGMII_RD3				| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL			| MUX_PAD_CTRL(ENET_PAD_CTRL),
	/* Marvell Alaska PHY Reset */
	MX6_PAD_ENET_CRS_DV__GPIO1_IO25				| MUX_PAD_CTRL(NO_PAD_CTRL),
};
/* GPIO MISC MUX */
static iomux_v3_cfg_t const init_pads[] =
{
	/* PCB GPIO to Detect Module Version */
	MX6_PAD_EIM_D22__GPIO3_IO22  | MUX_PAD_CTRL(GPIO_VERSION_PAD_CTRL),
	MX6_PAD_EIM_D23__GPIO3_IO23  | MUX_PAD_CTRL(GPIO_VERSION_PAD_CTRL),
	MX6_PAD_EIM_D29__GPIO3_IO29  | MUX_PAD_CTRL(GPIO_VERSION_PAD_CTRL),
	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(GPIO_VERSION_PAD_CTRL),
	/* PCB GPIO LEDs */
	MX6_PAD_DI0_PIN2__GPIO4_IO18  | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
	MX6_PAD_DI0_PIN3__GPIO4_IO19  | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
	MX6_PAD_DI0_PIN4__GPIO4_IO20  | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
	MX6_PAD_DI0_PIN15__GPIO4_IO17 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
	#ifdef CONFIG_BASE0040
	/* TLV320AIC3106 Audio codec Reset*/
	MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
	/* USB2514 HUB Reset */
	MX6_PAD_CSI0_DAT4__GPIO5_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
	/* USB Power Lines */
	MX6_PAD_CSI0_DAT5__GPIO5_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_CSI0_DAT6__GPIO5_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_CSI0_DAT7__GPIO5_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
	#endif
};
#define STATION 0x01
const uchar igep_mac0 [6] = { 0x02, 0xBA, 0xD0, 0xBA, 0xD0, STATION };
uchar enetaddr[6];	
static int igep_eeprom_valid = 0;
static struct igep_mf_setup igep0046_eeprom_config;

/* I2C MUX */
#ifdef CONFIG_SYS_I2C
static struct i2c_pads_info i2c_pad_info1 =
{
	.scl =
	{
		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
		.gp = IMX_GPIO_NR(4, 12)
	},
	.sda =
	{
		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
		.gp = IMX_GPIO_NR(4, 13)
	}
};

static struct i2c_pads_info i2c_pad_info2 =
{
	.scl =
	{
		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | I2C_PAD,
		.gp = IMX_GPIO_NR(3, 17)
	},
	.sda =
	{
		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | I2C_PAD,
		.gp = IMX_GPIO_NR(3, 18)
	}
};
#endif

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}

#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET	0x800
#define UCTRL_PWR_POL		(1 << 9)

static iomux_v3_cfg_t const usb_otg_pads[] =
{
	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
};

#ifdef CONFIG_BASE0040
static void reset_audio(void)
{
	/* Audio Reset */
	gpio_direction_output(IMX_GPIO_NR(4, 10), 0);
	mdelay(5);
}

static void reset_usb_hub(void)
{
	/* Activate USB_PWRx */
	gpio_direction_output(IMX_GPIO_NR(5, 23), 1);
	gpio_direction_output(IMX_GPIO_NR(5, 24), 1);
	gpio_direction_output(IMX_GPIO_NR(5, 25), 1);
}
#endif

static void setup_usb(void)
{
	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
					 ARRAY_SIZE(usb_otg_pads));
}

int board_ehci_hcd_init(int port)
{
	u32 *usbnc_usb_ctrl;

	if (port > 1)
		return -EINVAL;

	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
				 port * 4);

	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);

	return 0;
}
#endif

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] =
{
	{USDHC1_BASE_ADDR},
	{USDHC3_BASE_ADDR},
};

#define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 1)

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base)
	{
	case USDHC1_BASE_ADDR:
		ret = !gpio_get_value(USDHC1_CD_GPIO);
		break;
	case USDHC3_BASE_ADDR:
		ret = 1; /* eMMC/uSDHC3 is always present */
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int ret;
	int i;
	/*
	 * According to the board_mmc_init() the following map is done:
	 * (U-boot device node)    (Physical Port)
	 * mmc0                    SD1 (external SDIO)
	 * mmc1                    SD3 (internal eMMC)
	 */
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
	{
		switch (i)
		{
		case 0:
			imx_iomux_v3_setup_multiple_pads(
				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
			gpio_direction_input(USDHC1_CD_GPIO);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(
				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			break;
		default:
			printf("Warning: you configured more USDHC controllers"
			       "(%d) then supported by the board (%d)\n",
			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
			return -EINVAL;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret)
			return ret;
	}

	return 0;
}
#endif

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
	gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset");
	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
	mdelay(15);
	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
	mdelay(10);
}

int board_phy_config(struct phy_device *phydev)
{
	unsigned short val;
	
	/* Marvel 88E1510 */
	if (phydev->phy_id == 0x1410dd1) {
		/*
		 * Page 3, Register 16: LED[2:0] Function Control Register
		 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
		 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
		 */
		phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
		val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
		val &= 0xff00;
		val |= 0x0017;
		phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
	}
	if (phydev->drv->config)
		phydev->drv->config(phydev);
	return 0;
}


static int get_mac_address (void)
{
	// MAC are 17 ASCII characters so we need to work it out a bit
	int i = 0;
	uchar ans[6];

	if(igep_eeprom_valid){
		for (i = 0; i < 6; i++){
		ans[i] = parse_char(igep0046_eeprom_config.bmac0[(i*3)]) * 0x10 + parse_char(igep0046_eeprom_config.bmac0[((i*3)+1)]);
		}
		memcpy(enetaddr, ans, 6);
		//memcpy(enetaddr, igep_mac0, 6);	
	}else{
		memcpy(enetaddr, igep_mac0, 6);
	}
	return eth_setenv_enetaddr("ethaddr", enetaddr);
}

int board_eth_init(bd_t *bis)
{
	get_mac_address();
	setup_iomux_enet();
#ifdef CONFIG_FEC_MXC
	cpu_eth_init(bis);
#endif
	return 0;
}

int checkboard(void)
{
	return 0;
}

int board_early_init_f(void)
{
	setup_iomux_uart();

	imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));

	/* configure LEDS - SPL = 1 YELLOW */
	gpio_direction_output(GPIO_LED_RED1, 1);
	gpio_direction_output(GPIO_LED_GREEN1, 1);
	gpio_direction_output(GPIO_LED_RED2, 0);
	gpio_direction_output(GPIO_LED_GREEN2, 0);
	return 0;
}

int board_init(void)
{

	/* configure LEDS - UBOOT = 2 YELLOW */
	gpio_direction_output(GPIO_LED_RED1, 1);
	gpio_direction_output(GPIO_LED_GREEN1, 1);
	gpio_direction_output(GPIO_LED_RED2, 1);
	gpio_direction_output(GPIO_LED_GREEN2, 1);

#ifdef CONFIG_BASE0040
	reset_audio();
#endif

#ifdef CONFIG_SYS_I2C
	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	mdelay(1);
#endif

#ifdef CONFIG_BASE0040
	reset_usb_hub();
#endif

#ifdef CONFIG_USB_EHCI_MX6
	setup_usb();
#endif

	return 0;	
}

static inline unsigned int pcb_version(void)
{
	unsigned int pcb_version_bit0, pcb_version_bit1,
		pcb_version_bit2, pcb_version_bit3;

	pcb_version_bit0 = gpio_get_value(PCB_CFG_0);
	pcb_version_bit1 = gpio_get_value(PCB_CFG_1);
	pcb_version_bit2 = gpio_get_value(PCB_CFG_2);
	pcb_version_bit3 = gpio_get_value(PCB_CFG_3);

	if (pcb_version_bit0 && pcb_version_bit1 \
		&& pcb_version_bit2 && pcb_version_bit3)
		/* RA revision: 0b1111*/
		return PCB_REV_A;
	else if (!(pcb_version_bit0 || pcb_version_bit1 \
		|| pcb_version_bit2 || pcb_version_bit3))
		/* RB revision: 0b0000*/
		return PCB_REV_B;
	else if (!(!(pcb_version_bit0) || pcb_version_bit1 \
		|| pcb_version_bit2 || pcb_version_bit3))
		/* RC revision: 0b0001*/
		return PCB_REV_C;
	else if (!(pcb_version_bit0 || pcb_version_bit1 \
		|| pcb_version_bit2 || !(pcb_version_bit3)))
		/* RD10 revision: 0b1000*/
		return PCB_REV_D10;
	else
		return 0;
}

int board_late_init(void)
{	

	u32 crc_value = 0;
	u32 crc_save_value;

    if(check_eeprom() != 0){
	printf("EEPROM: not found\n");
    }else{
		/* Read configuration from eeprom */
		if(eeprom46_read_setup(0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup)))
	  		printf("EEPROM: read fail\n");	
		/* Verify crc32 */

	  	printf("EEPROM: read %d bytes \n", sizeof(struct igep_mf_setup));
	  	printf("---------------------------- |!| IGEP STRUCT |!| ----------------------------\n");
  		printf("magic_id: 0x%x \n", igep0046_eeprom_config.magic_id);
  		printf("crc32: 0x%x \n", igep0046_eeprom_config.crc32);
  		printf("board_uuid: %.36s \n", igep0046_eeprom_config.board_uuid);
  		printf("board_pid: %.16s \n", igep0046_eeprom_config.board_pid);
  		printf("model: %.8s \n", igep0046_eeprom_config.model);
  		printf("variant: %.9s \n", igep0046_eeprom_config.variant);
		printf("manf_of: %.6s \n", igep0046_eeprom_config.manf_of);
  		printf("manf_timestamp: %.19s \n", igep0046_eeprom_config.manf_timestamp);
		printf("bmac0: %.17s \n", igep0046_eeprom_config.bmac0);
  		printf("bmac1: %.17s \n", igep0046_eeprom_config.bmac1);
	  	printf("-----------------------------------------------------------------------------\n");


	   	crc_save_value = igep0046_eeprom_config.crc32;
	   	igep0046_eeprom_config.crc32 = 0;
	   	crc_value = crc32(0, (const unsigned char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup));
  		printf("crc32 calculated: 0x%x \n", crc_value);
		if(crc_save_value != crc_value){
       		printf("EEPROM: CRC32 failed. Loading default MAC\n");				
		}else{
	    	printf("EEPROM: CRC32 OK! Loading MAC from eeprom\n");	       		
	  		igep_eeprom_valid = 1;
		}
	}

	checkboard();
	switch (pcb_version()) {
		case PCB_REV_A:
			puts("Board: MX6-IGEP0046 Rev A\n");
	#ifdef CONFIG_MX6Q
			setenv("fdt_file", "imx6q-igep-base0040ra1.dtb");
	#elif CONFIG_MX6DL
			setenv("fdt_file", "imx6dl-igep-base0040ra1.dtb");
	#endif
			break;
		case PCB_REV_B:
			puts("Board: MX6-IGEP0046 Rev B\n");
	#ifdef CONFIG_MX6Q
			setenv("fdt_file", "imx6q-igep-base0040rb2.dtb");
	#elif CONFIG_MX6DL
			setenv("fdt_file", "imx6dl-igep-base0040rb2.dtb");
	#endif
			break;
		case PCB_REV_C:
			puts("Board: MX6-IGEP0046 Rev C/D\n");
	#ifdef CONFIG_MX6Q
			setenv("fdt_file", "imx6q-igep-base0040rc2.dtb");
	#elif CONFIG_MX6DL
			setenv("fdt_file", "imx6dl-igep-base0040rc2.dtb");
	#endif
			break;
		case PCB_REV_D10:
			puts("Board: MX6-IGEP0046 Rev D10\n");
	#ifdef CONFIG_MX6Q
			setenv("fdt_file", "imx6q-igep-base0040rd102.dtb");
	#elif CONFIG_MX6DL
			setenv("fdt_file", "imx6dl-igep-base0040rd102.dtb");
	#endif
			break;
		default:
			puts("Board: ERROR unknown PCB revision\n");
			setenv("fdt_file", "");
			break;
	}
	return 0;
}

#ifdef CONFIG_LDO_BYPASS_CHECK
/* TODO, use external pmic, for now always ldo_enable */
void ldo_mode_set(int ldo_bypass)
{
	return;
}
#endif

#ifdef CONFIG_POWER
int power_init_board(void)
{
#ifdef CONFIG_SYS_I2C 
	struct pmic *p;
	unsigned int reg, ret;

	p = pfuze_common_init(I2C_PMIC);
	if (!p)
		return -ENODEV;

	ret = pfuze_mode_init(p, APS_PFM);
	if (ret < 0)
		return ret;

	/* Increase VGEN5 from 2.8 to 3V */
	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
	reg &= ~LDO_VOL_MASK;
	reg |= LDOB_3_00V;
	pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);

	/* Decrease VGEN6 from 3.3 to 2.5V */
	pmic_reg_read(p, PFUZE100_VGEN6VOL, &reg);
	reg &= ~LDO_VOL_MASK;
	reg |= LDOB_2_50V;
	pmic_reg_write(p, PFUZE100_VGEN6VOL, reg);
#endif
	return 0;
}
#endif


#ifdef CONFIG_RESET_PHY_R
void mv_phy_88e1510_init(char *name)
{
	u16 val;
	u16 devadr;

	if (miiphy_set_current_dev(name))
		return;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
		printf("Err..%s could not read PHY dev address\n",
			__FUNCTION__);
		return;
	}

	/*
	* Page 2 Register 24: RGMII Output Impedance Calibration Override
	* VDDO Level R24_2.13: 1; 2.5V used
	*/
	miiphy_write(name, 0, 22, 2);
	miiphy_read(name, 0, 24, &val);
	val |= 0x2000;
	miiphy_write(name, 0, 24, val);

	/*
	* Page 0 Register 9: 1000BASE-T Control Register
	* 1000BASE-T Full-Duplex R0_9.8: 0 Do not advertise
	* 1000BASE-T Half-Duplex R0_9.7: 0 Do not advertise
	*/
	miiphy_write(name, 0, 22, 0);
	miiphy_read(name, 0, 9, &val);
	val = 0x0000;
	miiphy_write(name, 0, 9, val);

	/*
	* Page 0 Register 0: Copper Control Register
	* Copper Reset R0_0.15: 1; PHY Software reset
	* Auto-Negotiation Enable R0_0.12: 1; Enable Auto-Negotiation Process
	*/
	miiphy_write(name, 0, 22, 0);
	miiphy_read(name, 0, 0, &val);
	val |= 0x9000;
	miiphy_write(name, 0, 0, val);
	miiphy_write(name, 0, 22, 0);

	printf("88E1510 Initialized on %s\n", name);
}

void reset_phy(void)
{
	/* configure and initialize */
	mv_phy_88e1510_init("FEC");
}
#endif /* CONFIG_RESET_PHY_R */

/* Add SPL Support if we want to build u-boot with SPL for i.MX6 */

#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#include <libfdt.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "pfuze.h"

#define IMX6DQ_DRIVE_STRENGTH		0x30
#define IMX6SDL_DRIVE_STRENGTH		0x28

/* configure MX6Q/DUAL mmdc DDR io registers */

#ifdef CONFIG_MX6Q
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
};

/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
};

/* DDR 64bit 2GB */
static struct mx6_ddr_sysinfo mem_q = {
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 0,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
	.p0_mpwldectrl0 = 0x00530056,
	.p0_mpwldectrl1 = 0x00440053,
	.p1_mpwldectrl0 = 0x002B002B,
	.p1_mpwldectrl1 = 0x0028003F,
	.p0_mpdgctrl0 = 0x021C021C,
	.p0_mpdgctrl1 = 0x02140214,
	.p1_mpdgctrl0 = 0x0178017C,
	.p1_mpdgctrl1 = 0x016C0170,
	.p0_mprddlctl = 0x46484C48,
	.p1_mprddlctl = 0x42424842,
	.p0_mpwrdlctl = 0x3434302E,
	.p1_mpwrdlctl = 0x3A303830,
};
#endif

static struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
};

/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
};

static struct mx6_ddr_sysinfo mem_dl = {
	.dsize		= 2, /* MMDCx_MDCTL */
	.cs1_mirror	= 0, /* MMDCx_MDMISC */
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32, /* MMDCx_MDCTL */
	.ncs		= 1, /* MMDCx_MDCTL */
	.bi_on		= 1, /* MMDCx_MDMISC */
	.rtt_nom	= 1, /* MMDCx_MPODTCTRL */
	.rtt_wr		= 0, /* - */
	.ralat		= 5, /* MMDCx_MDMISC */
	.walat		= 0, /* MMDCx_MDMISC */
	.mif3_mode	= 3, /* MMDCx_MDMISC */
	.rst_to_cke	= 0x23, /* MMDCx_MDOR */
	.sde_to_rst	= 0x10, /* MMDCx_MDOR */
};

static struct mx6_ddr_sysinfo mem_s = {
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 0,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

/* K484G1646D-8MK0 (4Gb density) */
static struct mx6_ddr3_cfg k484g1646d_8mk0 = {
	.mem_speed = 1600,
	.density = 4,
	.width = 16,
	.banks = 8,
	.rowaddr = 15,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

static struct mx6_mmdc_calibration mx6dl_2g_mmdc_calib = {
	.p0_mpwldectrl0 = 0x00530056,
	.p0_mpwldectrl1 = 0x00440053,
	.p1_mpwldectrl0 = 0x002B002B,
	.p1_mpwldectrl1 = 0x0028003F,
	.p0_mpdgctrl0 = 0x021C021C,
	.p0_mpdgctrl1 = 0x02140214,
	.p1_mpdgctrl0 = 0x0178017C,
	.p1_mpdgctrl1 = 0x016C0170,
	.p0_mprddlctl = 0x46484C48,
	.p1_mprddlctl = 0x42424842,
	.p0_mpwrdlctl = 0x3434302E,
	.p1_mpwrdlctl = 0x3A303830,
};

static void spl_dram_init(void)
{

/* TO DO: IMPLEMENT CASE FOR EACH MEMORY DEVICE AND MEMORY DENSITY CONFIGURATION (1,2,4 GB) */

	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_s, &mx6dl_2g_mmdc_calib, &k484g1646d_8mk0);
	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_dl, &mx6dl_2g_mmdc_calib, &k484g1646d_8mk0);
	}
#ifdef CONFIG_MX6Q
	else if (is_cpu_type(MXC_CPU_MX6Q)) {
		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
		mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &k484g1646d_8mk0);
	}
#endif
	udelay(100);
}

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC03, &ccm->CCGR1);
	writel(0x0FFFC000, &ccm->CCGR2);
	writel(0x3FF00000, &ccm->CCGR3);
	writel(0x00FFF300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
}

static void gpr_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	if (is_mx6dqp()) {
		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
		writel(0x007F007F, &iomux->gpr[6]);
		writel(0x007F007F, &iomux->gpr[7]);
	} else {
		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
		writel(0x007F007F, &iomux->gpr[6]);
		writel(0x007F007F, &iomux->gpr[7]);
	}
}
/*
 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
 * - no variable global data is available
 */
void board_init_f(ulong dummy)
{

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	/* setup clock gating */
	ccgr_init();

	/* setup general purpose register */
	gpr_init();

	/* iomux and setup of UART and leds */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* Silent Console */
	gd->flags |= GD_FLG_SILENT;
	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();

	/* Get RAM size */
	dram_init();

	/* Initialize SDRAM banks - fdt_fixup*/
	dram_init_banksize();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);
	
	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}

/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* its our chance to print info about boot device */
void spl_board_init(void)
{

	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
	u32 boot_device = spl_boot_device();

	switch (boot_device) {
	case BOOT_DEVICE_MMC1:
		puts("Booting from MMC\n");
		break;
	case BOOT_DEVICE_NAND:
		puts("Booting from NAND\n");
		break;
	case BOOT_DEVICE_SATA:
		puts("Booting from SATA\n");
		break;
	default:
		puts("Unknown boot device\n");
	}
	
	/* Minimal init sequence for pmic setup of igep imx6 boards */
	#ifdef CONFIG_BASE0040
	reset_audio();
	#endif

	#ifdef CONFIG_SYS_I2C
	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	mdelay(1);
	#endif

	/* PMIC init */
	power_init_board();
}

#ifdef CONFIG_SPL_OS_BOOT
/* return 1 if we wish to boot to uboot vs os (falcon mode) */
int spl_start_uboot(void)
{
	return 0;
}

void spl_board_prepare_for_linux(void)
{
	/* Fill here igep i.MX6 specific code to set up board just before
	Jumping to Linux in SPL Falcon Mode */

#ifdef CONFIG_FALCON_RAMDISK

	#define CONFIG_RAMDISK_START	0x5000
	#define CONFIG_RAMDISK_SIZE		22 * 1024 * 1024
	#define CONFIG_RAMDISK_ARG_DDR	0x14000000
	#define CONFIG_RAMDISK_MMC_DEV 	0

	u32 initrd_size_sectors;
	ulong start;
	ulong size;
	int dev;
	struct mmc *mmc;

	/* We need to re-fill mmc structure for blk_dread to work with mmc */
	dev = CONFIG_RAMDISK_MMC_DEV;
	mmc = find_mmc_device(dev);
	if (!mmc) {
		puts("error MMC init\n");
	}

	mmc_init(mmc);

	/* We expect initrd.img in offset RAMDISK_ARG_DDR of device x */
	start = CONFIG_RAMDISK_START;
	/* We exect initrd.img to be size of RAMDISK_SIZE */
	size = CONFIG_RAMDISK_SIZE;

	/* convert size to sectors - round up */
	initrd_size_sectors = (size / 512);

	/* Load initrd.img from RAW MMC starting at start with size size into 0x14000000 ADDR */
	blk_dread(mmc_get_blk_desc(mmc), start, initrd_size_sectors,
			  (void *)CONFIG_RAMDISK_ARG_DDR);

#endif
}

#endif
#endif