1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
|
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* (C) Copyright 2004
* ARM Ltd.
* Philippe Robin, <philippe.robin@arm.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
void flash__init (void);
void ether__init (void);
void peripheral_power_enable (void);
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);
}
#endif
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* arch number of Integrator Board */
gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
gd->flags = 0;
#ifdef CONFIG_CM_REMAP
extern void cm_remap(void);
cm_remap(); /* remaps writeable memory to 0x00000000 */
#endif
icache_enable ();
flash__init ();
ether__init ();
return 0;
}
int misc_init_r (void)
{
setenv("verify", "n");
return (0);
}
/******************************
Routine:
Description:
******************************/
void flash__init (void)
{
}
/*************************************************************
Routine:ether__init
Description: take the Ethernet controller out of reset and wait
for the EEPROM load to complete.
*************************************************************/
void ether__init (void)
{
}
/******************************
Routine:
Description:
******************************/
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
unsigned long cm_reg_sdram;
unsigned long sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
/* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
* 0xXXXXXXbbb001bb 32 MB
* 0xXXXXXXbbb010bb 64 MB
* 0xXXXXXXbbb011bb 128 MB
* 0xXXXXXXbbb100bb 256 MB
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
}
#endif /* CM_SPD_DETECT */
return 0;
}
/* The Integrator/CP timer1 is clocked at 1MHz
* can be divided by 16 or 256
* and can be set up as a 32-bit timer
*/
/* U-Boot expects a 32 bit timer, running at CFG_HZ */
/* Keep total timer count to avoid losing decrements < div_timer */
static unsigned long long total_count = 0;
static unsigned long long lastdec; /* Timer reading at last call */
static unsigned long long div_clock = 1; /* Divisor applied to timer clock */
static unsigned long long div_timer = 1; /* Divisor to convert timer reading
* change to U-Boot ticks
*/
/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
static ulong timestamp; /* U-Boot ticks since startup */
#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF)
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
* - unless otherwise stated
*/
/* starts up a counter
* - the Integrator/CP timer can be set up to issue an interrupt */
int interrupt_init (void)
{
/* Load timer with initial value */
*(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
/* Set timer to be
* enabled 1
* periodic 1
* no interrupts 0
* X 0
* divider 1 00 == less rounding error
* 32 bit 1
* wrapping 0
*/
*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x000000C2;
/* init the timestamp */
total_count = 0ULL;
reset_timer_masked();
div_timer = (unsigned long long)(CFG_HZ_CLOCK / CFG_HZ);
div_timer /= div_clock;
return (0);
}
/*
* timer without interrupts
*/
void reset_timer (void)
{
reset_timer_masked ();
}
ulong get_timer (ulong base_ticks)
{
return get_timer_masked () - base_ticks;
}
void set_timer (ulong ticks)
{
timestamp = ticks;
total_count = (unsigned long long)ticks * div_timer;
}
/* delay usec useconds */
void udelay (unsigned long usec)
{
ulong tmo, tmp;
/* Convert to U-Boot ticks */
tmo = usec * CFG_HZ;
tmo /= (1000000L);
tmp = get_timer_masked(); /* get current timestamp */
tmo += tmp; /* form target timestamp */
while (get_timer_masked () < tmo)/* loop till event */
{
/*NOP*/;
}
}
void reset_timer_masked (void)
{
/* capure current decrementer value */
lastdec = (unsigned long long)READ_TIMER;
/* start "advancing" time stamp from 0 */
timestamp = 0L;
}
/* converts the timer reading to U-Boot ticks */
/* the timestamp is the number of ticks since reset */
ulong get_timer_masked (void)
{
/* get current count */
unsigned long long now = (unsigned long long)READ_TIMER;
if(now > lastdec)
{
/* Must have wrapped */
total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
} else {
total_count += lastdec - now;
}
lastdec = now;
timestamp = (ulong)(total_count/div_timer);
return timestamp;
}
/* waits specified delay value and resets timestamp */
void udelay_masked (unsigned long usec)
{
udelay(usec);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return (unsigned long long)get_timer(0);
}
/*
* Return the timebase clock frequency
* i.e. how often the timer decrements
*/
ulong get_tbclk (void)
{
return (ulong)(((unsigned long long)CFG_HZ_CLOCK)/div_clock);
}
|