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/*
* Copyright 2007-2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <netdev.h>
#include "../common/ngpixis.h"
#include "../common/sgmii_riser.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
#ifdef CONFIG_MMC
ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr,
(MPC85xx_PMUXCR_SDHC_CD |
MPC85xx_PMUXCR_SDHC_WP));
#endif
return 0;
}
int checkboard(void)
{
u8 sw;
printf("Board: P2020DS Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
if (sw < 0x8)
/* The lower two bits are the actual vbank number */
printf("vBank: %d\n", sw & 3);
else
puts("Promjet\n");
return 0;
}
#if !defined(CONFIG_DDR_SPD)
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram(void)
{
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
if (!strcmp("performance", getenv("perf_mode"))) {
/* Performance Mode Values */
ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
asm("sync;isync");
udelay(500);
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
} else {
/* Stable Mode Values */
ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
/* ECC will be assumed in stable mode */
ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
ddr->err_sbe = CONFIG_SYS_DDR_SBE;
asm("sync;isync");
udelay(500);
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
}
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
d_init = 1;
debug("DDR - 1st controller: memory initializing\n");
/*
* Poll until memory is initialized.
* 512 Meg at 400 might hit this 200 times or so.
*/
while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
udelay(1000);
debug("DDR: memory initialized\n\n");
asm("sync; isync");
udelay(500);
#endif
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
LAW_TRGT_IF_DDR) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
};
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif
#ifdef CONFIG_PCI
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
return 0;
}
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
if (is_serdes_configured(SGMII_TSEC2)) {
puts("eTSEC2 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
if (is_serdes_configured(SGMII_TSEC3)) {
puts("eTSEC3 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_init(tsec_info, num);
#endif
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
return pci_eth_init(bis);
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
}
#endif
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