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|
/*
* Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
#include <lcd.h>
#include <mxc_epdc_fb.h>
#endif
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_SYS_I2C_MXC
#include <i2c.h>
#include <asm/imx-common/mxc_i2c.h>
#endif
#ifdef CONFIG_CMD_SATA
#include <asm/imx-common/sata.h>
#endif
#ifdef CONFIG_FASTBOOT
#include <fastboot.h>
#ifdef CONFIG_ANDROID_RECOVERY
#include <recovery.h>
#endif
#endif /*CONFIG_FASTBOOT*/
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C2 Camera, MIPI, pfuze */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
#endif
int dram_init(void)
{
gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
return 0;
}
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8031 PHY Reset */
MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}
iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#ifdef CONFIG_SYS_USE_SPINOR
iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_spinor(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
gpio_direction_output(IMX_GPIO_NR(4, 9), 0);
}
#endif
iomux_v3_cfg_t const pcie_pads[] = {
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
};
static void setup_pcie(void)
{
imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
}
iomux_v3_cfg_t const di0_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
};
#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
static iomux_v3_cfg_t const epdc_enable_pads[] = {
MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
};
static iomux_v3_cfg_t const epdc_disable_pads[] = {
MX6_PAD_EIM_A16__GPIO2_IO22,
MX6_PAD_EIM_DA10__GPIO3_IO10,
MX6_PAD_EIM_DA12__GPIO3_IO12,
MX6_PAD_EIM_DA11__GPIO3_IO11,
MX6_PAD_EIM_LBA__GPIO2_IO27,
MX6_PAD_EIM_EB2__GPIO2_IO30,
MX6_PAD_EIM_CS0__GPIO2_IO23,
MX6_PAD_EIM_RW__GPIO2_IO26,
MX6_PAD_EIM_A21__GPIO2_IO17,
MX6_PAD_EIM_A22__GPIO2_IO16,
MX6_PAD_EIM_A23__GPIO6_IO06,
MX6_PAD_EIM_A24__GPIO5_IO04,
MX6_PAD_EIM_D31__GPIO3_IO31,
MX6_PAD_EIM_D27__GPIO3_IO27,
MX6_PAD_EIM_DA1__GPIO3_IO01,
MX6_PAD_EIM_EB1__GPIO2_IO29,
MX6_PAD_EIM_DA2__GPIO3_IO02,
MX6_PAD_EIM_DA4__GPIO3_IO04,
MX6_PAD_EIM_DA5__GPIO3_IO05,
MX6_PAD_EIM_DA6__GPIO3_IO06,
};
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_SYS_I2C_MXC
static int setup_pmic_voltages(void)
{
unsigned char value, rev_id = 0 ;
i2c_set_bus_num(1);
if (!i2c_probe(0x8)) {
if (i2c_read(0x8, 0, 1, &value, 1)) {
printf("Read device ID error!\n");
return -1;
}
if (i2c_read(0x8, 3, 1, &rev_id, 1)) {
printf("Read Rev ID error!\n");
return -1;
}
printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id);
/*For camera streaks issue,swap VGEN5 and VGEN3 to power camera.
*sperate VDDHIGH_IN and camera 2.8V power supply, after switch:
*VGEN5 for VDDHIGH_IN and increase to 3V to align with datasheet
*VGEN3 for camera 2.8V power supply
*/
/*increase VGEN3 from 2.5 to 2.8V*/
if (i2c_read(0x8, 0x6e, 1, &value, 1)) {
printf("Read VGEN3 error!\n");
return -1;
}
value &= ~0xf;
value |= 0xa;
if (i2c_write(0x8, 0x6e, 1, &value, 1)) {
printf("Set VGEN3 error!\n");
return -1;
}
/*increase VGEN5 from 2.8 to 3V*/
if (i2c_read(0x8, 0x70, 1, &value, 1)) {
printf("Read VGEN5 error!\n");
return -1;
}
value &= ~0xf;
value |= 0xc;
if (i2c_write(0x8, 0x70, 1, &value, 1)) {
printf("Set VGEN5 error!\n");
return -1;
}
/* set SW1AB staby volatage 0.975V*/
if (i2c_read(0x8, 0x21, 1, &value, 1)) {
printf("Read SW1ABSTBY error!\n");
return -1;
}
value &= ~0x3f;
value |= 0x1b;
if (i2c_write(0x8, 0x21, 1, &value, 1)) {
printf("Set SW1ABSTBY error!\n");
return -1;
}
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
if (i2c_read(0x8, 0x24, 1, &value, 1)) {
printf("Read SW1ABSTBY error!\n");
return -1;
}
value &= ~0xc0;
value |= 0x40;
if (i2c_write(0x8, 0x24, 1, &value, 1)) {
printf("Set SW1ABSTBY error!\n");
return -1;
}
/* set SW1C staby volatage 0.975V*/
if (i2c_read(0x8, 0x2f, 1, &value, 1)) {
printf("Read SW1CSTBY error!\n");
return -1;
}
value &= ~0x3f;
value |= 0x1b;
if (i2c_write(0x8, 0x2f, 1, &value, 1)) {
printf("Set SW1CSTBY error!\n");
return -1;
}
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
if (i2c_read(0x8, 0x32, 1, &value, 1)) {
printf("Read SW1ABSTBY error!\n");
return -1;
}
value &= ~0xc0;
value |= 0x40;
if (i2c_write(0x8, 0x32, 1, &value, 1)) {
printf("Set SW1ABSTBY error!\n");
return -1;
}
}
return 0;
}
#ifdef CONFIG_LDO_BYPASS_CHECK
void ldo_mode_set(int ldo_bypass)
{
unsigned char value;
/* increase VDDARM/VDDSOC to support 1.2G chip */
if (check_1_2G()) {
ldo_bypass = 0; /* ldo_enable on 1.2G chip */
printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
/* increase VDDARM to 1.425V */
if (i2c_read(0x8, 0x20, 1, &value, 1)) {
printf("Read SW1AB error!\n");
return;
}
value &= ~0x3f;
value |= 0x2d;
if (i2c_write(0x8, 0x20, 1, &value, 1)) {
printf("Set SW1AB error!\n");
return;
}
/* increase VDDSOC to 1.425V */
if (i2c_read(0x8, 0x2e, 1, &value, 1)) {
printf("Read SW1C error!\n");
return;
}
value &= ~0x3f;
value |= 0x2d;
if (i2c_write(0x8, 0x2e, 1, &value, 1)) {
printf("Set SW1C error!\n");
return;
}
}
/* switch to ldo_bypass mode , boot on 800Mhz */
if (ldo_bypass) {
/* decrease VDDARM to 1.175V */
if (i2c_read(0x8, 0x20, 1, &value, 1)) {
printf("Read SW1AB error!\n");
return;
}
value &= ~0x3f;
value |= 0x23;
if (i2c_write(0x8, 0x20, 1, &value, 1)) {
printf("Set SW1AB error!\n");
return;
}
/* increase VDDSOC to 1.175V */
if (i2c_read(0x8, 0x2e, 1, &value, 1)) {
printf("Read SW1C error!\n");
return;
}
value &= ~0x3f;
value |= 0x23;
if (i2c_write(0x8, 0x2e, 1, &value, 1)) {
printf("Set SW1C error!\n");
return;
}
set_anatop_bypass();
printf("switch to ldo_bypass mode!\n");
}
}
#endif
#endif
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
int mmc_get_env_devno(void)
{
u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
u32 dev_no;
/* BOOT_CFG2[3] and BOOT_CFG2[4] */
dev_no = (soc_sbmr & 0x00001800) >> 11;
/* need ubstract 1 to map to the mmc device id
* see the comments in board_mmc_init function
*/
dev_no--;
return dev_no;
}
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int i;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 SD2
* mmc1 SD3
* mmc2 eMMC
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
}
return status;
}
void board_late_mmc_env_init(void)
{
char cmd[32];
u32 dev_no = mmc_get_env_devno();
setenv_ulong("mmcdev", dev_no);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#endif
#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
#ifdef CONFIG_SPLASH_SCREEN
extern int mmc_get_env_devno(void);
int setup_splash_img(void)
{
#ifdef CONFIG_SPLASH_IS_IN_MMC
int mmc_dev = mmc_get_env_devno();
ulong offset = CONFIG_SPLASH_IMG_OFFSET;
ulong size = CONFIG_SPLASH_IMG_SIZE;
ulong addr = 0;
char *s = NULL;
struct mmc *mmc = find_mmc_device(mmc_dev);
uint blk_start, blk_cnt, n;
s = getenv("splashimage");
if (NULL == s) {
puts("env splashimage not found!\n");
return -1;
}
addr = simple_strtoul(s, NULL, 16);
if (!mmc) {
printf("MMC Device %d not found\n", mmc_dev);
return -1;
}
if (mmc_init(mmc)) {
puts("MMC init failed\n");
return -1;
}
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
n = mmc->block_dev.block_read(mmc_dev, blk_start,
blk_cnt, (u_char *)addr);
flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
return (n == blk_cnt) ? 0 : -1;
#endif
return 0;
}
#endif
vidinfo_t panel_info = {
.vl_refresh = 85,
.vl_col = 800,
.vl_row = 600,
.vl_pixclock = 26666667,
.vl_left_margin = 8,
.vl_right_margin = 100,
.vl_upper_margin = 4,
.vl_lower_margin = 8,
.vl_hsync = 4,
.vl_vsync = 1,
.vl_sync = 0,
.vl_mode = 0,
.vl_flag = 0,
.vl_bpix = 3,
.cmap = 0,
};
struct epdc_timing_params panel_timings = {
.vscan_holdoff = 4,
.sdoed_width = 10,
.sdoed_delay = 20,
.sdoez_width = 10,
.sdoez_delay = 20,
.gdclk_hp_offs = 419,
.gdsp_offs = 20,
.gdoe_offs = 0,
.gdclk_offs = 5,
.num_ce = 1,
};
static void setup_epdc_power(void)
{
/* Setup epdc voltage */
/* EIM_A17 - GPIO2[21] for PWR_GOOD status */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as input */
gpio_direction_input(IMX_GPIO_NR(2, 21));
/* EIM_D17 - GPIO3[17] for VCOM control */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(2, 20), 1);
}
int setup_waveform_file(void)
{
#ifdef CONFIG_WAVEFORM_FILE_IN_MMC
int mmc_dev = mmc_get_env_devno();
ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
ulong size = CONFIG_WAVEFORM_FILE_SIZE;
ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
struct mmc *mmc = find_mmc_device(mmc_dev);
uint blk_start, blk_cnt, n;
if (!mmc) {
printf("MMC Device %d not found\n", mmc_dev);
return -1;
}
if (mmc_init(mmc)) {
puts("MMC init failed\n");
return -1;
}
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
n = mmc->block_dev.block_read(mmc_dev, blk_start,
blk_cnt, (u_char *)addr);
flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
return (n == blk_cnt) ? 0 : -1;
#else
return -1;
#endif
}
static void epdc_enable_pins(void)
{
/* epdc iomux settings */
imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
ARRAY_SIZE(epdc_enable_pads));
}
static void epdc_disable_pins(void)
{
/* Configure MUX settings for EPDC pins to GPIO */
imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
ARRAY_SIZE(epdc_disable_pads));
}
static void setup_epdc(void)
{
unsigned int reg;
struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/*** epdc Maxim PMIC settings ***/
/* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* EPDC VCOM0 - GPIO3[17] for VCOM control */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/*** Set pixel clock rates for EPDC ***/
/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */
reg = readl(&ccm_regs->cscdr3);
reg &= ~0x7C000;
reg |= (1 << 16) | (1 << 14);
writel(reg, &ccm_regs->cscdr3);
/* EPDC AXI clk enable */
reg = readl(&ccm_regs->CCGR3);
reg |= 0x00C0;
writel(reg, &ccm_regs->CCGR3);
/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */
reg = readl(&ccm_regs->cscdr2);
reg &= ~0x3FE00;
reg |= (2 << 15) | (5 << 12);
writel(reg, &ccm_regs->cscdr2);
/* PLL5 enable (defaults to 650) */
reg = readl(ANATOP_BASE_ADDR + ANATOP_PLL_VIDEO);
reg &= ~((1 << 16) | (1 << 12));
reg |= (1 << 13);
writel(reg, ANATOP_BASE_ADDR + ANATOP_PLL_VIDEO);
/* EPDC PIX clk enable */
reg = readl(&ccm_regs->CCGR3);
reg |= 0x0C00;
writel(reg, &ccm_regs->CCGR3);
panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
panel_info.epdc_data.wv_modes.mode_init = 0;
panel_info.epdc_data.wv_modes.mode_du = 1;
panel_info.epdc_data.wv_modes.mode_gc4 = 3;
panel_info.epdc_data.wv_modes.mode_gc8 = 2;
panel_info.epdc_data.wv_modes.mode_gc16 = 2;
panel_info.epdc_data.wv_modes.mode_gc32 = 2;
panel_info.epdc_data.epdc_timings = panel_timings;
setup_epdc_power();
/* Assign fb_base */
gd->fb_base = CONFIG_FB_BASE;
}
void epdc_power_on(void)
{
unsigned int reg;
struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
gpio_set_value(IMX_GPIO_NR(2, 20), 1);
udelay(1000);
/* Enable epdc signal pin */
epdc_enable_pins();
/* Set PMIC Wakeup to high - enable Display power */
gpio_set_value(IMX_GPIO_NR(3, 20), 1);
/* Wait for PWRGOOD == 1 */
while (1) {
reg = readl(&gpio_regs->gpio_psr);
if (!(reg & (1 << 21)))
break;
udelay(100);
}
/* Enable VCOM */
gpio_set_value(IMX_GPIO_NR(3, 17), 1);
udelay(500);
}
void epdc_power_off(void)
{
/* Set PMIC Wakeup to low - disable Display power */
gpio_set_value(IMX_GPIO_NR(3, 20), 0);
/* Disable VCOM */
gpio_set_value(IMX_GPIO_NR(3, 17), 0);
epdc_disable_pins();
/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
gpio_set_value(IMX_GPIO_NR(2, 20), 0);
}
#endif
int mx6_rgmii_rework(struct phy_device *phydev)
{
unsigned short val;
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
val &= 0xffe3;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
/* introduce tx clock delay */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
val |= 0x0100;
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
mx6_rgmii_rework(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#if defined(CONFIG_VIDEO_IPUV3)
struct display_info_t {
int bus;
int addr;
int pixfmt;
int (*detect)(struct display_info_t const *dev);
void (*enable)(struct display_info_t const *dev);
struct fb_videomode mode;
};
static void disable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg = readl(&iomux->gpr[2]);
reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
writel(reg, &iomux->gpr[2]);
}
static void do_enable_hdmi(struct display_info_t const *dev)
{
disable_lvds(dev);
imx_enable_hdmi_phy();
}
static struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB666,
.detect = NULL,
.enable = NULL,
.mode = {
.name = "Hannstar-XGA",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = NULL,
.enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39721,
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} } };
int board_video_skip(void)
{
int i;
int ret;
char const *panel = getenv("panel");
if (!panel) {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
struct display_info_t const *dev = displays+i;
if (dev->detect && dev->detect(dev)) {
panel = dev->mode.name;
printf("auto-detected panel %s\n", panel);
break;
}
}
if (!panel) {
panel = displays[0].mode.name;
printf("No panel detected: default to %s\n", panel);
i = 0;
}
} else {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
if (!strcmp(panel, displays[i].mode.name))
break;
}
}
if (i < ARRAY_SIZE(displays)) {
ret = ipuv3_fb_init(&displays[i].mode, 0,
displays[i].pixfmt);
if (!ret) {
if (displays[i].enable)
displays[i].enable(displays+i);
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,
displays[i].mode.yres);
} else
printf("LCD %s cannot be configured: %d\n",
displays[i].mode.name, ret);
} else {
printf("unsupported panel %s\n", panel);
return -EINVAL;
}
return 0;
}
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
enable_ipu_clock();
imx_setup_hdmi();
/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
writel(reg, &mxc_ccm->CCGR3);
/* set LDB0, LDB1 clk select to 011/011 */
reg = readl(&mxc_ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->cs2cdr);
reg = readl(&mxc_ccm->cscmr2);
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
writel(reg, &iomux->gpr[2]);
reg = readl(&iomux->gpr[3]);
reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
}
#endif /* CONFIG_VIDEO_IPUV3 */
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
setup_pcie();
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
#ifdef CONFIG_SYS_USE_SPINOR
setup_spinor();
#endif
#ifdef CONFIG_CMD_SATA
setup_sata();
#endif
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
setup_epdc();
#endif
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
/* 8 bit bus width */
{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
int ret = 0;
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(1, CONFIG_SYS_I2C_SPEED,
0x7f, &i2c_pad_info1);
ret = setup_pmic_voltages();
if (ret)
return -1;
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
return 0;
}
int checkboard(void)
{
puts("Board: MX6-SabreSD\n");
return 0;
}
#ifdef CONFIG_FASTBOOT
void board_fastboot_setup(void)
{
switch (get_boot_device()) {
#if defined(CONFIG_FASTBOOT_STORAGE_SATA)
case SATA_BOOT:
if (!getenv("fastboot_dev"))
setenv("fastboot_dev", "sata");
if (!getenv("bootcmd"))
setenv("bootcmd", "booti sata");
break;
#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
case SD2_BOOT:
case MMC2_BOOT:
if (!getenv("fastboot_dev"))
setenv("fastboot_dev", "mmc0");
if (!getenv("bootcmd"))
setenv("bootcmd", "booti mmc0");
break;
case SD3_BOOT:
case MMC3_BOOT:
if (!getenv("fastboot_dev"))
setenv("fastboot_dev", "mmc1");
if (!getenv("bootcmd"))
setenv("bootcmd", "booti mmc1");
break;
case MMC4_BOOT:
if (!getenv("fastboot_dev"))
setenv("fastboot_dev", "mmc2");
if (!getenv("bootcmd"))
setenv("bootcmd", "booti mmc2");
break;
#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
default:
printf("unsupported boot devices\n");
break;
}
}
#ifdef CONFIG_ANDROID_RECOVERY
#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
iomux_v3_cfg_t const recovery_key_pads[] = {
(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
int check_recovery_cmd_file(void)
{
int button_pressed = 0;
int recovery_mode = 0;
recovery_mode = recovery_check_and_clean_flag();
/* Check Recovery Combo Button press or not. */
imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
ARRAY_SIZE(recovery_key_pads));
gpio_direction_input(GPIO_VOL_DN_KEY);
if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
button_pressed = 1;
printf("Recovery key pressed\n");
}
return recovery_mode || button_pressed;
}
void board_recovery_setup(void)
{
int bootdev = get_boot_device();
switch (bootdev) {
#if defined(CONFIG_FASTBOOT_STORAGE_SATA)
case SATA_BOOT:
if (!getenv("bootcmd_android_recovery"))
setenv("bootcmd_android_recovery",
"booti sata recovery");
break;
#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
case SD2_BOOT:
case MMC2_BOOT:
if (!getenv("bootcmd_android_recovery"))
setenv("bootcmd_android_recovery",
"booti mmc0 recovery");
break;
case SD3_BOOT:
case MMC3_BOOT:
if (!getenv("bootcmd_android_recovery"))
setenv("bootcmd_android_recovery",
"booti mmc1 recovery");
break;
case MMC4_BOOT:
if (!getenv("bootcmd_android_recovery"))
setenv("bootcmd_android_recovery",
"booti mmc2 recovery");
break;
#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
default:
printf("Unsupported bootup device for recovery: dev: %d\n",
bootdev);
return;
}
printf("setup env for recovery..\n");
setenv("bootcmd", "run bootcmd_android_recovery");
}
#endif /*CONFIG_ANDROID_RECOVERY*/
#endif /*CONFIG_FASTBOOT*/
#ifdef CONFIG_IMX_UDC
iomux_v3_cfg_t const otg_udc_pads[] = {
(MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
void udc_pins_setting(void)
{
imx_iomux_v3_setup_multiple_pads(otg_udc_pads,
ARRAY_SIZE(otg_udc_pads));
/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/
mxc_iomux_set_gpr_register(1, 13, 1, 0);
}
#endif /*CONFIG_IMX_UDC*/
#ifdef CONFIG_USB_EHCI_MX6
iomux_v3_cfg_t const usb_otg_pads[] = {
MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const usb_hc1_pads[] = {
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int board_ehci_hcd_init(int port)
{
switch (port) {
case 0:
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));
/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/
mxc_iomux_set_gpr_register(1, 13, 1, 0);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
ARRAY_SIZE(usb_hc1_pads));
break;
default:
printf("MXC USB port %d not yet supported\n", port);
return 1;
}
return 0;
}
int board_ehci_power(int port, int on)
{
switch (port) {
case 0:
break;
case 1:
if (on)
gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
else
gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
break;
default:
printf("MXC USB port %d not yet supported\n", port);
return 1;
}
return 0;
}
#endif
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