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/*
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#ifdef CONFIG_MX6DQ_POP_LPDDR2
/* set ddr to 400Mhz */
DATA 4 0x020C4018 0x21324
DATA 4 0x020C4014 0x2018100
CHECK_BITS_CLR 4 0x020C4048 0x3F
DATA 4 0x020C4018 0x61324
DATA 4 0x020C4014 0x18900
CHECK_BITS_CLR 4 0x020C4048 0x3F
DATA 4 0x020C4018 0x60324
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff
// Switch PL301_FAST2 to DDR dual channel mapping
//DATA 4 0x00B00000 0x1
//=============================================================================
/// IOMUX
//=============================================================================
//DDR IO TYPE:
DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
//Control:
DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4 0x020e05a8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
DATA 4 0x020e05b0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
DATA 4 0x020e0524 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
DATA 4 0x020e051c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
DATA 4 0x020e0518 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
DATA 4 0x020e050c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
DATA 4 0x020e05b8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
DATA 4 0x020e05c0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
//Data:
DATA 4 0x020e0798 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS
DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS
DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS
DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS
DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS
DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS
DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron - POP Package
// Device Part Number: MT42L128M64D2LL-25WT
// Clock Freq.: 400MHz
// Density per CS in Gb: 4
// Chip Selects used: 1
// Number of channels 2
// Density per channel (Gb) 4
// Total DRAM density (Gb) 8
// Number of Banks: 8
// Row address: 14
// Column address: 10
// Data bus width 32
//=============================================================================
// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
DATA 4 0x021b001c 0x00008000 // Chan 0
DATA 4 0x021b401c 0x00008000 // Chan 1
DATA 4 0x021b085c 0x1b5f0109 //LPDDR2 ZQ params
DATA 4 0x021b485c 0x1b5f0109 //LPDDR2 ZQ params
//=============================================================================
// Calibration setup.
//
//=============================================================================
DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable one time ZQ calibration
DATA 4 0x021b4800 0xa1380003 // DDR_PHY_P1_MPZQHWCTRL
DATA 4 0x021b0890 0x00400000 //ca bus abs delay
DATA 4 0x021b4890 0x00400000 //ca bus abs delay
//DATA 4 0x021b48bc0x00055555 // DDR_PHY_P1_MPWRCADL
DATA 4 0x021b08b8 0x00000800 //frc_msr.
DATA 4 0x021b48b8 0x00000800 //frc_msr.
// read delays, settings recommended by design to remain constant
DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
// write delays, settings recommended by design to remain constant
DATA 4 0x021b082c 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
DATA 4 0x021b0830 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
DATA 4 0x021b0834 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
DATA 4 0x021b0838 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
DATA 4 0x021b482c 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
DATA 4 0x021b4830 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
DATA 4 0x021b4834 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
DATA 4 0x021b4838 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
DATA 4 0x021b0848 0x36383644 // MPRDDLCTL PHY0
DATA 4 0x021b4848 0x3a383846 // MPRDDLCTL PHY1
DATA 4 0x021b0850 0x38343E34 // MPWRDLCTL PHY0
DATA 4 0x021b4850 0x48384A44 // MPWRDLCTL PHY1
DATA 4 0x021b083c 0x20000000 //PHY0 dqs gating dis
DATA 4 0x021b0840 0x0
DATA 4 0x021b483c 0x20000000 //PHY0 dqs gating dis
DATA 4 0x021b4840 0x0
//For i.mx6qd parts of versions C and later (v1.2, v1.3).
DATA 4 0x021b08c0 0x24921492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
DATA 4 0x021b48c0 0x24921492
DATA 4 0x021b08b8 0x00000800 //frc_msr.
DATA 4 0x021b48b8 0x00000800 //frc_msr.
//=============================================================================
// Calibration setup end
//=============================================================================
// Channel0 - starting address 0x80000000
DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0
DATA 4 0x021b0004 0x00020024 // MMDC0_MDPDC
DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1
DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4 0x021b0018 0x0000174C // MMDC0_MDMISC
DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD
DATA 4 0x021b0030 0x009F0E10 // MMDC0_MDOR
DATA 4 0x021b0038 0x001A0889 // MMDC0_MDCFG3LP
DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC
DATA 4 0x021b0040 0x0000004F // Chan0 CS0_END 2 channel with 2 Channel fixed mode
// DATA 4 0x021b0400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL
// Channel1 - starting address 0x10000000
// Note: the values for Chan1 should match those of Chan0
DATA 4 0x021b400c 0x33374133 // MMDC1_MDCFG0
DATA 4 0x021b4004 0x00020024 // MMDC1_MDPDC
DATA 4 0x021b4010 0x00100A82 // MMDC1_MDCFG1
DATA 4 0x021b4014 0x00000093 // MMDC1_MDCFG2
DATA 4 0x021b4018 0x0000174C // MMDC1_MDMISC
DATA 4 0x021b402c 0x0F9F26D2 // MMDC1_MDRWD
DATA 4 0x021b4030 0x009F0E10 // MMDC1_MDOR
DATA 4 0x021b4038 0x001A0889 // MMDC1_MDCFG3LP
DATA 4 0x021b4008 0x00000000 // MMDC1_MDOTC
DATA 4 0x021b4040 0x00000017 // Chan1 CS0_END
// DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL
//=============================================================================
// LPDDR2 Mode Register Writes
//=============================================================================
// Channel 0 CS0
DATA 4 0x021b001c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset)
DATA 4 0x021b001c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
DATA 4 0x021b001c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration
DATA 4 0x021b001c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration
DATA 4 0x021b001c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration
// Channel 0 CS1
// Note, CS1 does not exist in this memory hence these writes are commented out
// They are only shown here for completeness
// If you use a memory where CS1 exists, simply uncomment these lines
//DATA 4 0x021b001c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset)
//DATA 4 0x021b001c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
//DATA 4 0x021b001c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration
//DATA 4 0x021b001c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration
//DATA 4 0x021b001c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration
// For Channel 1 mode register writes - these should match channel 0 settings
// Channel 1 CS0
DATA 4 0x021b401c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset)
DATA 4 0x021b401c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
DATA 4 0x021b401c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration
DATA 4 0x021b401c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration
DATA 4 0x021b401c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration
// Channel 1 CS1
// Note, CS1 does not exist in this memory hence these writes are commented out
// They are only shown here for completeness
// If you use a memory where CS1 exists, simply uncomment these lines
//DATA 4 0x021b401c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset)
//DATA 4 0x021b401c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
//DATA 4 0x021b401c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration
//DATA 4 0x021b401c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration
//DATA 4 0x021b401c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration
//////////#################################################//
//final DDR setup, before operation start:
DATA 4 0x021b0020 0x00001800 // MMDC0_MDREF
DATA 4 0x021b4020 0x00001800 // MMDC1_MDREF, align with Chan 0 setting
DATA 4 0x021b0818 0x0 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021b4818 0x0 // DDR_PHY_P1_MPODTCTRL
DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P1_MPMUR0, frc_msr
DATA 4 0x021b0004 0x00025564 // MMDC0_MDPDC now SDCTL power down enabled
DATA 4 0x021b4004 0x00025564 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting
DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled
DATA 4 0x021b4404 0x00011006 //MMDC1_MAPSR ADOPT power down enabled, align with Chan 0 setting
DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register
DATA 4 0x021b401c 0x00000000 // MMDC1_MDSCR, clear this register
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, 0x020e0010, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, 0x020e0018, 0x007F007F
DATA 4, 0x020e001c, 0x007F007F
#endif
#endif
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