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/*
* This header is generated by sopc2dts
* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CUSTOM_FPGA_H_
#define _CUSTOM_FPGA_H_
/* generated from qsys_ghrd_3c120.sopcinfo */
/* Dumping slaves of cpu.data_master */
/* cpu.jtag_debug_module is a altera_nios2_qsys */
#define CONFIG_SYS_CLK_FREQ 125000000
#define CONFIG_SYS_DCACHE_SIZE 32768
#define CONFIG_SYS_DCACHELINE_SIZE 32
#define CONFIG_SYS_ICACHELINE_SIZE 32
#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020
#define CONFIG_SYS_ICACHE_SIZE 32768
#define CONFIG_SYS_RESET_ADDR 0xc2800000
#define IO_REGION_BASE 0xE0000000
/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */
/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */
/* ddr2_bot.s1 is a altmemddr2 */
#define CONFIG_SYS_SDRAM_BASE 0xD0000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */
/* Dumping slaves of pb_cpu_to_io.m0 */
/* timer_1ms.s1 is a altera_avalon_timer */
#define CONFIG_SYS_TIMER_IRQ 11
#define CONFIG_SYS_TIMER_FREQ 125000000
#define CONFIG_SYS_TIMER_BASE 0xE8400000
/* sysid.control_slave is a altera_avalon_sysid_qsys */
#define CONFIG_SYS_SYSID_BASE 0xE8004D40
/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50
/* tse_mac.control_port is a triple_speed_ethernet */
#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048
#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800
#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400
#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048
#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000
#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000
#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000
#define CONFIG_ALTERA_TSE
#define CONFIG_MII
#define CONFIG_CMD_MII
#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18
#define CONFIG_SYS_ALTERA_TSE_FLAGS 1
/* uart.s1 is a altera_avalon_uart */
#define CONFIG_SYS_UART_BAUD 115200
#define CONFIG_SYS_UART_BASE 0xE8004C80
#define CONFIG_SYS_UART_FREQ 62500000
/* user_led_pio_8out.s1 is a altera_avalon_pio */
#define USER_LED_PIO_8OUT_BASE 0xE8004CC0
/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */
#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0
#define USER_DIPSW_PIO_8IN_IRQ 8
/* user_pb_pio_4in.s1 is a altera_avalon_pio */
#define USER_PB_PIO_4IN_BASE 0xE8004D00
#define USER_PB_PIO_4IN_IRQ 9
/* cfi_flash_64m.uas is a altera_generic_tristate_controller */
#define CFI_FLASH_64M_BASE 0xE0000000
/* ext_flash.s1 is a altera_avalon_cfi_flash */
#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
#endif /* _CUSTOM_FPGA_H_ */
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