blob: 8b9815fa00574f10cac1d017a322529610b335c4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/post.h>
#include <asm/arch/fsp/fsp_support.h>
#include <asm/processor.h>
int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
return x86_cpu_init_f();
}
int print_cpuinfo(void)
{
post_code(POST_CPU_INFO);
return default_print_cpuinfo();
}
void reset_cpu(ulong addr)
{
/* cold reset */
outb(0x06, PORT_RESET);
}
void board_final_cleanup(void)
{
u32 status;
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
status = fsp_notify(NULL, INIT_PHASE_BOOT);
if (status != FSP_SUCCESS)
debug("fail, error code %x\n", status);
else
debug("OK\n");
return;
}
|
