blob: b21dc4422ed21355fa717228a6a4d51b98e79227 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
|
#ifndef __ASM_SH_CACHE_H
#define __ASM_SH_CACHE_H
#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
int cache_control(unsigned int cmd);
#define L1_CACHE_BYTES 32
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
#else
/*
* 32-bytes is the largest L1 data cache line size for SH the architecture. So
* it is a safe default for DMA alignment.
*/
#define ARCH_DMA_MINALIGN 32
#endif /* CONFIG_SH4 || CONFIG_SH4A */
/*
* Use the L1 data cache line size value for the minimum DMA buffer alignment
* on SH.
*/
#ifndef ARCH_DMA_MINALIGN
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#endif
#endif /* __ASM_SH_CACHE_H */
|
