blob: 91133a38aee345a697ef52f24ec25b0d62d7ab6e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
|
/*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/cache.h>
int checkcpu(void)
{
#ifdef CONFIG_SH4A
puts("CPU: SH-4A\n");
#else
puts("CPU: SH4\n");
#endif
return 0;
}
int cpu_init (void)
{
return 0;
}
int cleanup_before_linux (void)
{
disable_interrupts();
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
reset_cpu (0);
return 0;
}
void flush_cache (unsigned long addr, unsigned long size)
{
invalidate_dcache_range(addr , addr + size);
}
void icache_enable (void)
{
cache_control(0);
}
void icache_disable (void)
{
cache_control(1);
}
int icache_status (void)
{
return 0;
}
void dcache_enable (void)
{
}
void dcache_disable (void)
{
}
int dcache_status (void)
{
return 0;
}
int cpu_eth_init(bd_t *bis)
{
#ifdef CONFIG_SH_ETHER
sh_eth_initialize(bis);
#endif
return 0;
}
|
