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/*
* Device Tree Source for UniPhier PH1-sLD8 SoC
*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "skeleton.dtsi"
/ {
compatible = "panasonic,ph1-sld8";
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
uart0: serial@54006800 {
compatible = "panasonic,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <80000000>;
};
uart1: serial@54006900 {
compatible = "panasonic,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <80000000>;
};
uart2: serial@54006a00 {
compatible = "panasonic,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <80000000>;
};
uart3: serial@54006b00 {
compatible = "panasonic,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x20>;
clock-frequency = <80000000>;
};
};
};
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