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config ARCH_LS1012A
bool
select FSL_LSCH2
select SYS_FSL_MMDC
select SYS_FSL_ERRATUM_A010315
config ARCH_LS1043A
bool
select FSL_LSCH2
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
config ARCH_LS1046A
bool
select FSL_LSCH2
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_SRDS_2
config ARCH_LS2080A
bool
select FSL_LSCH3
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_SRDS_2
config FSL_LSCH2
bool
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
config FSL_LSCH3
bool
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
config SYS_FSL_MMDC
bool
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
SoCs may have multiple clusters with each cluster may have multiple
ports. If some ports are reserved but higher ports are used for
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config NUM_DDR_CONTROLLERS
int "Maximum DDR controllers"
default 3 if ARCH_LS2080A
default 1
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
config SYS_FSL_HAS_DP_DDR
bool
config SYS_FSL_SRDS_1
bool
config SYS_FSL_SRDS_2
bool
config SYS_HAS_SERDES
bool
endmenu
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