blob: 397b1791980ef565eaaea349efd49cb4308eda9f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
menu "ARC architecture"
depends on ARC
config SYS_ARCH
default "arc"
config SYS_CPU
default "arcv1"
choice
prompt "CPU selection"
default CPU_ARC770D
config CPU_ARC750D
bool "ARC 750D"
select ARC_MMU_V2
help
Choose this option to build an U-Boot for ARC750D CPU.
config CPU_ARC770D
bool "ARC 770D"
select ARC_MMU_V3
help
Choose this option to build an U-Boot for ARC770D CPU.
endchoice
choice
prompt "MMU Version"
default ARC_MMU_V3 if CPU_ARC770D
default ARC_MMU_V2 if CPU_ARC750D
config ARC_MMU_V2
bool "MMU v2"
depends on CPU_ARC750D
help
Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
when 2 D-TLB and 1 I-TLB entries index into same 2way set.
config ARC_MMU_V3
bool "MMU v3"
depends on CPU_ARC770D
help
Introduced with ARC700 4.10: New Features
Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
Shared Address Spaces (SASID)
endchoice
config SYS_ICACHE_OFF
bool "Do not use Instruction Cache"
default n
config SYS_DCACHE_OFF
bool "Do not use Data Cache"
default n
config ARC_CACHE_LINE_SHIFT
int "Cache Line Length (as power of 2)"
range 5 7
default "6"
depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
help
Starting with ARC700 4.9, Cache line length is configurable,
This option specifies "N", with Line-len = 2 power N
So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
Linux only supports same line lengths for I and D caches.
choice
prompt "Target select"
config TARGET_TB100
bool "Support tb100"
config TARGET_ARCANGEL4
bool "Support arcangel4"
config TARGET_ARCANGEL4_BE
bool "Support arcangel4-be"
config TARGET_AXS101
bool "Support axs101"
endchoice
source "board/abilis/tb100/Kconfig"
source "board/synopsys/Kconfig"
source "board/synopsys/axs101/Kconfig"
endmenu
|
