/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1994 Waldorf GMBH * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle * Copyright (C) 1996 Paul M. Antoine * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H #include <linux/config.h> #include <asm/isadep.h> #include <asm/cachectl.h> #include <asm/mipsregs.h> #include <asm/reg.h> #include <asm/system.h> /* * Return current * instruction pointer ("program counter"). */ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) /* * System setup and hardware flags.. */ extern void (*cpu_wait)(void); extern unsigned int vced_count, vcei_count; #define NUM_FPU_REGS 32 typedef __u64 fpureg_t; /* * It would be nice to add some more fields for emulator statistics, but there * are a number of fixed offsets in offset.h and elsewhere that would have to * be recalculated by hand. So the additional information will be private to * the FPU emulator for now. See asm-mips/fpu_emulator.h. */ struct mips_fpu_struct { fpureg_t fpr[NUM_FPU_REGS]; unsigned int fcr31; }; #define NUM_DSP_REGS 6 typedef __u32 dspreg_t; struct mips_dsp_state { dspreg_t dspr[NUM_DSP_REGS]; unsigned int dspcontrol; }; typedef struct { unsigned long seg; } mm_segment_t; #define ARCH_MIN_TASKALIGN 8 struct mips_abi; /* * If you change thread_struct remember to change the #defines below too! */ struct thread_struct { /* Saved main processor registers. */ unsigned long reg16; unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; unsigned long reg29, reg30, reg31; /* Saved cp0 stuff. */ unsigned long cp0_status; /* Saved fpu/fpu emulator stuff. */ struct mips_fpu_struct fpu; #ifdef CONFIG_MIPS_MT_FPAFF /* Emulated instruction count */ unsigned long emulated_fp; /* Saved per-thread scheduler affinity mask */ cpumask_t user_cpus_allowed; #endif /* CONFIG_MIPS_MT_FPAFF */ /* Saved state of the DSP ASE, if available. */ struct mips_dsp_state dsp; /* Other stuff associated with the thread. */ unsigned long cp0_badvaddr; /* Last user fault */ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; unsigned long trap_no; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; struct mips_abi *abi; }; struct task_struct; /* Free all resources held by a thread. */ #define release_thread(thread) do { } while(0) /* Prepare to copy thread state - unlazy all lazy status */ #define prepare_to_copy(tsk) do { } while (0) #define cpu_relax() barrier() /* * Return_address is a replacement for __builtin_return_address(count) * which on certain architectures cannot reasonably be implemented in GCC * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). * Note that __builtin_return_address(x>=1) is forbidden because GCC * aborts compilation on some CPUs. It's simply not possible to unwind * some CPU's stackframes. * * __builtin_return_address works only for non-leaf functions. We avoid the * overhead of a function call by forcing the compiler to save the return * address register on the stack. */ #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) #ifdef CONFIG_CPU_HAS_PREFETCH #define ARCH_HAS_PREFETCH static inline void prefetch(const void *addr) { __asm__ __volatile__( " .set mips4 \n" " pref %0, (%1) \n" " .set mips0 \n" : : "i" (Pref_Load), "r" (addr)); } #endif #endif /* _ASM_PROCESSOR_H */