/* * (C) Copyright 2013 - 2015 Xilinx, Inc. * * Xilinx Zynq SD Host Controller Interface * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <dm.h> #include <fdtdec.h> #include <libfdt.h> #include <malloc.h> #include <sdhci.h> #ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ # define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0 #endif struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; }; static int arasan_sdhci_probe(struct udevice *dev) { struct arasan_sdhci_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); u32 caps; int ret; host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; #ifdef CONFIG_ZYNQ_HISPD_BROKEN host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; #endif host->version = sdhci_readw(host, SDHCI_HOST_VERSION); caps = sdhci_readl(host, SDHCI_CAPABILITIES); ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width, caps, CONFIG_ZYNQ_SDHCI_MAX_FREQ, CONFIG_ZYNQ_SDHCI_MIN_FREQ, host->version, host->quirks, 0); host->mmc = &plat->mmc; if (ret) return ret; host->mmc->priv = host; host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); } static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) { struct sdhci_host *host = dev_get_priv(dev); host->name = dev->name; host->ioaddr = (void *)dev_get_addr(dev); return 0; } static int arasan_sdhci_bind(struct udevice *dev) { struct arasan_sdhci_plat *plat = dev_get_platdata(dev); int ret; ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); if (ret) return ret; return 0; } static const struct udevice_id arasan_sdhci_ids[] = { { .compatible = "arasan,sdhci-8.9a" }, { } }; U_BOOT_DRIVER(arasan_sdhci_drv) = { .name = "arasan_sdhci", .id = UCLASS_MMC, .of_match = arasan_sdhci_ids, .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, .ops = &sdhci_ops, .bind = arasan_sdhci_bind, .probe = arasan_sdhci_probe, .priv_auto_alloc_size = sizeof(struct sdhci_host), .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat), };