/*********************************************************************
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
# Description: U-BOOT Configuration File
# Michal Simek - monstr@monstr.eu
#
**********************************************************************/

/* System Clock Frequency */
#define XILINX_CLOCK_FREQ	100000000

/* Interrupt controller is opb_intc_0 */
#define XILINX_INTC_BASEADDR	0x41200000
#define XILINX_INTC_NUM_INTR_INPUTS	11

/* Timer pheriphery is opb_timer_1 */
#define XILINX_TIMER_BASEADDR	0x41c00000
#define XILINX_TIMER_IRQ	1

/* Uart pheriphery is RS232_Uart_1 */
#define XILINX_UART_BASEADDR	0x40600000
#define XILINX_UART_BAUDRATE	115200

/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR	0x40000000

/* FLASH doesn't exist none */

/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
#define XILINX_RAM_START	0x30000000
#define XILINX_RAM_SIZE	0x10000000

/* Sysace Controller is SysACE_CompactFlash */
#define XILINX_SYSACE_BASEADDR	0x41800000
#define XILINX_SYSACE_HIGHADDR	0x4180ffff
#define XILINX_SYSACE_MEM_WIDTH	16

/* Ethernet controller is Ethernet_MAC */
#define XPAR_XEMAC_NUM_INSTANCES	1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID	0
#define XPAR_OPB_ETHERNET_0_BASEADDR	0x40c00000
#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0ffff
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT	1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST	1
#define XPAR_OPB_ETHERNET_0_MII_EXIST	1