/* * mux.c * * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <common.h> #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> #include <asm/arch/mux.h> #include <asm/io.h> #include <i2c.h> #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ {-1}, }; static struct module_pin_mux uart1_pin_mux[] = { {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ {-1}, }; static struct module_pin_mux uart2_pin_mux[] = { {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ {-1}, }; static struct module_pin_mux uart3_pin_mux[] = { {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ {-1}, }; static struct module_pin_mux uart4_pin_mux[] = { {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ {-1}, }; static struct module_pin_mux uart5_pin_mux[] = { {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ {-1}, }; static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; static struct module_pin_mux i2c0_pin_mux[] = { {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ {-1}, }; static struct module_pin_mux i2c1_pin_mux[] = { {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ {-1}, }; static struct module_pin_mux gpio0_7_pin_mux[] = { {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ {-1}, }; static struct module_pin_mux rmii1_pin_mux[] = { {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ {-1}, }; static struct module_pin_mux rgmii2_pin_mux[] = { {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ {-1}, }; static struct module_pin_mux nand_pin_mux[] = { {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ {-1}, }; void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); } void enable_uart1_pin_mux(void) { configure_module_pin_mux(uart1_pin_mux); } void enable_uart2_pin_mux(void) { configure_module_pin_mux(uart2_pin_mux); } void enable_uart3_pin_mux(void) { configure_module_pin_mux(uart3_pin_mux); } void enable_uart4_pin_mux(void) { configure_module_pin_mux(uart4_pin_mux); } void enable_uart5_pin_mux(void) { configure_module_pin_mux(uart5_pin_mux); } void enable_i2c0_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); } void enable_i2c1_pin_mux(void) { configure_module_pin_mux(i2c1_pin_mux); } void enable_board_pin_mux() { /* Baltos */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii2_pin_mux); configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #endif }