/* * Copyright (C) 2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ * * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage */ /* image version */ #define __ASSEMBLY__ #include IMAGE_VERSION 2 /* * Boot Device : one of spi, sd, eimnor, nand, sata: * spinor: flash_offset: 0x0400 * nand: flash_offset: 0x0400 * sata: flash_offset: 0x0400 * sd/mmc: flash_offset: 0x0400 * eimnor: flash_offset: 0x1000 */ #if defined(CONFIG_SYS_BOOT_EIMNOR) BOOT_FROM nor #else /* others has the same flash_offset as sd */ BOOT_FROM sd #endif #ifdef CONFIG_USE_PLUGIN /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ PLUGIN board/freescale/mx6qsabreauto/plugin.bin 0x00907000 #else #ifdef CONFIG_SECURE_BOOT CSF 0x2000 #endif /* * Device Configuration Data (DCD) * * Each entry must have the format: * Addr-type Address Value * * where: * Addr-type register length (1,2 or 4 bytes) * Address absolute address of the register * value value to be stored in the register */ DATA 4 0x020e0798 0x000C0000 DATA 4 0x020e0758 0x00000000 DATA 4 0x020e0588 0x00000030 DATA 4 0x020e0594 0x00000030 DATA 4 0x020e056c 0x00000030 DATA 4 0x020e0578 0x00000030 DATA 4 0x020e074c 0x00000030 DATA 4 0x020e057c 0x00000030 DATA 4 0x020e058c 0x00000000 DATA 4 0x020e059c 0x00000030 DATA 4 0x020e05a0 0x00000030 DATA 4 0x020e078c 0x00000030 DATA 4 0x020e0750 0x00020000 DATA 4 0x020e05a8 0x00000030 DATA 4 0x020e05b0 0x00000030 DATA 4 0x020e0524 0x00000030 DATA 4 0x020e051c 0x00000030 DATA 4 0x020e0518 0x00000030 DATA 4 0x020e050c 0x00000030 DATA 4 0x020e05b8 0x00000030 DATA 4 0x020e05c0 0x00000030 DATA 4 0x020e0774 0x00020000 DATA 4 0x020e0784 0x00000030 DATA 4 0x020e0788 0x00000030 DATA 4 0x020e0794 0x00000030 DATA 4 0x020e079c 0x00000030 DATA 4 0x020e07a0 0x00000030 DATA 4 0x020e07a4 0x00000030 DATA 4 0x020e07a8 0x00000030 DATA 4 0x020e0748 0x00000030 DATA 4 0x020e05ac 0x00000030 DATA 4 0x020e05b4 0x00000030 DATA 4 0x020e0528 0x00000030 DATA 4 0x020e0520 0x00000030 DATA 4 0x020e0514 0x00000030 DATA 4 0x020e0510 0x00000030 DATA 4 0x020e05bc 0x00000030 DATA 4 0x020e05c4 0x00000030 DATA 4 0x021b0800 0xa1390003 DATA 4 0x021b080c 0x001b001e DATA 4 0x021b0810 0x002e0029 DATA 4 0x021b480c 0x001b002a DATA 4 0x021b4810 0x0019002c DATA 4 0x021b083c 0x43240334 DATA 4 0x021b0840 0x0324031a DATA 4 0x021b483c 0x43340344 DATA 4 0x021b4840 0x03280276 DATA 4 0x021b0848 0x44383A3E DATA 4 0x021b4848 0x3C3C3846 DATA 4 0x021b0850 0x2e303230 DATA 4 0x021b4850 0x38283E34 DATA 4 0x021b081c 0x33333333 DATA 4 0x021b0820 0x33333333 DATA 4 0x021b0824 0x33333333 DATA 4 0x021b0828 0x33333333 DATA 4 0x021b481c 0x33333333 DATA 4 0x021b4820 0x33333333 DATA 4 0x021b4824 0x33333333 DATA 4 0x021b4828 0x33333333 DATA 4 0x021b08b8 0x00000800 DATA 4 0x021b48b8 0x00000800 DATA 4 0x021b0004 0x00020036 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b000c 0x898E7955 DATA 4 0x021b0010 0xFF328F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b0018 0x00001740 DATA 4 0x021b001c 0x00008000 DATA 4 0x021b002c 0x000026d2 DATA 4 0x021b0030 0x008E1023 DATA 4 0x021b0040 0x00000047 DATA 4 0x021b0400 0x12420000 DATA 4 0x021b0000 0x841A0000 DATA 4 0x00bb0008 0x00000004 DATA 4 0x00bb000c 0x2891E41A DATA 4 0x00bb0038 0x00000564 DATA 4 0x021b001c 0x04088032 DATA 4 0x021b001c 0x00008033 DATA 4 0x021b001c 0x00048031 DATA 4 0x021b001c 0x09408030 DATA 4 0x021b001c 0x04008040 DATA 4 0x021b0020 0x00005800 DATA 4 0x021b0818 0x00011117 DATA 4 0x021b4818 0x00011117 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 /* set the default clock gate to save power */ DATA 4, 0x020c4068, 0x00C03F3F DATA 4, 0x020c406c, 0x0030FC03 DATA 4, 0x020c4070, 0x0FFFC000 DATA 4, 0x020c4074, 0x3FF00000 DATA 4, 0x020c4078, 0xFFFFF300 DATA 4, 0x020c407c, 0x0F0000F3 DATA 4, 0x020c4080, 0x00000FFF /* enable AXI cache for VDOA/VPU/IPU */ DATA 4, 0x020e0010, 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4, 0x020e0018, 0x007F007F DATA 4, 0x020e001c, 0x007F007F #endif