/* * Copyright (C) 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include #include #include #include #include #include #if CONFIG_I2C_MXC #include #endif #ifdef CONFIG_CMD_MMC #include #include #endif #ifdef CONFIG_ARCH_MMU #include #include #endif #ifdef CONFIG_CMD_CLOCK #include #endif #ifdef CONFIG_ANDROID_RECOVERY #include "../common/recovery.h" #include #include #include #include #include #include #endif DECLARE_GLOBAL_DATA_PTR; static u32 system_rev; static enum boot_device boot_dev; static inline void setup_boot_device(void) { uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; switch (bt_mem_ctl) { case 0x0: if (bt_mem_type) boot_dev = ONE_NAND_BOOT; else boot_dev = WEIM_NOR_BOOT; break; case 0x2: if (bt_mem_type) boot_dev = SATA_BOOT; else boot_dev = PATA_BOOT; break; case 0x3: if (bt_mem_type) boot_dev = SPI_NOR_BOOT; else boot_dev = I2C_BOOT; break; case 0x4: case 0x5: boot_dev = SD_BOOT; break; case 0x6: case 0x7: boot_dev = MMC_BOOT; break; case 0x8 ... 0xf: boot_dev = NAND_BOOT; break; default: boot_dev = UNKNOWN_BOOT; break; } } enum boot_device get_boot_device(void) { return boot_dev; } u32 get_board_rev(void) { return system_rev; } static inline void setup_soc_rev(void) { int reg; /* Si rev is obtained from ROM */ reg = __REG(ROM_SI_REV); switch (reg) { case 0x10: system_rev = 0x53000 | CHIP_REV_1_0; break; case 0x20: system_rev = 0x53000 | CHIP_REV_2_0; break; case 0x21: system_rev = 0x53000 | CHIP_REV_2_1; break; default: system_rev = 0x53000 | CHIP_REV_UNKNOWN; } } inline int is_soc_rev(int rev) { return (system_rev & 0xFF) - rev; } #ifdef CONFIG_ARCH_MMU void board_mmu_init(void) { unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; unsigned long i; /* * Set the TTB register */ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); /* * Set the Domain Access Control Register */ i = ARM_ACCESS_DACR_DEFAULT; asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); /* * First clear all TT entries - ie Set them to Faulting */ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); /* Actual Virtual Size Attributes Function */ /* Base Base MB cached? buffered? access permissions */ /* xxx00000 xxx00000 */ X_ARM_MMU_SECTION(0x000, 0x000, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */ X_ARM_MMU_SECTION(0x070, 0x070, 0x010, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */ X_ARM_MMU_SECTION(0x100, 0x100, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SATA */ X_ARM_MMU_SECTION(0x180, 0x180, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3M */ X_ARM_MMU_SECTION(0x200, 0x200, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* GPU */ X_ARM_MMU_SECTION(0x400, 0x400, 0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */ X_ARM_MMU_SECTION(0x700, 0x700, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ X_ARM_MMU_SECTION(0x700, 0x900, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ X_ARM_MMU_SECTION(0xB00, 0xB00, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ X_ARM_MMU_SECTION(0xB00, 0xD00, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */ X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* iRam */ /* Workaround for arm errata #709718 */ /* Setup PRRR so device is always mapped to non-shared */ asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); i &= (~(3 << 0x10)); asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); /* Enable MMU */ MMU_ON(); } #endif int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; return 0; } static void setup_uart(void) { /* UART1 RXD */ mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3); mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, 0x1E4); mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); /* UART1 TXD */ mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3); mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, 0x1E4); } #ifdef CONFIG_I2C_MXC static void setup_i2c(unsigned int module_base) { switch (module_base) { case I2C1_BASE_ADDR: /* i2c1 SDA */ mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, INPUT_CTL_PATH1); mxc_iomux_set_pad(MX53_PIN_EIM_D28, PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE); /* i2c1 SCL */ mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH1); mxc_iomux_set_pad(MX53_PIN_EIM_D21, PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE); break; case I2C2_BASE_ADDR: /* i2c2 SDA */ mxc_request_iomux(MX53_PIN_KEY_ROW3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, INPUT_CTL_PATH0); mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE); /* i2c2 SCL */ mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH0); mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE); break; case I2C3_BASE_ADDR: /* GPIO_3 for I2C3_SCL */ mxc_request_iomux(MX53_PIN_GPIO_5, IOMUX_CONFIG_ALT6 | IOMUX_CONFIG_SION); mxc_iomux_set_input(MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH1); mxc_iomux_set_pad(MX53_PIN_GPIO_5, PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD | PAD_CTL_HYS_ENABLE); /* GPIO_16 for I2C3_SDA */ mxc_request_iomux(MX53_PIN_GPIO_6, IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION); mxc_iomux_set_input(MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT, INPUT_CTL_PATH1); mxc_iomux_set_pad(MX53_PIN_GPIO_6, PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD | PAD_CTL_HYS_ENABLE); /* No device is connected via I2C3 in EVK and ARM2 */ break; default: printf("Invalid I2C base: 0x%x\n", module_base); break; } } void setup_pmic_voltages(void) { int value; unsigned char buf[4] = { 0 }; i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (!i2c_probe(0x8)) { if (i2c_read(0x8, 24, 1, &buf[0], 3)) { printf("%s:i2c_read:error\n", __func__); } /* increase VDDGP as 1.25V for 1GHZ on SW1 */ buf[2] = 0x30; if (i2c_write(0x8, 24, 1, buf, 3)) { printf("%s:i2c_write:error\n", __func__); } /* Charger Source: set VBUS threshold low to 4.25V, * set Weak VBUS threshold to 4.275V */ if (i2c_read(0x8, 53, 1, &buf[0], 3)) printf("%s:i2c_read 53:error\n", __func__); buf[2] = (buf[2] & 0x38) | 0x47; buf[1] = (buf[1] & 0x70) | 0x8e; buf[0] = buf[0] & 0xfc; if (i2c_write(0x8, 53, 1, buf, 3)) printf("%s:i2c_write 53:error\n", __func__); /* set both AUX&USB current limit to 1.5A for Ripley 2.1 only */ if (i2c_read(0x8, 52, 1, &buf[0], 3)) printf("%s:i2c_read 52:error\n", __func__); buf[0] = (buf[0] & 0xef) | 0x10; if (i2c_write(0x8, 52, 1, buf, 3)) printf("%s:i2c_write 52:error\n", __func__); /* Change CC current to 1550mA */ /* Change CV voltage as 4.2v */ if (i2c_read(0x8, 51, 1, &buf[0], 3)) printf("%s:i2c_read 51:error\n", __func__); buf[1] = (buf[1] & 0x0) | 0xd8; buf[2] = (buf[2] & 0x3f) | 0xc0; if (i2c_write(0x8, 51, 1, buf, 3)) printf("%s:i2c_write 51:error\n", __func__); } else printf("Error: Dont't found mc34708 on board.\n"); } #endif #ifdef CONFIG_CMD_MMC struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1, 1}, {MMC_SDHC3_BASE_ADDR, 1, 1}, }; #ifdef CONFIG_DYNAMIC_MMC_DEVNO int get_mmc_env_devno() { uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); return (soc_sbmr & 0x00300000) ? 1 : 0; } #endif #ifdef CONFIG_EMMC_DDR_PORT_DETECT int detect_mmc_emmc_ddr_port(struct fsl_esdhc_cfg *cfg) { return (MMC_SDHC3_BASE_ADDR == cfg->esdhc_base) ? 1 : 0; } #endif int esdhc_gpio_init(bd_t *bis) { s32 status = 0; u32 index = 0; for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; ++index) { switch (index) { case 0: mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); break; case 1: mxc_request_iomux(MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2); mxc_request_iomux(MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2); mxc_request_iomux(MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4); mxc_request_iomux(MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4); mxc_request_iomux(MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4); mxc_request_iomux(MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4); mxc_request_iomux(MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4); mxc_request_iomux(MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4); mxc_request_iomux(MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4); mxc_request_iomux(MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4); mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4); mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4); break; default: printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); return status; } status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); } return status; } int board_mmc_init(bd_t *bis) { if (!esdhc_gpio_init(bis)) return 0; else return -1; } #endif int board_init(void) { #ifdef CONFIG_MFG /* MFG firmware need reset usb to avoid host crash firstly */ #define USBCMD 0x140 int val = readl(OTG_BASE_ADDR + USBCMD); val &= ~0x1; /*RS bit*/ writel(val, OTG_BASE_ADDR + USBCMD); #endif setup_boot_device(); setup_soc_rev(); gd->bd->bi_arch_number = MACH_TYPE_MX53_PCBA;/* board id for linux */ /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; setup_uart(); #ifdef CONFIG_I2C_MXC setup_i2c(CONFIG_SYS_I2C_PORT); /* Increase VDDGP voltage */ setup_pmic_voltages(); /* Switch to 1GHZ */ clk_config(CONFIG_REF_CLK_FREQ, 1000, CPU_CLK); #endif return 0; } #ifdef CONFIG_ANDROID_RECOVERY struct reco_envs supported_reco_envs[BOOT_DEV_NUM] = { { .cmd = NULL, .args = NULL, }, { .cmd = NULL, .args = NULL, }, { .cmd = NULL, .args = NULL, }, { .cmd = NULL, .args = NULL, }, { .cmd = NULL, .args = NULL, }, { .cmd = NULL, .args = NULL, }, { .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, }, { .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, }, { .cmd = NULL, .args = NULL, }, }; int check_recovery_cmd_file(void) { disk_partition_t info; ulong part_length; int filelen = 0; char *env; int i; /* For test only */ /* When detecting android_recovery_switch, * enter recovery mode directly */ env = getenv("android_recovery_switch"); if (!strcmp(env, "1")) { printf("Env recovery detected!\nEnter recovery mode!\n"); return 1; } printf("Checking for recovery command file...\n"); switch (get_boot_device()) { case MMC_BOOT: case SD_BOOT: { for (i = 0; i < 2; i++) { block_dev_desc_t *dev_desc = NULL; struct mmc *mmc = find_mmc_device(i); dev_desc = get_dev("mmc", i); if (NULL == dev_desc) { printf("** Block device MMC %d not supported\n", i); continue; } mmc_init(mmc); if (get_partition_info(dev_desc, CONFIG_ANDROID_CACHE_PARTITION_MMC, &info)) { printf("** Bad partition %d **\n", CONFIG_ANDROID_CACHE_PARTITION_MMC); continue; } part_length = ext2fs_set_blk_dev(dev_desc, CONFIG_ANDROID_CACHE_PARTITION_MMC); if (part_length == 0) { printf("** Bad partition - mmc %d:%d **\n", i, CONFIG_ANDROID_CACHE_PARTITION_MMC); ext2fs_close(); continue; } if (!ext2fs_mount(part_length)) { printf("** Bad ext2 partition or " "disk - mmc i:%d **\n", i, CONFIG_ANDROID_CACHE_PARTITION_MMC); ext2fs_close(); continue; } filelen = ext2fs_open(CONFIG_ANDROID_RECOVERY_CMD_FILE); ext2fs_close(); break; } } break; case NAND_BOOT: return 0; break; case SPI_NOR_BOOT: return 0; break; case UNKNOWN_BOOT: default: return 0; break; } return (filelen > 0) ? 1 : 0; } #endif int board_late_init(void) { return 0; } int checkboard(void) { printf("Board: MX53-PCBA "); printf("Boot Reason: ["); switch (__REG(SRC_BASE_ADDR + 0x8)) { case 0x0001: printf("POR"); break; case 0x0009: printf("RST"); break; case 0x0010: case 0x0011: printf("WDOG"); break; default: printf("unknown"); } printf("]\n"); printf("Boot Device: "); switch (get_boot_device()) { case WEIM_NOR_BOOT: printf("NOR\n"); break; case ONE_NAND_BOOT: printf("ONE NAND\n"); break; case PATA_BOOT: printf("PATA\n"); break; case SATA_BOOT: printf("SATA\n"); break; case I2C_BOOT: printf("I2C\n"); break; case SPI_NOR_BOOT: printf("SPI NOR\n"); break; case SD_BOOT: printf("SD\n"); break; case MMC_BOOT: printf("MMC\n"); break; case NAND_BOOT: printf("NAND\n"); break; case UNKNOWN_BOOT: default: printf("UNKNOWN\n"); break; } return 0; }