/* * Copyright 2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "../common/qixis.h" #include "ls1012aqds_qixis.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { char buf[64]; u8 sw; sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); if (sw & QIXIS_LBMAP_ALTBANK) printf("flash: 2\n"); else printf("flash: 1\n"); printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf)); return 0; } int dram_init(void) { mmdc_init(); gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } int board_early_init_f(void) { fsl_lsch2_early_init_f(); return 0; } #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { u8 mux_sdhc_cd = 0x80; i2c_set_bus_num(0); i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); return 0; } #endif int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *) CONFIG_SYS_CCI400_ADDR; /* Set CCI-400 control override register to enable barrier * transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif return 0; } int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { arch_fixup_fdt(blob); ft_cpu_setup(blob, bd); return 0; } #endif