/* * Copyright 2013 Maxime Ripard * * Maxime Ripard <maxime.ripard@free-electrons.com> * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ /include/ "skeleton.dtsi" / { interrupt-parent = <&gic>; aliases { ethernet0 = &gmac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; serial6 = &uart6; serial7 = &uart7; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; }; }; memory { reg = <0x40000000 0x80000000>; }; timer { compatible = "arm,armv7-timer"; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; pmu { compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; interrupts = <0 120 4>, <0 121 4>; }; clocks { #address-cells = <1>; #size-cells = <1>; ranges; osc24M: clk@01c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "osc32k"; }; pll1: clk@01c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; clock-output-names = "pll1"; }; pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; clock-output-names = "pll4"; }; pll5: clk@01c20020 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; }; pll6: clk@01c20028 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; }; pll8: clk@01c20040 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; reg = <0x01c20040 0x4>; clocks = <&osc24M>; clock-output-names = "pll8"; }; cpu: cpu@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; clock-output-names = "cpu"; }; axi: axi@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; clock-output-names = "axi"; }; ahb: ahb@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; clock-output-names = "ahb"; }; ahb_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; clock-output-names = "ahb_usb0", "ahb_ehci0", "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", "ahb_sata", "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", "ahb_de_fe1", "ahb_gmac", "ahb_mp", "ahb_mali"; }; apb0: apb0@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; clock-output-names = "apb0"; }; apb0_gates: clk@01c20068 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; clock-output-names = "apb0_codec", "apb0_spdif", "apb0_ac97", "apb0_iis0", "apb0_iis1", "apb0_pio", "apb0_ir0", "apb0_ir1", "apb0_iis2", "apb0_keypad"; }; apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1_mux"; }; apb1: apb1@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; clock-output-names = "apb1"; }; apb1_gates: clk@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_i2c3", "apb1_can", "apb1_scr", "apb1_ps20", "apb1_ps21", "apb1_i2c4", "apb1_uart0", "apb1_uart1", "apb1_uart2", "apb1_uart3", "apb1_uart4", "apb1_uart5", "apb1_uart6", "apb1_uart7"; }; nand_clk: clk@01c20080 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; }; ms_clk: clk@01c20084 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; }; mmc0_clk: clk@01c20088 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; }; mmc1_clk: clk@01c2008c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; }; mmc2_clk: clk@01c20090 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; }; mmc3_clk: clk@01c20094 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20094 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc3"; }; ts_clk: clk@01c20098 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; }; ss_clk: clk@01c2009c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; }; spi0_clk: clk@01c200a0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; }; spi1_clk: clk@01c200a4 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; }; spi2_clk: clk@01c200a8 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; }; pata_clk: clk@01c200ac { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200ac 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "pata"; }; ir0_clk: clk@01c200b0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; }; ir1_clk: clk@01c200b4 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir1"; }; usb_clk: clk@01c200cc { #clock-cells = <1>; #reset-cells = <1>; compatible = "allwinner,sun4i-a10-usb-clk"; reg = <0x01c200cc 0x4>; clocks = <&pll6 1>; clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; }; spi3_clk: clk@01c200d4 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200d4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi3"; }; mbus_clk: clk@01c2015c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; clock-output-names = "mbus"; }; /* * The following two are dummy clocks, placeholders used in the gmac_tx * clock. The gmac driver will choose one parent depending on the PHY * interface mode, using clk_set_rate auto-reparenting. * The actual TX clock rate is not controlled by the gmac_tx clock. */ mii_phy_tx_clk: clk@2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; gmac_int_tx_clk: clk@3 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; clock-output-names = "gmac_int_tx"; }; gmac_tx_clk: clk@01c20164 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c20164 0x4>; clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; clock-output-names = "gmac_tx"; }; /* * Dummy clock used by output clocks */ osc24M_32k: clk@1 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <750>; clock-mult = <1>; clocks = <&osc24M>; clock-output-names = "osc24M_32k"; }; clk_out_a: clk@01c201f0 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-out-clk"; reg = <0x01c201f0 0x4>; clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; clock-output-names = "clk_out_a"; }; clk_out_b: clk@01c201f4 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-out-clk"; reg = <0x01c201f4 0x4>; clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; clock-output-names = "clk_out_b"; }; }; soc@01c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; nmi_intc: interrupt-controller@01c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; #interrupt-cells = <2>; reg = <0x01c00030 0x0c>; interrupts = <0 0 4>; }; spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <0 10 4>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@01c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <0 11 4>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; emac: ethernet@01c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <0 55 4>; clocks = <&ahb_gates 17>; status = "disabled"; }; mdio@01c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mmc0: mmc@01c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ahb_gates 8>, <&mmc0_clk>; clock-names = "ahb", "mmc"; interrupts = <0 32 4>; status = "disabled"; }; mmc1: mmc@01c10000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ahb_gates 9>, <&mmc1_clk>; clock-names = "ahb", "mmc"; interrupts = <0 33 4>; status = "disabled"; }; mmc2: mmc@01c11000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ahb_gates 10>, <&mmc2_clk>; clock-names = "ahb", "mmc"; interrupts = <0 34 4>; status = "disabled"; }; mmc3: mmc@01c12000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c12000 0x1000>; clocks = <&ahb_gates 11>, <&mmc3_clk>; clock-names = "ahb", "mmc"; interrupts = <0 35 4>; status = "disabled"; }; usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; clocks = <&usb_clk 8>; clock-names = "usb_phy"; resets = <&usb_clk 1>, <&usb_clk 2>; reset-names = "usb1_reset", "usb2_reset"; status = "disabled"; }; ehci0: usb@01c14000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <0 39 4>; clocks = <&ahb_gates 1>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; ohci0: usb@01c14400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <0 64 4>; clocks = <&usb_clk 6>, <&ahb_gates 2>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; spi2: spi@01c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <0 12 4>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; ahci: sata@01c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <0 56 4>; clocks = <&pll6 0>, <&ahb_gates 25>; status = "disabled"; }; ehci1: usb@01c1c000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <0 40 4>; clocks = <&ahb_gates 3>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; ohci1: usb@01c1c400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <0 65 4>; clocks = <&usb_clk 7>, <&ahb_gates 4>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; spi3: spi@01c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <0 50 4>; clocks = <&ahb_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; pio: pinctrl@01c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <0 28 4>; clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; pwm0_pins_a: pwm0@0 { allwinner,pins = "PB2"; allwinner,function = "pwm"; allwinner,drive = <0>; allwinner,pull = <0>; }; pwm1_pins_a: pwm1@0 { allwinner,pins = "PI3"; allwinner,function = "pwm"; allwinner,drive = <0>; allwinner,pull = <0>; }; uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; allwinner,drive = <0>; allwinner,pull = <0>; }; uart2_pins_a: uart2@0 { allwinner,pins = "PI16", "PI17", "PI18", "PI19"; allwinner,function = "uart2"; allwinner,drive = <0>; allwinner,pull = <0>; }; uart6_pins_a: uart6@0 { allwinner,pins = "PI12", "PI13"; allwinner,function = "uart6"; allwinner,drive = <0>; allwinner,pull = <0>; }; uart7_pins_a: uart7@0 { allwinner,pins = "PI20", "PI21"; allwinner,function = "uart7"; allwinner,drive = <0>; allwinner,pull = <0>; }; i2c0_pins_a: i2c0@0 { allwinner,pins = "PB0", "PB1"; allwinner,function = "i2c0"; allwinner,drive = <0>; allwinner,pull = <0>; }; i2c1_pins_a: i2c1@0 { allwinner,pins = "PB18", "PB19"; allwinner,function = "i2c1"; allwinner,drive = <0>; allwinner,pull = <0>; }; i2c2_pins_a: i2c2@0 { allwinner,pins = "PB20", "PB21"; allwinner,function = "i2c2"; allwinner,drive = <0>; allwinner,pull = <0>; }; emac_pins_a: emac0@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", "PA16"; allwinner,function = "emac"; allwinner,drive = <0>; allwinner,pull = <0>; }; clk_out_a_pins_a: clk_out_a@0 { allwinner,pins = "PI12"; allwinner,function = "clk_out_a"; allwinner,drive = <0>; allwinner,pull = <0>; }; clk_out_b_pins_a: clk_out_b@0 { allwinner,pins = "PI13"; allwinner,function = "clk_out_b"; allwinner,drive = <0>; allwinner,pull = <0>; }; gmac_pins_mii_a: gmac_mii@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", "PA16"; allwinner,function = "gmac"; allwinner,drive = <0>; allwinner,pull = <0>; }; gmac_pins_rgmii_a: gmac_rgmii@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA10", "PA11", "PA12", "PA13", "PA15", "PA16"; allwinner,function = "gmac"; /* * data lines in RGMII mode use DDR mode * and need a higher signal drive strength */ allwinner,drive = <3>; allwinner,pull = <0>; }; spi1_pins_a: spi1@0 { allwinner,pins = "PI16", "PI17", "PI18", "PI19"; allwinner,function = "spi1"; allwinner,drive = <0>; allwinner,pull = <0>; }; spi2_pins_a: spi2@0 { allwinner,pins = "PC19", "PC20", "PC21", "PC22"; allwinner,function = "spi2"; allwinner,drive = <0>; allwinner,pull = <0>; }; mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; allwinner,function = "mmc0"; allwinner,drive = <2>; allwinner,pull = <0>; }; mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { allwinner,pins = "PH1"; allwinner,function = "gpio_in"; allwinner,drive = <0>; allwinner,pull = <1>; }; mmc3_pins_a: mmc3@0 { allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; allwinner,function = "mmc3"; allwinner,drive = <2>; allwinner,pull = <0>; }; ir0_pins_a: ir0@0 { allwinner,pins = "PB3","PB4"; allwinner,function = "ir0"; allwinner,drive = <0>; allwinner,pull = <0>; }; ir1_pins_a: ir1@0 { allwinner,pins = "PB22","PB23"; allwinner,function = "ir1"; allwinner,drive = <0>; allwinner,pull = <0>; }; }; timer@01c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <0 22 4>, <0 23 4>, <0 24 4>, <0 25 4>, <0 67 4>, <0 68 4>; clocks = <&osc24M>; }; wdt: watchdog@01c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; rtc: rtc@01c20d00 { compatible = "allwinner,sun7i-a20-rtc"; reg = <0x01c20d00 0x20>; interrupts = <0 24 4>; }; pwm: pwm@01c20e00 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; #pwm-cells = <3>; status = "disabled"; }; ir0: ir@01c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; clock-names = "apb", "ir"; interrupts = <0 5 4>; reg = <0x01c21800 0x40>; status = "disabled"; }; ir1: ir@01c21c00 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 7>, <&ir1_clk>; clock-names = "apb", "ir"; interrupts = <0 6 4>; reg = <0x01c21c00 0x40>; status = "disabled"; }; sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; }; rtp: rtp@01c25000 { compatible = "allwinner,sun4i-a10-ts"; reg = <0x01c25000 0x100>; interrupts = <0 29 4>; }; uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <0 1 4>; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 16>; status = "disabled"; }; uart1: serial@01c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <0 2 4>; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 17>; status = "disabled"; }; uart2: serial@01c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <0 3 4>; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 18>; status = "disabled"; }; uart3: serial@01c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <0 4 4>; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 19>; status = "disabled"; }; uart4: serial@01c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <0 17 4>; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 20>; status = "disabled"; }; uart5: serial@01c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <0 18 4>; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 21>; status = "disabled"; }; uart6: serial@01c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <0 19 4>; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 22>; status = "disabled"; }; uart7: serial@01c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <0 20 4>; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 23>; status = "disabled"; }; i2c0: i2c@01c2ac00 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <0 7 4>; clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@01c2b000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <0 8 4>; clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@01c2b400 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <0 9 4>; clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c3: i2c@01c2b800 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = <0 88 4>; clocks = <&apb1_gates 3>; clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c4: i2c@01c2c000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = <0 89 4>; clocks = <&apb1_gates 15>; clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; gmac: ethernet@01c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>; interrupts = <0 85 4>; interrupt-names = "macirq"; clocks = <&ahb_gates 49>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; snps,pbl = <2>; snps,fixed-burst; snps,force_sf_dma_mode; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; hstimer@01c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <0 81 4>, <0 82 4>, <0 83 4>, <0 84 4>; clocks = <&ahb_gates 28>; }; gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x1000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; #interrupt-cells = <3>; interrupts = <1 9 0xf04>; }; }; };