/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * SPDX-License-Identifier:     GPL-2.0+
 *
 */

#include <dt-bindings/clock/imx7d-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx7d-pinfunc.h"
#include "imx7d-pinfunc-lpsr.h"
#include "skeleton.dtsi"

/ {
	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		serial6 = &uart7;
		spi1 = &qspi1;
		spi2 = &ecspi1;
		spi3 = &ecspi2;
		spi4 = &ecspi3;
		spi5 = &ecspi4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			operating-points = <
				/* KHz	uV */
				1200000	1225000
				996000	1075000
				792000	975000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
				 <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
			clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	intc: interrupt-controller@31001000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x31001000 0x1000>,
		      <0x31002000 0x100>;
		interrupt-parent = <&intc>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil: clock@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "ckil";
		};

		osc: clock@1 {
			compatible = "fixed-clock";
			reg = <1>;
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "osc";
		};

	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&intc>;
		clock-frequency = <8000000>;
	};

	etr@0,30086000 {
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0x30086000 0x1000>;

		coresight-default-sink;
		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
		clock-names = "apb_pclk";

		port{
			etr_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port1>;
			};
		};
	};

	tpiu@0,30087000 {
		compatible = "arm,coresight-tpiu", "arm,primecell";
		reg = <0x30087000 0x1000>;

		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
		clock-names = "apb_pclk";
		port {
			tpiu_in_port: endpoint@0 {
				slave-mode;
				remote-endpoint = <&replicator_out_port1>;
			};
		};
	};

	replicator {
		/* non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell".
		 */
		compatible = "arm,coresight-replicator";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&etr_in_port>;
				};
			};

			/* replicator input port */
			port@2 {
				reg = <0>;
				replicator_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&etf_out_port>;
				};
			};
		};
	};

	etf@0,30084000 {
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0x30084000 0x1000>;
		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
		clock-names = "apb_pclk";

		ports{
			#address-cells = <1>;
			#size-cells = <0>;

			port@0{
				reg = <0>;
				etf_in_port: endpoint {
					slave-mode;
					remote-endpoint = <&hugo_funnel_out_port0>;
				};
			};
			port@1{
				reg = <0>;
				etf_out_port: endpoint {
					remote-endpoint = <&replicator_in_port0>;
				};
			};
		};
	};

	funnel@1,30083000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0x30083000 0x1000>;
		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
		clock-names = "apb_pclk";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			/* funnel input ports */
			port@0 {
				reg = <0>;
				hugo_funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&ca_funnel_out_port0>;
				};
			};
			port@1 {
				reg = <1>;
				hugo_funnel_in_port1: endpoint {
					slave-mode; /* M4 input */
				};
			};
			port@2 {
				reg = <0>;
				hugo_funnel_out_port0: endpoint {
					remote-endpoint = <&etf_in_port>;
				};
			};
		};
	};

	funnel@0,30041000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0x30041000 0x1000>;
		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* funnel input ports */
			port@0 {
				reg = <0>;
				ca_funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&etm0_out_port>;
				};
			};

			port@1 {
				reg = <1>;
				ca_funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint = <&etm1_out_port>;
				};
			};

			/* funnel output port */
			port@2 {
				reg = <0>;
				ca_funnel_out_port0: endpoint {
					remote-endpoint =
						<&hugo_funnel_in_port0>;
				};
			};
		};
	};

	etm@0,3007c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0x3007c000 0x1000>;

		cpu = <&cpu0>;
		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
		clock-names = "apb_pclk";
		port {
			etm0_out_port: endpoint {
				remote-endpoint = <&ca_funnel_in_port0>;
			};
		};
	};

	etm@1,3007d000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0x3007d000 0x1000>;
		arm,primecell-periphid =  <0xbb956>;

		cpu = <&cpu1>;
		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
		clock-names = "apb_pclk";
		port {
			etm1_out_port: endpoint {
				remote-endpoint = <&ca_funnel_in_port1>;
			};
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x14000000>;
			linux,cma-default;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gpc>;
		ranges;

		busfreq {
			compatible = "fsl,imx_busfreq";
			fsl,max_ddr_freq = <533000000>;
			clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>,
				<&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>,
				<&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>,
				<&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>,
				<&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>,
				<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>;
			clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel",
					"pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi";
			interrupts = <0 112 0x04>, <0 113 0x04>;
			interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
		};

		caam_sm: caam-sm@00100000 {
			 compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
			 reg = <0x00100000 0x3fff>;
		};

		irq_sec_vio: caam_secvio {
			compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			jtag-tamper = "disabled";
			watchdog-tamper = "enabled";
			internal-boot-tamper = "enabled";
			external-pin-tamper = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ocrams_ddr: sram@00900000 {
			compatible = "fsl,ddr-lpm-sram";
			reg = <0x00900000 0x1000>;
			clocks = <&clks IMX7D_OCRAM_CLK>;
		};

		ocram: sram@901000 {
			compatible = "mmio-sram";
			reg = <0x00901000 0x1f000>;
			clocks = <&clks IMX7D_OCRAM_CLK>;
		};

		ocrams: sram@00180000 {
			compatible = "fsl,lpm-sram";
			reg = <0x00180000 0x8000>;
			clocks = <&clks IMX7D_OCRAM_S_CLK>;
			status = "disabled";
		};

		ocrams_mf: sram-mf@00900000 {
			compatible = "fsl,mega-fast-sram";
			reg = <0x00900000 0x20000>;
			clocks = <&clks IMX7D_OCRAM_CLK>;
		};

		dma_apbh: dma-apbh@33000000 {
			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x33000000 0x2000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
				<&clks IMX7D_NAND_ROOT_CLK>;
			clock-names = "dma_apbh_bch", "dma_apbh_io";
		};

		gpmi: gpmi-nand@33002000{
			compatible = "fsl,imx7d-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clks IMX7D_NAND_ROOT_CLK>,
				<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>;
			clock-names = "gpmi_io", "gpmi_bch_apb";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		aips1: aips-bus@30000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x30000000 0x400000>;
			ranges;

			gpio1: gpio@30200000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@30250000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30250000 0x10000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio7: gpio@30260000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30260000 0x10000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			iomuxc_lpsr_gpr: lpsr-gpr@30270000 {
				compatible = "fsl,imx7d-lpsr-gpr";
				reg = <0x30270000 0x10000>;
			};

			wdog1: wdog@30280000 {
				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
			};

			wdog2: wdog@30290000 {
				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
				reg = <0x30290000 0x10000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
				status = "disabled";
			};

			wdog3: wdog@302a0000 {
				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
				reg = <0x302a0000 0x10000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
				status = "disabled";
			};

			wdog4: wdog@302b0000 {
				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
				reg = <0x302b0000 0x10000>;
				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
				status = "disabled";
			};

			iomuxc_lpsr: iomuxc-lpsr@302c0000 {
				compatible = "fsl,imx7d-iomuxc-lpsr";
				reg = <0x302c0000 0x10000>;
				fsl,input-sel = <&iomuxc>;
			};

			gpt1: gpt@302d0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx31-gpt";
				reg = <0x302d0000 0x10000>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
					<&clks IMX7D_GPT1_ROOT_CLK>,
					<&clks IMX7D_GPT_3M_CLK>;
				clock-names = "ipg", "per", "osc_per";
			};

			gpt2: gpt@302e0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx31-gpt";
				reg = <0x302e0000 0x10000>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_GPT2_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt3: gpt@302f0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx31-gpt";
				reg = <0x302f0000 0x10000>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_GPT3_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt4: gpt@30300000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx31-gpt";
				reg = <0x30300000 0x10000>;
				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_GPT4_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			kpp: kpp@30320000 {
				compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
				reg = <0x30320000 0x10000>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>;
				status = "disabled";
			};

			iomuxc: iomuxc@30330000 {
				compatible = "fsl,imx7d-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			gpr: iomuxc-gpr@30340000 {
				compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
				reg = <0x30340000 0x10000>;
			};

			mqs: mqs {
				compatible = "fsl,imx6sx-mqs";
				gpr = <&gpr>;
				status = "disabled";
			};

			ocotp: ocotp-ctrl@30350000 {
				compatible = "fsl,imx7d-ocotp", "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clks IMX7D_OCOTP_CLK>;
			};

			anatop: anatop@30360000 {
				compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
					"syscon", "simple-bus";
				reg = <0x30360000 0x10000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

				reg_1p0d: regulator-vdd1p0d@210 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p0d";
					regulator-min-microvolt = <800000>;
					regulator-max-microvolt = <1200000>;
					anatop-reg-offset = <0x210>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <8>;
					anatop-min-voltage = <800000>;
					anatop-max-voltage = <1200000>;
					anatop-enable-bit = <0>;
				};

				reg_1p2: regulator-vdd1p2@220 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p2";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1300000>;
					anatop-reg-offset = <0x220>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <8>;
					anatop-min-voltage = <1100000>;
					anatop-max-voltage = <1300000>;
					anatop-enable-bit = <31>;
				};
			};

			tempmon: tempmon {
				compatible = "fsl,imx7d-tempmon";
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
				fsl,tempmon =<&anatop>;
				fsl,tempmon-data = <&ocotp>;
				clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
			};

			caam_snvs: caam-snvs@30370000 {
				compatible = "fsl,imx6q-caam-snvs";
				reg = <0x30370000 0x10000>;
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
				reg = <0x30370000 0x10000>;

				snvs_rtc: snvs-rtc-lp{
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap =<&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					linux,keycode = <KEY_POWER>;
					wakeup;
				};

				snvs_poweroff: snvs-poweroff {
					compatible = "syscon-poweroff";
					regmap = <&snvs>;
					offset = <0x38>;
					mask = <0x61>;
				};
			};

			clks: ccm@30380000 {
				compatible = "fsl,imx7d-ccm";
				reg = <0x30380000 0x10000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc>;
				clock-names = "ckil", "osc";
			};

			src: src@30390000 {
				compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
				reg = <0x30390000 0x10000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@303a0000 {
				compatible = "fsl,imx7d-gpc";
				reg = <0x303a0000 0x10000>;
				interrupt-controller;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <3>;
				interrupt-parent = <&intc>;
				fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>;
				mipi-phy-supply = <&reg_1p0d>;
				pcie-phy-supply = <&reg_1p0d>;
				vcc-supply = <&reg_1p2>;
			};
		};

		aips2: aips-bus@30400000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x30400000 0x400000>;
			ranges;

			adc1: adc@30610000 {
				compatible = "fsl,imx7d-adc";
				reg = <0x30610000 0x10000>;
				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
				num-channels = <4>;
				clock-names = "adc";
				status = "disabled";
			};

			adc2: adc@30620000 {
				compatible = "fsl,imx7d-adc";
				reg = <0x30620000 0x10000>;
				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
				num-channels = <4>;
				clock-names = "adc";
				status = "disabled";
			};

			ecspi4: ecspi@30630000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-ecspi", "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
				reg = <0x30630000 0x10000>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
					<&clks IMX7D_ECSPI4_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			flextimer1: flextimer@30640000 {
				compatible = "fsl,imx7d-flextimer";
				reg = <0x30640000 0x10000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			flextimer2: flextimer@30650000 {
				compatible = "fsl,imx7d-flextimer";
				reg = <0x30650000 0x10000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			pwm1: pwm@30660000 {
				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
				reg = <0x30660000 0x10000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
					<&clks IMX7D_PWM1_ROOT_CLK>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm2: pwm@30670000 {
				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
				reg = <0x30670000 0x10000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
					<&clks IMX7D_PWM2_ROOT_CLK>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm3: pwm@30680000 {
				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
				reg = <0x30680000 0x10000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
					<&clks IMX7D_PWM3_ROOT_CLK>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm4: pwm@30690000 {
				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
				reg = <0x30690000 0x10000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
					<&clks IMX7D_PWM4_ROOT_CLK>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			system_counter_rd: system-counter-rd@306a0000 {
				compatible = "fsl,imx7d-system-counter-rd";
				reg = <0x306a0000 0x10000>;
				status = "disabled";
			};

			system_counter_cmp: system-counter-cmp@306b0000 {
				compatible = "fsl,imx7d-system-counter-cmp";
				reg = <0x306b0000 0x10000>;
				status = "disabled";
			};

			system_counter_ctrl: system-counter-ctrl@306c0000 {
				compatible = "fsl,imx7d-system-counter-ctrl";
				reg = <0x306c0000 0x10000>;
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			pcie_phy: pcie-phy@306d0000 {
				compatible = "fsl,imx-pcie-phy";
				reg = <0x306d0000 0x10000>;
				status = "disabled";
			};

			epdc: epdc@306f0000 {
				compatible = "fsl,imx7d-epdc";
				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x306f0000 0x10000>;
				clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
				clock-names = "epdc_axi", "epdc_pix";
				epdc-ram = <&gpr 0x4 30>;
				status = "disabled";
			};

			epxp: epxp@30700000 {
				compatible = "fsl,imx7d-pxp-dma";
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x30700000 0x10000>;
				clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>;
				clock-names = "pxp_ipg", "pxp_axi";
				status = "disabled";
			};

			csi1: csi@30710000 {
				compatible = "fsl,imx7d-csi", "fsl,imx6s-csi";
				reg = <0x30710000 0x10000>;
				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CSI_MCLK_ROOT_CLK>,
					<&clks IMX7D_CLK_DUMMY>;
				clock-names = "disp-axi", "csi_mclk", "disp_dcic";
				status = "disabled";
			};

			lcdif: lcdif@30730000 {
				compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
				reg = <0x30730000 0x10000>;
				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
					<&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CLK_DUMMY>;
				clock-names = "pix", "axi", "disp_axi";
				status = "disabled";
			};

			mipi_csi: mipi-csi@30750000 {
				compatible = "fsl,imx7d-mipi-csi";
				reg = <0x30750000 0x10000>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
						<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
				clock-names = "mipi_clk", "phy_clk";
				mipi-phy-supply = <&reg_1p0d>;
				csis-phy-reset = <&src 0x28 2>;
				bus-width = <4>;
				status = "disabled";
			};

			mipi_dsi: mipi-dsi@30760000 {
				compatible = "fsl,imx7d-mipi-dsi";
				reg = <0x30760000 0x10000>;
				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
					<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
				clock-names = "mipi_cfg_clk", "mipi_pllref_clk";
				mipi-phy-supply = <&reg_1p0d>;
				status = "disabled";
			};

			ddrc: ddrc@307a0000 {
				compatible = "fsl,imx7-ddrc";
				reg = <0x307a0000 0x10000>;
			};
		};

		aips3: aips-bus@30800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x30800000 0x400000>;
			ranges;

			spba-bus@30800000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30800000 0x100000>;
				ranges;

				ecspi1: ecspi@30820000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx7d-ecspi", "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x30820000 0x10000>;
					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
						<&clks IMX7D_ECSPI1_ROOT_CLK>;
					clock-names = "ipg", "per";
					dmas = <&sdma 0 7 1>, <&sdma 1 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi2: ecspi@30830000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx7d-ecspi", "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x30830000 0x10000>;
					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
						<&clks IMX7D_ECSPI2_ROOT_CLK>;
					clock-names = "ipg", "per";
					dmas = <&sdma 2 7 1>, <&sdma 3 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi3: ecspi@30840000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx7d-ecspi", "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x30840000 0x10000>;
					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
						<&clks IMX7D_ECSPI3_ROOT_CLK>;
					clock-names = "ipg", "per";
					dmas = <&sdma 4 7 1>, <&sdma 5 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart1: serial@30860000 {
					compatible = "fsl,imx7d-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x30860000 0x10000>;
					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_UART1_ROOT_CLK>,
						<&clks IMX7D_UART1_ROOT_CLK>;
					clock-names = "ipg", "per";
					dmas = <&sdma 22 4 0>, <&sdma 23 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart2: serial@30890000 {
					compatible = "fsl,imx7d-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x30890000 0x10000>;
					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_UART2_ROOT_CLK>,
						<&clks IMX7D_UART2_ROOT_CLK>;
					clock-names = "ipg", "per";
					dmas = <&sdma 24 4 0>, <&sdma 25 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart3: serial@30880000 {
					compatible = "fsl,imx7d-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x30880000 0x10000>;
					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_UART3_ROOT_CLK>,
						<&clks IMX7D_UART3_ROOT_CLK>;
					clock-names = "ipg", "per";
					dmas = <&sdma 26 4 0>, <&sdma 27 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai1: sai@308a0000 {
					compatible = "fsl,imx7d-sai",
						     "fsl,imx6sx-sai";
					reg = <0x308a0000 0x10000>;
					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_SAI1_IPG_CLK>,
						<&clks IMX7D_CLK_DUMMY>,
						<&clks IMX7D_SAI1_ROOT_CLK>,
						<&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
					status = "disabled";
				};

				sai2: sai@308b0000 {
					compatible = "fsl,imx7d-sai",
						     "fsl,imx6sx-sai";
					reg = <0x308b0000 0x10000>;
					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_SAI2_IPG_CLK>,
						<&clks IMX7D_CLK_DUMMY>,
						<&clks IMX7D_SAI2_ROOT_CLK>,
						<&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
					status = "disabled";
				};

				sai3: sai@308c0000 {
					compatible = "fsl,imx7d-sai",
						     "fsl,imx6sx-sai";
					reg = <0x308c0000 0x10000>;
					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_SAI3_IPG_CLK>,
						<&clks IMX7D_CLK_DUMMY>,
						<&clks IMX7D_SAI3_ROOT_CLK>,
						<&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
					status = "disabled";
				};
			};

			crypto: caam@30900000 {
				compatible = "fsl,imx7d-caam", "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30900000 0x40000>;
				ranges = <0 0x30900000 0x40000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CAAM_CLK>,
					<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
				clock-names = "caam_ipg", "caam_aclk";

				sec_jr0: jr0@1000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x1000 0x1000>;
					 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr1@2000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x2000 0x1000>;
					 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr2: jr2@3000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x3000 0x1000>;
					 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			flexcan1: can@30a00000 {
				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
				reg = <0x30a00000 0x10000>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CAN1_ROOT_CLK>;
				clock-names = "ipg", "per";
				stop-mode = <&gpr 0x10 1 0x10 17>;
				status = "disabled";
			};

			flexcan2: can@30a10000 {
				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
				reg = <0x30a10000 0x10000>;
				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CAN2_ROOT_CLK>;
				clock-names = "ipg", "per";
				stop-mode = <&gpr 0x10 2 0x10 18>;
				status = "disabled";
			};

			i2c1: i2c@30a20000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART4_ROOT_CLK>,
					<&clks IMX7D_UART4_ROOT_CLK>;
				clock-names = "ipg", "per";
				dmas = <&sdma 28 4 0>, <&sdma 29 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart5: serial@30a70000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x30a70000 0x10000>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART5_ROOT_CLK>,
					<&clks IMX7D_UART5_ROOT_CLK>;
				clock-names = "ipg", "per";
				dmas = <&sdma 30 4 0>, <&sdma 31 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart6: serial@30a80000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x30a80000 0x10000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART6_ROOT_CLK>,
					<&clks IMX7D_UART6_ROOT_CLK>;
				clock-names = "ipg", "per";
				dmas = <&sdma 32 4 0>, <&sdma 33 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart7: serial@30a90000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x30a90000 0x10000>;
				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART7_ROOT_CLK>,
					<&clks IMX7D_UART7_ROOT_CLK>;
				clock-names = "ipg", "per";
				dmas = <&sdma 34 4 0>, <&sdma 35 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			mu: mu@30aa0000 {
				compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu";
				reg = <0x30aa0000 0x10000>;
				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_MU_ROOT_CLK>;
				clock-names = "mu";
				status = "okay";
			};

			rpmsg: rpmsg{
				compatible = "fsl,imx7d-rpmsg";
				status = "disabled";
			};

			sema4: sema4@30ac0000 {
				compatible = "fsl,imx7d-sema4";
				reg = <0x30ac0000 0x10000>;
				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>;
				clock-names = "sema4";
				status = "okay";
			};

			usbotg1: usb@30b10000 {
				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
				reg = <0x30b10000 0x200>;
				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_USB_CTRL_CLK>;
				fsl,usbphy = <&usbphy_nop1>;
				fsl,usbmisc = <&usbmisc1 0>;
				phy-clkgate-delay-us = <400>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbotg2: usb@30b20000 {
				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
				reg = <0x30b20000 0x200>;
				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_USB_CTRL_CLK>;
				fsl,usbphy = <&usbphy_nop2>;
				fsl,usbmisc = <&usbmisc2 0>;
				phy-clkgate-delay-us = <400>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbh: usb@30b30000 {
				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
				reg = <0x30b30000 0x200>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_USB_CTRL_CLK>;
				fsl,usbphy = <&usbphy_nop3>;
				fsl,usbmisc = <&usbmisc3 0>;
				phy_type = "hsic";
				dr_mode = "host";
				phy-clkgate-delay-us = <400>;
				status = "disabled";
			};

			usbmisc1: usbmisc@30b10200 {
				#index-cells = <1>;
				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x30b10200 0x200>;
			};

			usbmisc2: usbmisc@30b20200 {
				#index-cells = <1>;
				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x30b20200 0x200>;
			};

			usbmisc3: usbmisc@30b30200 {
				#index-cells = <1>;
				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x30b30200 0x200>;
			};

			usbphy_nop1: usbphy_nop1 {
				compatible = "usb-nop-xceiv";
				clocks = <&clks IMX7D_USB_PHY1_CLK>;
				clock-names = "main_clk";
			};

			usbphy_nop2: usbphy_nop2 {
				compatible = "usb-nop-xceiv";
				clocks = <&clks IMX7D_USB_PHY2_CLK>;
				clock-names = "main_clk";
			};

			usbphy_nop3: usbphy_nop3 {
				compatible = "usb-nop-xceiv";
				clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
				clock-names = "main_clk";
				vcc-supply = <&reg_1p2>;
			};

			usdhc1: usdhc@30b40000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
					<&clks IMX7D_USDHC1_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: usdhc@30b50000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sx-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
					<&clks IMX7D_USDHC2_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: usdhc@30b60000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sx-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
					<&clks IMX7D_USDHC3_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			sim1: sim@30b90000 {
				compatible = "fsl,imx7d-sim";
				reg = <0x30b90000 0x10000>;
				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_SIM1_ROOT_CLK>;
				clock-names = "sim";
				status = "disabled";
			};

			sim2: sim@30ba0000 {
				compatible = "fsl,imx7d-sim";
				reg = <0x30ba0000 0x10000>;
				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			qspi1: qspi@30bb0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-qspi";
				reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
					<&clks IMX7D_QSPI_ROOT_CLK>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			weim: weim@30bc0000 {
				compatible = "fsl,imx7d-weim", "fsl,imx6sx-weim", "fsl,imx6q-weim";
				reg = <0x30bc0000 0x10000>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_EIM_ROOT_CLK>;
				status = "disabled";
			};

			sdma: sdma@30bd0000 {
				compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
				reg = <0x30bd0000 0x10000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_SDMA_CORE_CLK>,
					<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				iram = <&ocram>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			fec1: ethernet@30be0000 {
				compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
					<&clks IMX7D_ENET_AXI_ROOT_CLK>,
					<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
					<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
				clock-names = "ipg", "ahb", "ptp",
					"enet_clk_ref", "enet_out";
				stop-mode = <&gpr 0x10 3>;
				fsl,num-tx-queues=<3>;
				fsl,num-rx-queues=<3>;
				fsl,wakeup_irq = <2>;
				status = "disabled";
			};

			fec2: ethernet@30bf0000 {
				compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
				reg = <0x30bf0000 0x10000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
					<&clks IMX7D_ENET_AXI_ROOT_CLK>,
					<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
					<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
				clock-names = "ipg", "ahb", "ptp",
					"enet_clk_ref", "enet_out";
				stop-mode = <&gpr 0x10 4>;
				fsl,num-tx-queues=<3>;
				fsl,num-rx-queues=<3>;
				fsl,wakeup_irq = <2>;
				status = "disabled";
			};
		};

		pcie: pcie@0x33800000 {
			compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
			reg = <0x33800000 0x4000>,  <0x4ff00000 0x80000>;
			reg-names = "dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges =  <0x81000000 0 0          0x4ff80000 0 0x00010000 /* downstream I/O 64KB */
				   0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
			num-lanes = <1>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
				<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
				<&clks IMX7D_PCIE_PHY_ROOT_CLK>;
			clock-names = "pcie", "pcie_bus", "pcie_phy";
			pcie-phy-supply = <&reg_1p0d>;
			status = "disabled";
		};
	};
};