From 5c952cf0245421feb4644f2e71487c0b2e1dbd13 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Sun, 10 Oct 2004 21:27:30 +0000
Subject: Patches by Scott McNutt, 24 Aug 2004: - Add support for Altera
 Nios-II processors. - Add support for Psyent PCI-5441 board. - Add support
 for Psyent PK1C20 board.

---
 lib_nios2/cache.S | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 lib_nios2/cache.S

(limited to 'lib_nios2/cache.S')

diff --git a/lib_nios2/cache.S b/lib_nios2/cache.S
new file mode 100644
index 0000000..eb7735a
--- /dev/null
+++ b/lib_nios2/cache.S
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+	.text
+
+	.global flush_dcache
+
+flush_dcache:
+	add	r5, r5, r4
+	movhi	r8, %hi(CFG_DCACHELINE_SIZE)
+	ori	r8, r8, %lo(CFG_DCACHELINE_SIZE)
+0:	flushd	0(r4)
+	add	r4, r4, r8
+	bltu	r4, r5, 0b
+	ret
+
+
+	.global flush_icache
+
+flush_icache:
+	add	r5, r5, r4
+	movhi	r8, %hi(CFG_ICACHELINE_SIZE)
+	ori	r8, r8, %lo(CFG_ICACHELINE_SIZE)
+1:	flushi	r4
+	add	r4, r4, r8
+	bltu	r4, r5, 1b
+	ret
+
+	.global flush_cache
+
+flush_cache:
+	add	r5, r5, r4
+	mov	r9, r4
+	mov	r10, r5
+
+	movhi	r8, %hi(CFG_DCACHELINE_SIZE)
+	ori	r8, r8, %lo(CFG_DCACHELINE_SIZE)
+0:	flushd	0(r4)
+	add	r4, r4, r8
+	bltu	r4, r5, 0b
+
+	mov	r4, r9
+	mov	r5, r10
+	movhi	r8, %hi(CFG_ICACHELINE_SIZE)
+	ori	r8, r8, %lo(CFG_ICACHELINE_SIZE)
+1:	flushi	r4
+	add	r4, r4, r8
+	bltu	r4, r5, 1b
+
+	sync
+	flushp
+	ret
-- 
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