From 55ae10f8dbdf306e210240937ee4d558c8590447 Mon Sep 17 00:00:00 2001 From: Bill Richardson Date: Sat, 20 Oct 2012 11:44:34 +0000 Subject: x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson Signed-off-by: Simon Glass --- include/pci.h | 123 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index eba122f..15f583f 100644 --- a/include/pci.h +++ b/include/pci.h @@ -67,7 +67,130 @@ #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ #define PCI_CLASS_DEVICE 0x0a /* Device class */ #define PCI_CLASS_CODE 0x0b /* Device class code */ +#define PCI_CLASS_CODE_TOO_OLD 0x00 +#define PCI_CLASS_CODE_STORAGE 0x01 +#define PCI_CLASS_CODE_NETWORK 0x02 +#define PCI_CLASS_CODE_DISPLAY 0x03 +#define PCI_CLASS_CODE_MULTIMEDIA 0x04 +#define PCI_CLASS_CODE_MEMORY 0x05 +#define PCI_CLASS_CODE_BRIDGE 0x06 +#define PCI_CLASS_CODE_COMM 0x07 +#define PCI_CLASS_CODE_PERIPHERAL 0x08 +#define PCI_CLASS_CODE_INPUT 0x09 +#define PCI_CLASS_CODE_DOCKING 0x0A +#define PCI_CLASS_CODE_PROCESSOR 0x0B +#define PCI_CLASS_CODE_SERIAL 0x0C +#define PCI_CLASS_CODE_WIRELESS 0x0D +#define PCI_CLASS_CODE_I2O 0x0E +#define PCI_CLASS_CODE_SATELLITE 0x0F +#define PCI_CLASS_CODE_CRYPTO 0x10 +#define PCI_CLASS_CODE_DATA 0x11 +/* Base Class 0x12 - 0xFE is reserved */ +#define PCI_CLASS_CODE_OTHER 0xFF + #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ +#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 +#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 +#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 +#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 +#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 +#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 +#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 +#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 +#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 +#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 +#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 +#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 +#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 +#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 +#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 +#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 +#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 +#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 +#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 +#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 +#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 +#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 +#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 +#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 +#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 +#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 +#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 +#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 +#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 +#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 +#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 +#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 +#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 +#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 +#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A +#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 +#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 +#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 +#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 +#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 +#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 +#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 +#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 +#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 +#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 +#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 +#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 +#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 +#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 +#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 +#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 +#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 +#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 +#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 +#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 +#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 +#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 +#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 +#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 +#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 +#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 +#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 +#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 +#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 +#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 +#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 +#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 +#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 +#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 +#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 +#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 +#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 +#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 +#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 +#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 +#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 +#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 +#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 +#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 +#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 +#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 +#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 +#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 +#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 +#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 +#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 +#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 +#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 +#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 +#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ -- cgit v1.1 From a7e6d5496c7981803482bfa6970eeda2954d3458 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 2 Dec 2012 03:44:44 +0000 Subject: x86: Enable ICH6 GPIO controller for coreboot Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass --- include/configs/coreboot.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index a010adc..fcfa7ed 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -138,6 +138,9 @@ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE +/* x86 GPIOs are accessed through a PCI device */ +#define CONFIG_INTEL_ICH6_GPIO + /*----------------------------------------------------------------------- * Command line configuration. */ @@ -150,6 +153,7 @@ #define CONFIG_CMD_ECHO #undef CONFIG_CMD_FLASH #define CONFIG_CMD_FPGA +#define CONFIG_CMD_GPIO #define CONFIG_CMD_IMI #undef CONFIG_CMD_IMLS #define CONFIG_CMD_IRQ -- cgit v1.1 From 34d6057be1a162ce6424314026af12f8963f2df2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 2 Dec 2012 04:49:55 +0000 Subject: x86: Enable CONFIG_CMD_ZBOOT for coreboot Enable this option to support booting a zImage. Signed-off-by: Simon Glass --- include/configs/coreboot.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index fcfa7ed..e45ecad 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -39,6 +39,7 @@ #define CONFIG_LAST_STAGE_INIT #define CONFIG_X86_NO_RESET_VECTOR #define CONFIG_SYS_VSNPRINTF +#define CONFIG_ZBOOT_32 /*----------------------------------------------------------------------- * Watchdog Configuration @@ -175,6 +176,8 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_ZBOOT + #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" -- cgit v1.1 From 40fef0490610686022f99b8e070df7ac761c11a0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 2 Dec 2012 04:55:18 +0000 Subject: Introduce arch_phys_memset which works like memset but on physical memory The default implementation of this function is just memset, but other implementations will be needed when physical memory isn't accessible by U-Boot using normal addressing mechanisms. Signed-off-by: Gabe Black Signed-off-by: Che-Liang Chiou Signed-off-by: Simon Glass --- include/physmem.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/physmem.h (limited to 'include') diff --git a/include/physmem.h b/include/physmem.h new file mode 100644 index 0000000..03d3a78 --- /dev/null +++ b/include/physmem.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + */ + +/* + * These functions work like memset but operate on physical memory which may + * not be accessible directly. + * + * @param s The physical address to start setting memory at. + * @param c The character to set each byte of the region to. + * @param n The number of bytes to set. + * + * @return The physical address of the memory which was set. + */ +phys_addr_t arch_phys_memset(phys_addr_t s, int c, phys_size_t n); -- cgit v1.1 From 300081aa68d705ce954c516751a9c03efa1fba5e Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 3 Dec 2012 13:58:12 +0000 Subject: x86: Emit port 80 post codes in show_boot_progress() This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- include/configs/coreboot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index e45ecad..94b6917 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -35,7 +35,7 @@ * (easy to change) */ #define CONFIG_SYS_COREBOOT -#undef CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_LAST_STAGE_INIT #define CONFIG_X86_NO_RESET_VECTOR #define CONFIG_SYS_VSNPRINTF -- cgit v1.1 From cbca883c46146e9b3128fcb51ab750089c47c241 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 3 Nov 2012 11:41:42 +0000 Subject: x86: coreboot: Enable video display Enable the display on coreboot, using CFB. Signed-off-by: Simon Glass --- include/configs/coreboot.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 94b6917..46b8d78 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -78,6 +78,7 @@ */ #define CONFIG_RTC_MC146818 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS /*----------------------------------------------------------------------- * Serial Configuration @@ -136,8 +137,13 @@ /*----------------------------------------------------------------------- * Video Configuration */ -#undef CONFIG_VIDEO -#undef CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO +#define CONFIG_VIDEO_COREBOOT +#define CONFIG_VIDEO_SW_CURSOR +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_I8042_KBD +#define CONFIG_CFB_CONSOLE +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* x86 GPIOs are accessed through a PCI device */ #define CONFIG_INTEL_ICH6_GPIO -- cgit v1.1 From d954a431ec4bbebc588ac810a1eb01f3512249a8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 5 Dec 2012 15:10:58 +0000 Subject: x86: Turn on support for EFI's GPT in the coreboot config This allows u-boot to figure out the partitions of a chrome-os install. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- include/configs/coreboot.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 46b8d78..06d2b2f 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -126,13 +126,16 @@ /************************************************************ * DISK Partition support ************************************************************/ +#define CONFIG_EFI_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_MAC_PARTITION #define CONFIG_ISO_PARTITION /* Experimental */ +#define CONFIG_CMD_PART #define CONFIG_CMD_CBFS #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE +#define CONFIG_PARTITION_UUIDS /*----------------------------------------------------------------------- * Video Configuration -- cgit v1.1 From ac426b7290e3a96c97fbc093f15cd0660e0edaf2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 5 Dec 2012 15:11:27 +0000 Subject: x86: Fix coreboot config to boot on Chromebook The config is current broken. It compiles but does not boot because IDE is enabled. Remove all IDE options, and enable SCSI instead. Also add a working boot command and Linux bootargs, and enable command line editing to make it easier to work with. Signed-off-by: Simon Glass --- include/configs/coreboot.h | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 06d2b2f..adeace0 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -39,7 +39,9 @@ #define CONFIG_LAST_STAGE_INIT #define CONFIG_X86_NO_RESET_VECTOR #define CONFIG_SYS_VSNPRINTF +#define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */ #define CONFIG_ZBOOT_32 +#define CONFIG_PHYSMEM /*----------------------------------------------------------------------- * Watchdog Configuration @@ -104,18 +106,9 @@ #define CONFIG_SYS_STDIO_DEREGISTER #define CONFIG_CBMEM_CONSOLE -/* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXBUS 1 -/* max. 1 drive per IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 - +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTOCOMPLETE #define CONFIG_SUPPORT_VFAT /************************************************************ @@ -181,14 +174,19 @@ #define CONFIG_CMD_SETGETDCR #define CONFIG_CMD_SOURCE #define CONFIG_CMD_XIMG -#define CONFIG_CMD_IDE +#define CONFIG_CMD_SCSI + #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 #define CONFIG_CMD_ZBOOT #define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" +#define CONFIG_BOOTARGS \ + "root=/dev/sdb3 init=/sbin/init rootwait ro" +#define CONFIG_BOOTCOMMAND \ + "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" + #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 -- cgit v1.1